Commit a314d5cb authored by Chris Wilson's avatar Chris Wilson

drm/i915: Before accessing an object via the cpu, flush GTT writes

If we want to read the pages directly via the CPU, we have to be sure
that we have to flush the writes via the GTT (as the CPU can not see
the address aliasing).
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20160818161718.27187-9-chris@chris-wilson.co.uk
parent 43394c7d
...@@ -622,6 +622,8 @@ int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, ...@@ -622,6 +622,8 @@ int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
if (ret) if (ret)
return ret; return ret;
i915_gem_object_flush_gtt_write_domain(obj);
/* If we're not in the cpu read domain, set ourself into the gtt /* If we're not in the cpu read domain, set ourself into the gtt
* read domain and manually flush cachelines (if required). This * read domain and manually flush cachelines (if required). This
* optimizes for the case when the gpu will dirty the data * optimizes for the case when the gpu will dirty the data
...@@ -662,6 +664,8 @@ int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, ...@@ -662,6 +664,8 @@ int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
if (ret) if (ret)
return ret; return ret;
i915_gem_object_flush_gtt_write_domain(obj);
/* If we're not in the cpu write domain, set ourself into the /* If we're not in the cpu write domain, set ourself into the
* gtt write domain and manually flush cachelines (as required). * gtt write domain and manually flush cachelines (as required).
* This optimizes for the case when the gpu will use the data * This optimizes for the case when the gpu will use the data
......
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