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Commit a413647b authored by Mike Frysinger's avatar Mike Frysinger
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Blackfin: pull updated anomaly lists from toolchain 

Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
Signed-off-by: default avatarBryan Wu <cooloney@kernel.org>
parent 648882d9
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Showing with 367 additions and 137 deletions
arch/blackfin/mach-bf518/include/mach/anomaly.h
View file @ a413647b
...@@ -6,14 +6,19 @@ ...@@ -6,14 +6,19 @@
* Licensed under the GPL-2 or later. * Licensed under the GPL-2 or later.
*/ */
/* This file shoule be up to date with: /* This file should be up to date with:
* - Revision B, 02/03/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List * - Revision B, 02/03/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
*/ */
/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */
#if __SILICON_REVISION__ < 0
# error will not work on BF518 silicon version
#endif
#ifndef _MACH_ANOMALY_H_ #ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_ #define _MACH_ANOMALY_H_
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ /* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
#define ANOMALY_05000074 (1) #define ANOMALY_05000074 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1) #define ANOMALY_05000122 (1)
...@@ -47,7 +52,7 @@ ...@@ -47,7 +52,7 @@
#define ANOMALY_05000435 (1) #define ANOMALY_05000435 (1)
/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */ /* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
#define ANOMALY_05000438 (1) #define ANOMALY_05000438 (1)
/* Preboot Cannot be Used to Program the PLL_DIV Register */ /* Preboot Cannot be Used to Alter the PLL_DIV Register */
#define ANOMALY_05000439 (1) #define ANOMALY_05000439 (1)
/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */ /* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
#define ANOMALY_05000440 (1) #define ANOMALY_05000440 (1)
...@@ -61,32 +66,56 @@ ...@@ -61,32 +66,56 @@
#define ANOMALY_05000453 (1) #define ANOMALY_05000453 (1)
/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */ /* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */
#define ANOMALY_05000455 (1) #define ANOMALY_05000455 (1)
/* False Hardware Error when RETI points to invalid memory */
#define ANOMALY_05000461 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
#define ANOMALY_05000119 (0)
#define ANOMALY_05000120 (0)
#define ANOMALY_05000125 (0) #define ANOMALY_05000125 (0)
#define ANOMALY_05000149 (0)
#define ANOMALY_05000158 (0) #define ANOMALY_05000158 (0)
#define ANOMALY_05000171 (0)
#define ANOMALY_05000179 (0)
#define ANOMALY_05000183 (0) #define ANOMALY_05000183 (0)
#define ANOMALY_05000198 (0) #define ANOMALY_05000198 (0)
#define ANOMALY_05000215 (0)
#define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0) #define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0)
#define ANOMALY_05000233 (0)
#define ANOMALY_05000242 (0)
#define ANOMALY_05000244 (0) #define ANOMALY_05000244 (0)
#define ANOMALY_05000248 (0)
#define ANOMALY_05000250 (0)
#define ANOMALY_05000261 (0) #define ANOMALY_05000261 (0)
#define ANOMALY_05000263 (0) #define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0) #define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0) #define ANOMALY_05000273 (0)
#define ANOMALY_05000274 (0)
#define ANOMALY_05000278 (0) #define ANOMALY_05000278 (0)
#define ANOMALY_05000285 (0) #define ANOMALY_05000285 (0)
#define ANOMALY_05000287 (0)
#define ANOMALY_05000301 (0)
#define ANOMALY_05000305 (0) #define ANOMALY_05000305 (0)
#define ANOMALY_05000307 (0) #define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0) #define ANOMALY_05000311 (0)
#define ANOMALY_05000312 (0) #define ANOMALY_05000312 (0)
#define ANOMALY_05000323 (0) #define ANOMALY_05000323 (0)
#define ANOMALY_05000353 (0) #define ANOMALY_05000353 (0)
#define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0) #define ANOMALY_05000363 (0)
#define ANOMALY_05000380 (0) #define ANOMALY_05000380 (0)
#define ANOMALY_05000386 (0) #define ANOMALY_05000386 (0)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000412 (0) #define ANOMALY_05000412 (0)
#define ANOMALY_05000432 (0) #define ANOMALY_05000432 (0)
#define ANOMALY_05000447 (0) #define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0) #define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
#define ANOMALY_05000450 (0)
#endif #endif
arch/blackfin/mach-bf537/include/mach/anomaly.h
View file @ a413647b
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
* Licensed under the GPL-2 or later. * Licensed under the GPL-2 or later.
*/ */
/* This file shoule be up to date with: /* This file should be up to date with:
* - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List * - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
*/ */
...@@ -36,77 +36,75 @@ ...@@ -36,77 +36,75 @@
/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ /* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
#define ANOMALY_05000074 (1) #define ANOMALY_05000074 (1)
/* DMA_RUN bit is not valid after a Peripheral Receive Channel DMA stops */ /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1) #define ANOMALY_05000119 (1)
/* Rx.H cannot be used to access 16-bit System MMR registers */ /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1) #define ANOMALY_05000122 (1)
/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ /* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
#define ANOMALY_05000157 (__SILICON_REVISION__ < 2) #define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
#define ANOMALY_05000167 (1)
/* PPI_DELAY not functional in PPI modes with 0 frame syncs */
#define ANOMALY_05000180 (1) #define ANOMALY_05000180 (1)
/* Instruction Cache Is Not Functional */ /* Instruction Cache Is Not Functional */
#define ANOMALY_05000237 (__SILICON_REVISION__ < 2) #define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */ /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
#define ANOMALY_05000244 (__SILICON_REVISION__ < 3) #define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
/* Spurious Hardware Error from an access in the shadow of a conditional branch */ /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1) #define ANOMALY_05000245 (1)
/* CLKIN Buffer Output Enable Reset Behavior Is Changed */ /* CLKIN Buffer Output Enable Reset Behavior Is Changed */
#define ANOMALY_05000247 (1) #define ANOMALY_05000247 (1)
/* Incorrect Bit-Shift of Data Word in Multichannel (TDM) mode in certain conditions */ /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
#define ANOMALY_05000250 (__SILICON_REVISION__ < 3) #define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
/* EMAC Tx DMA error after an early frame abort */ /* EMAC Tx DMA error after an early frame abort */
#define ANOMALY_05000252 (__SILICON_REVISION__ < 3) #define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
/* Maximum external clock speed for Timers */ /* Maximum External Clock Speed for Timers */
#define ANOMALY_05000253 (__SILICON_REVISION__ < 3) #define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT mode with external clock */ /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
#define ANOMALY_05000254 (__SILICON_REVISION__ > 2) #define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
/* Entering Hibernate Mode with RTC Seconds event interrupt not functional */ /* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
#define ANOMALY_05000255 (__SILICON_REVISION__ < 3) #define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
/* EMAC MDIO input latched on wrong MDC edge */ /* EMAC MDIO input latched on wrong MDC edge */
#define ANOMALY_05000256 (__SILICON_REVISION__ < 3) #define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
/* Interrupt/Exception during short hardware loop may cause bad instruction fetches */ /* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
#define ANOMALY_05000257 (__SILICON_REVISION__ < 3) #define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
/* Instruction Cache is corrupted when bits 9 and 12 of the ICPLB Data registers differ */ /* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2) #define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
/* ICPLB_STATUS MMR register may be corrupted */ /* ICPLB_STATUS MMR Register May Be Corrupted */
#define ANOMALY_05000260 (__SILICON_REVISION__ == 2) #define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
/* DCPLB_FAULT_ADDR MMR register may be corrupted */ /* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
#define ANOMALY_05000261 (__SILICON_REVISION__ < 3) #define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
/* Stores to data cache may be lost */ /* Stores To Data Cache May Be Lost */
#define ANOMALY_05000262 (__SILICON_REVISION__ < 3) #define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
/* Hardware loop corrupted when taking an ICPLB exception */ /* Hardware Loop Corrupted When Taking an ICPLB Exception */
#define ANOMALY_05000263 (__SILICON_REVISION__ == 2) #define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
/* CSYNC/SSYNC/IDLE causes infinite stall in second to last instruction in hardware loop */ /* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
#define ANOMALY_05000264 (__SILICON_REVISION__ < 3) #define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
/* Sensitivity to noise with slow input edge rates on external SPORT TX and RX clocks */ /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
#define ANOMALY_05000265 (1) #define ANOMALY_05000265 (1)
/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */ /* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */
#define ANOMALY_05000268 (__SILICON_REVISION__ < 3) #define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
/* High I/O activity causes output voltage of internal voltage regulator (VDDint) to decrease */ /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
#define ANOMALY_05000270 (__SILICON_REVISION__ < 3) #define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
/* Certain data cache write through modes fail for VDDint <=0.9V */ /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
#define ANOMALY_05000272 (1) #define ANOMALY_05000272 (1)
/* Writes to Synchronous SDRAM memory may be lost */ /* Writes to Synchronous SDRAM Memory May Be Lost */
#define ANOMALY_05000273 (__SILICON_REVISION__ < 3) #define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */ /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
#define ANOMALY_05000277 (__SILICON_REVISION__ < 3) #define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
/* Disabling Peripherals with DMA running may cause DMA system instability */ /* Disabling Peripherals with DMA Running May Cause DMA System Instability */
#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2)) #define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
/* SPI Master boot mode does not work well with Atmel Data flash devices */ /* SPI Master boot mode does not work well with Atmel Data flash devices */
#define ANOMALY_05000280 (1) #define ANOMALY_05000280 (1)
/* False Hardware Error Exception when ISR context is not restored */ /* False Hardware Error Exception When ISR Context Is Not Restored */
#define ANOMALY_05000281 (__SILICON_REVISION__ < 3) #define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
/* Memory DMA corruption with 32-bit data and traffic control */ /* Memory DMA Corruption with 32-Bit Data and Traffic Control */
#define ANOMALY_05000282 (__SILICON_REVISION__ < 3) #define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ /* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
#define ANOMALY_05000283 (__SILICON_REVISION__ < 3) #define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */ /* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */
#define ANOMALY_05000285 (__SILICON_REVISION__ < 3) #define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
/* SPORTs may receive bad data if FIFOs fill up */ /* SPORTs May Receive Bad Data If FIFOs Fill Up */
#define ANOMALY_05000288 (__SILICON_REVISION__ < 3) #define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
/* Memory to memory DMA source/destination descriptors must be in same memory space */ /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
#define ANOMALY_05000301 (1) #define ANOMALY_05000301 (1)
/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
#define ANOMALY_05000304 (__SILICON_REVISION__ < 3) #define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
...@@ -116,11 +114,11 @@ ...@@ -116,11 +114,11 @@
#define ANOMALY_05000307 (__SILICON_REVISION__ < 3) #define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
/* Writing UART_THR while UART clock is disabled sends erroneous start bit */ /* Writing UART_THR while UART clock is disabled sends erroneous start bit */
#define ANOMALY_05000309 (__SILICON_REVISION__ < 3) #define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
/* False hardware errors caused by fetches at the boundary of reserved memory */ /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1) #define ANOMALY_05000310 (1)
/* Errors when SSYNC, CSYNC, or loads to LT, LB and LC registers are interrupted */ /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (1) #define ANOMALY_05000312 (1)
/* PPI is level sensitive on first transfer */ /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
#define ANOMALY_05000313 (1) #define ANOMALY_05000313 (1)
/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ /* Killed System MMR Write Completes Erroneously On Next System MMR Access */
#define ANOMALY_05000315 (__SILICON_REVISION__ < 3) #define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
...@@ -156,24 +154,46 @@ ...@@ -156,24 +154,46 @@
#define ANOMALY_05000426 (1) #define ANOMALY_05000426 (1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1) #define ANOMALY_05000443 (1)
/* False Hardware Error when RETI points to invalid memory */
#define ANOMALY_05000461 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
#define ANOMALY_05000120 (0)
#define ANOMALY_05000125 (0) #define ANOMALY_05000125 (0)
#define ANOMALY_05000149 (0)
#define ANOMALY_05000158 (0) #define ANOMALY_05000158 (0)
#define ANOMALY_05000171 (0)
#define ANOMALY_05000179 (0)
#define ANOMALY_05000183 (0) #define ANOMALY_05000183 (0)
#define ANOMALY_05000198 (0) #define ANOMALY_05000198 (0)
#define ANOMALY_05000215 (0)
#define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0) #define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0)
#define ANOMALY_05000233 (0)
#define ANOMALY_05000242 (0)
#define ANOMALY_05000248 (0)
#define ANOMALY_05000266 (0) #define ANOMALY_05000266 (0)
#define ANOMALY_05000274 (0)
#define ANOMALY_05000287 (0)
#define ANOMALY_05000311 (0) #define ANOMALY_05000311 (0)
#define ANOMALY_05000323 (0) #define ANOMALY_05000323 (0)
#define ANOMALY_05000353 (1) #define ANOMALY_05000353 (1)
#define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0) #define ANOMALY_05000363 (0)
#define ANOMALY_05000380 (0) #define ANOMALY_05000380 (0)
#define ANOMALY_05000386 (1) #define ANOMALY_05000386 (1)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000412 (0) #define ANOMALY_05000412 (0)
#define ANOMALY_05000430 (0)
#define ANOMALY_05000432 (0) #define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0) #define ANOMALY_05000435 (0)
#define ANOMALY_05000447 (0) #define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0) #define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
#define ANOMALY_05000450 (0)
#endif #endif
arch/blackfin/mach-bf538/include/mach/anomaly.h
View file @ a413647b
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
* Licensed under the GPL-2 or later. * Licensed under the GPL-2 or later.
*/ */
/* This file shoule be up to date with: /* This file should be up to date with:
* - Revision G, 09/18/2008; ADSP-BF538/BF538F Blackfin Processor Anomaly List * - Revision G, 09/18/2008; ADSP-BF538/BF538F Blackfin Processor Anomaly List
* - Revision L, 09/18/2008; ADSP-BF539/BF539F Blackfin Processor Anomaly List * - Revision L, 09/18/2008; ADSP-BF539/BF539F Blackfin Processor Anomaly List
*/ */
...@@ -14,17 +14,29 @@ ...@@ -14,17 +14,29 @@
#ifndef _MACH_ANOMALY_H_ #ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_ #define _MACH_ANOMALY_H_
/* We do not support old silicon - sorry */
#if __SILICON_REVISION__ < 4 #if __SILICON_REVISION__ < 4
# error will not work on BF538 silicon version 0.0, 0.1, 0.2, or 0.3 # error will not work on BF538/BF539 silicon version 0.0, 0.1, 0.2, or 0.3
#endif #endif
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #if defined(__ADSPBF538__)
# define ANOMALY_BF538 1
#else
# define ANOMALY_BF538 0
#endif
#if defined(__ADSPBF539__)
# define ANOMALY_BF539 1
#else
# define ANOMALY_BF539 0
#endif
/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
#define ANOMALY_05000074 (1) #define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1) #define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1) #define ANOMALY_05000122 (1)
/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ /* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
#define ANOMALY_05000166 (1) #define ANOMALY_05000166 (1)
/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
#define ANOMALY_05000179 (1) #define ANOMALY_05000179 (1)
...@@ -40,13 +52,13 @@ ...@@ -40,13 +52,13 @@
#define ANOMALY_05000229 (1) #define ANOMALY_05000229 (1)
/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ /* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
#define ANOMALY_05000233 (1) #define ANOMALY_05000233 (1)
/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */ /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
#define ANOMALY_05000244 (__SILICON_REVISION__ < 3) #define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1) #define ANOMALY_05000245 (1)
/* Maximum External Clock Speed for Timers */ /* Maximum External Clock Speed for Timers */
#define ANOMALY_05000253 (1) #define ANOMALY_05000253 (1)
/* DCPLB_FAULT_ADDR MMR register may be corrupted */ /* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
#define ANOMALY_05000261 (__SILICON_REVISION__ < 3) #define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
#define ANOMALY_05000270 (__SILICON_REVISION__ < 4) #define ANOMALY_05000270 (__SILICON_REVISION__ < 4)
...@@ -58,11 +70,11 @@ ...@@ -58,11 +70,11 @@
#define ANOMALY_05000277 (__SILICON_REVISION__ < 4) #define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ /* Disabling Peripherals with DMA Running May Cause DMA System Instability */
#define ANOMALY_05000278 (__SILICON_REVISION__ < 4) #define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
/* False Hardware Error Exception when ISR Context Is Not Restored */ /* False Hardware Error Exception When ISR Context Is Not Restored */
#define ANOMALY_05000281 (__SILICON_REVISION__ < 4) #define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
/* Memory DMA Corruption with 32-Bit Data and Traffic Control */ /* Memory DMA Corruption with 32-Bit Data and Traffic Control */
#define ANOMALY_05000282 (__SILICON_REVISION__ < 4) #define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ /* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
#define ANOMALY_05000283 (__SILICON_REVISION__ < 4) #define ANOMALY_05000283 (__SILICON_REVISION__ < 4)
/* SPORTs May Receive Bad Data If FIFOs Fill Up */ /* SPORTs May Receive Bad Data If FIFOs Fill Up */
#define ANOMALY_05000288 (__SILICON_REVISION__ < 4) #define ANOMALY_05000288 (__SILICON_REVISION__ < 4)
...@@ -80,14 +92,14 @@ ...@@ -80,14 +92,14 @@
#define ANOMALY_05000307 (__SILICON_REVISION__ < 4) #define ANOMALY_05000307 (__SILICON_REVISION__ < 4)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1) #define ANOMALY_05000310 (1)
/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (__SILICON_REVISION__ < 5) #define ANOMALY_05000312 (__SILICON_REVISION__ < 5)
/* PPI Is Level-Sensitive on First Transfer */ /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
#define ANOMALY_05000313 (__SILICON_REVISION__ < 4) #define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ /* Killed System MMR Write Completes Erroneously On Next System MMR Access */
#define ANOMALY_05000315 (__SILICON_REVISION__ < 4) #define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */ /* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
#define ANOMALY_05000318 (__SILICON_REVISION__ < 4) #define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4)
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
#define ANOMALY_05000355 (__SILICON_REVISION__ < 5) #define ANOMALY_05000355 (__SILICON_REVISION__ < 5)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
...@@ -114,23 +126,45 @@ ...@@ -114,23 +126,45 @@
#define ANOMALY_05000436 (__SILICON_REVISION__ > 3) #define ANOMALY_05000436 (__SILICON_REVISION__ > 3)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1) #define ANOMALY_05000443 (1)
/* False Hardware Error when RETI points to invalid memory */
#define ANOMALY_05000461 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
#define ANOMALY_05000120 (0)
#define ANOMALY_05000149 (0)
#define ANOMALY_05000158 (0) #define ANOMALY_05000158 (0)
#define ANOMALY_05000171 (0)
#define ANOMALY_05000198 (0) #define ANOMALY_05000198 (0)
#define ANOMALY_05000215 (0)
#define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0) #define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0)
#define ANOMALY_05000242 (0)
#define ANOMALY_05000248 (0)
#define ANOMALY_05000250 (0)
#define ANOMALY_05000254 (0)
#define ANOMALY_05000263 (0) #define ANOMALY_05000263 (0)
#define ANOMALY_05000274 (0)
#define ANOMALY_05000287 (0)
#define ANOMALY_05000305 (0) #define ANOMALY_05000305 (0)
#define ANOMALY_05000311 (0) #define ANOMALY_05000311 (0)
#define ANOMALY_05000323 (0) #define ANOMALY_05000323 (0)
#define ANOMALY_05000353 (1) #define ANOMALY_05000353 (1)
#define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0) #define ANOMALY_05000363 (0)
#define ANOMALY_05000380 (0) #define ANOMALY_05000380 (0)
#define ANOMALY_05000386 (1) #define ANOMALY_05000386 (1)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000412 (0) #define ANOMALY_05000412 (0)
#define ANOMALY_05000430 (0)
#define ANOMALY_05000432 (0) #define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0) #define ANOMALY_05000435 (0)
#define ANOMALY_05000447 (0) #define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0) #define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
#define ANOMALY_05000450 (0)
#endif #endif
arch/blackfin/mach-bf548/include/mach/anomaly.h
View file @ a413647b
...@@ -6,26 +6,31 @@ ...@@ -6,26 +6,31 @@
* Licensed under the GPL-2 or later. * Licensed under the GPL-2 or later.
*/ */
/* This file shoule be up to date with: /* This file should be up to date with:
* - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List * - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
*/ */
#ifndef _MACH_ANOMALY_H_ #ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_ #define _MACH_ANOMALY_H_
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ /* We do not support 0.0 or 0.1 silicon - sorry */
#if __SILICON_REVISION__ < 2
# error will not work on BF548 silicon version 0.0, or 0.1
#endif
/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
#define ANOMALY_05000074 (1) #define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1) #define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1) #define ANOMALY_05000122 (1)
/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1) #define ANOMALY_05000245 (1)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
#define ANOMALY_05000265 (1) #define ANOMALY_05000265 (1)
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
#define ANOMALY_05000272 (1) #define ANOMALY_05000272 (1)
/* False Hardware Error Exception when ISR context is not restored */ /* False Hardware Error Exception When ISR Context Is Not Restored */
#define ANOMALY_05000281 (__SILICON_REVISION__ < 1) #define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
#define ANOMALY_05000304 (__SILICON_REVISION__ < 1) #define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
...@@ -59,7 +64,7 @@ ...@@ -59,7 +64,7 @@
#define ANOMALY_05000340 (__SILICON_REVISION__ < 1) #define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ /* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
#define ANOMALY_05000344 (__SILICON_REVISION__ < 1) #define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
/* USB Calibration Value Is Not Intialized */ /* USB Calibration Value Is Not Initialized */
#define ANOMALY_05000346 (__SILICON_REVISION__ < 1) #define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
/* USB Calibration Value to use */ /* USB Calibration Value to use */
#define ANOMALY_05000346_value 0x5411 #define ANOMALY_05000346_value 0x5411
...@@ -147,11 +152,11 @@ ...@@ -147,11 +152,11 @@
#define ANOMALY_05000416 (1) #define ANOMALY_05000416 (1)
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ /* Multichannel SPORT Channel Misalignment Under Specific Configuration */
#define ANOMALY_05000425 (1) #define ANOMALY_05000425 (1)
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */ /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
#define ANOMALY_05000426 (1) #define ANOMALY_05000426 (1)
/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */ /* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
#define ANOMALY_05000427 (__SILICON_REVISION__ < 2) #define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Behaves as a Buffer Status Bit Instead of an IRQ Status Bit */ /* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
#define ANOMALY_05000429 (__SILICON_REVISION__ < 2) #define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
/* Software System Reset Corrupts PLL_LOCKCNT Register */ /* Software System Reset Corrupts PLL_LOCKCNT Register */
#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) #define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
...@@ -170,26 +175,49 @@ ...@@ -170,26 +175,49 @@
/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */ /* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
#define ANOMALY_05000449 (__SILICON_REVISION__ == 1) #define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
/* USB DMA Mode 1 Short Packet Data Corruption */ /* USB DMA Mode 1 Short Packet Data Corruption */
#define ANOMALY_05000450 (1 #define ANOMALY_05000450 (1)
/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
#define ANOMALY_05000456 (__SILICON_REVISION__ < 3)
/* False Hardware Error when RETI points to invalid memory */
#define ANOMALY_05000461 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
#define ANOMALY_05000120 (0)
#define ANOMALY_05000125 (0) #define ANOMALY_05000125 (0)
#define ANOMALY_05000149 (0)
#define ANOMALY_05000158 (0) #define ANOMALY_05000158 (0)
#define ANOMALY_05000171 (0)
#define ANOMALY_05000179 (0)
#define ANOMALY_05000183 (0) #define ANOMALY_05000183 (0)
#define ANOMALY_05000198 (0) #define ANOMALY_05000198 (0)
#define ANOMALY_05000215 (0)
#define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0) #define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0)
#define ANOMALY_05000233 (0)
#define ANOMALY_05000242 (0)
#define ANOMALY_05000244 (0) #define ANOMALY_05000244 (0)
#define ANOMALY_05000248 (0)
#define ANOMALY_05000250 (0)
#define ANOMALY_05000254 (0)
#define ANOMALY_05000261 (0) #define ANOMALY_05000261 (0)
#define ANOMALY_05000263 (0) #define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0) #define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0) #define ANOMALY_05000273 (0)
#define ANOMALY_05000274 (0)
#define ANOMALY_05000278 (0) #define ANOMALY_05000278 (0)
#define ANOMALY_05000287 (0)
#define ANOMALY_05000301 (0)
#define ANOMALY_05000305 (0) #define ANOMALY_05000305 (0)
#define ANOMALY_05000307 (0) #define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0) #define ANOMALY_05000311 (0)
#define ANOMALY_05000323 (0) #define ANOMALY_05000323 (0)
#define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0) #define ANOMALY_05000363 (0)
#define ANOMALY_05000380 (0) #define ANOMALY_05000380 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000412 (0) #define ANOMALY_05000412 (0)
#define ANOMALY_05000432 (0) #define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0) #define ANOMALY_05000435 (0)
......
arch/blackfin/mach-bf561/include/mach/anomaly.h
View file @ a413647b
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
* Licensed under the GPL-2 or later. * Licensed under the GPL-2 or later.
*/ */
/* This file shoule be up to date with: /* This file should be up to date with:
* - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List * - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List
*/ */
...@@ -18,11 +18,11 @@ ...@@ -18,11 +18,11 @@
# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4 # error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
#endif #endif
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ /* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
#define ANOMALY_05000074 (1) #define ANOMALY_05000074 (1)
/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
#define ANOMALY_05000099 (__SILICON_REVISION__ < 5) #define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
/* Trace Buffers may contain errors in emulation mode and/or exception, NMI, reset handlers */ /* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */
#define ANOMALY_05000116 (__SILICON_REVISION__ < 3) #define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
/* Testset instructions restricted to 32-bit aligned memory locations */ /* Testset instructions restricted to 32-bit aligned memory locations */
#define ANOMALY_05000120 (1) #define ANOMALY_05000120 (1)
...@@ -40,7 +40,7 @@ ...@@ -40,7 +40,7 @@
#define ANOMALY_05000136 (__SILICON_REVISION__ < 3) #define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
/* Allowing the SPORT RX FIFO to fill will cause an overflow */ /* Allowing the SPORT RX FIFO to fill will cause an overflow */
#define ANOMALY_05000140 (__SILICON_REVISION__ < 3) #define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ /* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */
#define ANOMALY_05000141 (__SILICON_REVISION__ < 3) #define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ /* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
#define ANOMALY_05000142 (__SILICON_REVISION__ < 3) #define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
...@@ -80,7 +80,7 @@ ...@@ -80,7 +80,7 @@
#define ANOMALY_05000163 (__SILICON_REVISION__ < 3) #define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ /* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
#define ANOMALY_05000166 (1) #define ANOMALY_05000166 (1)
/* Turning Serial Ports on with External Frame Syncs */ /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
#define ANOMALY_05000167 (1) #define ANOMALY_05000167 (1)
/* SDRAM auto-refresh and subsequent Power Ups */ /* SDRAM auto-refresh and subsequent Power Ups */
#define ANOMALY_05000168 (__SILICON_REVISION__ < 5) #define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
...@@ -164,7 +164,7 @@ ...@@ -164,7 +164,7 @@
#define ANOMALY_05000242 (__SILICON_REVISION__ < 5) #define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
#define ANOMALY_05000244 (__SILICON_REVISION__ < 5) #define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (__SILICON_REVISION__ < 5) #define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
/* TESTSET operation forces stall on the other core */ /* TESTSET operation forces stall on the other core */
#define ANOMALY_05000248 (__SILICON_REVISION__ < 5) #define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
...@@ -208,7 +208,7 @@ ...@@ -208,7 +208,7 @@
#define ANOMALY_05000275 (__SILICON_REVISION__ > 2) #define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
#define ANOMALY_05000276 (__SILICON_REVISION__ < 5) #define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */ /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
#define ANOMALY_05000277 (__SILICON_REVISION__ < 3) #define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ /* Disabling Peripherals with DMA Running May Cause DMA System Instability */
#define ANOMALY_05000278 (__SILICON_REVISION__ < 5) #define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
...@@ -232,7 +232,7 @@ ...@@ -232,7 +232,7 @@
#define ANOMALY_05000310 (1) #define ANOMALY_05000310 (1)
/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (1) #define ANOMALY_05000312 (1)
/* PPI Is Level-Sensitive on First Transfer */ /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
#define ANOMALY_05000313 (1) #define ANOMALY_05000313 (1)
/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ /* Killed System MMR Write Completes Erroneously On Next System MMR Access */
#define ANOMALY_05000315 (1) #define ANOMALY_05000315 (1)
...@@ -276,18 +276,27 @@ ...@@ -276,18 +276,27 @@
#define ANOMALY_05000428 (__SILICON_REVISION__ > 3) #define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1) #define ANOMALY_05000443 (1)
/* False Hardware Error when RETI points to invalid memory */
#define ANOMALY_05000461 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000119 (0)
#define ANOMALY_05000158 (0) #define ANOMALY_05000158 (0)
#define ANOMALY_05000183 (0) #define ANOMALY_05000183 (0)
#define ANOMALY_05000233 (0)
#define ANOMALY_05000273 (0) #define ANOMALY_05000273 (0)
#define ANOMALY_05000311 (0) #define ANOMALY_05000311 (0)
#define ANOMALY_05000353 (1) #define ANOMALY_05000353 (1)
#define ANOMALY_05000380 (0) #define ANOMALY_05000380 (0)
#define ANOMALY_05000386 (1) #define ANOMALY_05000386 (1)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000430 (0)
#define ANOMALY_05000432 (0) #define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0) #define ANOMALY_05000435 (0)
#define ANOMALY_05000447 (0) #define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0) #define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
#define ANOMALY_05000450 (0)
#endif #endif
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