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Commit a56866a9 authored by Ben Skeggs's avatar Ben Skeggs
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drm/nouveau/vp: namespace + nvidia gpu names (no binary change) 

The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent f84aff4e
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Showing with 41 additions and 41 deletions
drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h
View file @ a56866a9
#ifndef __NOUVEAU_VP_H__ #ifndef __NVKM_VP_H__
#define __NOUVEAU_VP_H__ #define __NVKM_VP_H__
extern struct nouveau_oclass nv84_vp_oclass; #include <core/engine.h>
extern struct nvkm_oclass g84_vp_oclass;
#endif #endif
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
View file @ a56866a9
...@@ -110,7 +110,7 @@ nv50_identify(struct nouveau_device *device) ...@@ -110,7 +110,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass; device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
...@@ -139,7 +139,7 @@ nv50_identify(struct nouveau_device *device) ...@@ -139,7 +139,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass; device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
...@@ -168,7 +168,7 @@ nv50_identify(struct nouveau_device *device) ...@@ -168,7 +168,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass; device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
...@@ -197,7 +197,7 @@ nv50_identify(struct nouveau_device *device) ...@@ -197,7 +197,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass; device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
...@@ -226,7 +226,7 @@ nv50_identify(struct nouveau_device *device) ...@@ -226,7 +226,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass; device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
...@@ -284,7 +284,7 @@ nv50_identify(struct nouveau_device *device) ...@@ -284,7 +284,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass; device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt200_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt200_disp_oclass;
......
drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild
View file @ a56866a9
nvkm-y += nvkm/engine/vp/nv84.o nvkm-y += nvkm/engine/vp/g84.o
drivers/gpu/drm/nouveau/nvkm/engine/vp/nv84.c → drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c
View file @ a56866a9
...@@ -21,9 +21,8 @@ ...@@ -21,9 +21,8 @@
* *
* Authors: Ben Skeggs, Ilia Mirkin * Authors: Ben Skeggs, Ilia Mirkin
*/ */
#include <engine/xtensa.h>
#include <engine/vp.h> #include <engine/vp.h>
#include <engine/xtensa.h>
#include <core/engctx.h> #include <core/engctx.h>
...@@ -31,9 +30,9 @@ ...@@ -31,9 +30,9 @@
* VP object classes * VP object classes
******************************************************************************/ ******************************************************************************/
static struct nouveau_oclass static struct nvkm_oclass
nv84_vp_sclass[] = { g84_vp_sclass[] = {
{ 0x7476, &nouveau_object_ofuncs }, { 0x7476, &nvkm_object_ofuncs },
{}, {},
}; };
...@@ -41,16 +40,16 @@ nv84_vp_sclass[] = { ...@@ -41,16 +40,16 @@ nv84_vp_sclass[] = {
* PVP context * PVP context
******************************************************************************/ ******************************************************************************/
static struct nouveau_oclass static struct nvkm_oclass
nv84_vp_cclass = { g84_vp_cclass = {
.handle = NV_ENGCTX(VP, 0x84), .handle = NV_ENGCTX(VP, 0x84),
.ofuncs = &(struct nouveau_ofuncs) { .ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nouveau_xtensa_engctx_ctor, .ctor = _nvkm_xtensa_engctx_ctor,
.dtor = _nouveau_engctx_dtor, .dtor = _nvkm_engctx_dtor,
.init = _nouveau_engctx_init, .init = _nvkm_engctx_init,
.fini = _nouveau_engctx_fini, .fini = _nvkm_engctx_fini,
.rd32 = _nouveau_engctx_rd32, .rd32 = _nvkm_engctx_rd32,
.wr32 = _nouveau_engctx_wr32, .wr32 = _nvkm_engctx_wr32,
}, },
}; };
...@@ -59,36 +58,36 @@ nv84_vp_cclass = { ...@@ -59,36 +58,36 @@ nv84_vp_cclass = {
******************************************************************************/ ******************************************************************************/
static int static int
nv84_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, g84_vp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size, struct nvkm_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject) struct nvkm_object **pobject)
{ {
struct nouveau_xtensa *priv; struct nvkm_xtensa *priv;
int ret; int ret;
ret = nouveau_xtensa_create(parent, engine, oclass, 0xf000, true, ret = nvkm_xtensa_create(parent, engine, oclass, 0xf000, true,
"PVP", "vp", &priv); "PVP", "vp", &priv);
*pobject = nv_object(priv); *pobject = nv_object(priv);
if (ret) if (ret)
return ret; return ret;
nv_subdev(priv)->unit = 0x01020000; nv_subdev(priv)->unit = 0x01020000;
nv_engine(priv)->cclass = &nv84_vp_cclass; nv_engine(priv)->cclass = &g84_vp_cclass;
nv_engine(priv)->sclass = nv84_vp_sclass; nv_engine(priv)->sclass = g84_vp_sclass;
priv->fifo_val = 0x111; priv->fifo_val = 0x111;
priv->unkd28 = 0x9c544; priv->unkd28 = 0x9c544;
return 0; return 0;
} }
struct nouveau_oclass struct nvkm_oclass
nv84_vp_oclass = { g84_vp_oclass = {
.handle = NV_ENGINE(VP, 0x84), .handle = NV_ENGINE(VP, 0x84),
.ofuncs = &(struct nouveau_ofuncs) { .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv84_vp_ctor, .ctor = g84_vp_ctor,
.dtor = _nouveau_xtensa_dtor, .dtor = _nvkm_xtensa_dtor,
.init = _nouveau_xtensa_init, .init = _nvkm_xtensa_init,
.fini = _nouveau_xtensa_fini, .fini = _nvkm_xtensa_fini,
.rd32 = _nouveau_xtensa_rd32, .rd32 = _nvkm_xtensa_rd32,
.wr32 = _nouveau_xtensa_wr32, .wr32 = _nvkm_xtensa_wr32,
}, },
}; };
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