[ARM] Optimise cache_is_xxx() macros.

Add CONFIG_CPU_CACHE_VIVT and CONFIG_CPU_CACHE_VIPT and use these to conditionalise cache_is_xxx(). This allows unnecessary cache handling code to be removed by the compiler.

[ARM] Optimise cache_is_xxx() macros.
Add CONFIG_CPU_CACHE_VIVT and CONFIG_CPU_CACHE_VIPT and use these to conditionalise cache_is_xxx(). This allows unnecessary cache handling code to be removed by the compiler.
a5db9f2a · Russell King · 5f54d380 · a5db9f2a · a5db9f2a · a5db9f2a
Commit a5db9f2a authored Nov 05, 2004 by Russell King
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Showing with 80 additions and 32 deletions

arch/arm/mm/Kconfig arch/arm/mm/Kconfig +21 -0

include/asm-arm/cacheflush.h include/asm-arm/cacheflush.h +59 -0

include/asm-arm/system.h include/asm-arm/system.h +0 -32

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--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -14,6 +14,7 @@ config CPU_ARM610
 	depends on ARCH_RPC
 	select CPU_32v3
 	select CPU_CACHE_V3
+	select CPU_CACHE_VIVT
 	select CPU_COPY_V3
 	select CPU_TLB_V3
 	help
@@ -29,6 +30,7 @@ config CPU_ARM710
 	default y if ARCH_CLPS7500
 	select CPU_32v3
 	select CPU_CACHE_V3
+	select CPU_CACHE_VIVT
 	select CPU_COPY_V3
 	select CPU_TLB_V3
 	help
@@ -47,6 +49,7 @@ config CPU_ARM720T
 	select CPU_32v4
 	select CPU_ABRT_LV4T
 	select CPU_CACHE_V4
+	select CPU_CACHE_VIVT
 	select CPU_COPY_V4WT
 	select CPU_TLB_V4WT
 	help
@@ -64,6 +67,7 @@ config CPU_ARM920T
 	select CPU_32v4
 	select CPU_ABRT_EV4T
 	select CPU_CACHE_V4WT
+	select CPU_CACHE_VIVT
 	select CPU_COPY_V4WB
 	select CPU_TLB_V4WBI
 	help
@@ -84,6 +88,7 @@ config CPU_ARM922T
 	select CPU_32v4
 	select CPU_ABRT_EV4T
 	select CPU_CACHE_V4WT
+	select CPU_CACHE_VIVT
 	select CPU_COPY_V4WB
 	select CPU_TLB_V4WBI
 	help
@@ -102,6 +107,7 @@ config CPU_ARM925T
 	select CPU_32v4
 	select CPU_ABRT_EV4T
 	select CPU_CACHE_V4WT
+	select CPU_CACHE_VIVT
 	select CPU_COPY_V4WB
 	select CPU_TLB_V4WBI
 	help
@@ -119,6 +125,7 @@ config CPU_ARM926T
 	default y if ARCH_VERSATILE_PB
 	select CPU_32v5
 	select CPU_ABRT_EV5TJ
+	select CPU_CACHE_VIVT
 	select CPU_COPY_V4WB
 	select CPU_TLB_V4WBI
 	help
@@ -136,6 +143,7 @@ config CPU_ARM1020
 	select CPU_32v5
 	select CPU_ABRT_EV4T
 	select CPU_CACHE_V4WT
+	select CPU_CACHE_VIVT
 	select CPU_COPY_V4WB
 	select CPU_TLB_V4WBI
 	help
@@ -152,6 +160,7 @@ config CPU_ARM1020E
 	select CPU_32v5
 	select CPU_ABRT_EV4T
 	select CPU_CACHE_V4WT
+	select CPU_CACHE_VIVT
 	select CPU_COPY_V4WB
 	select CPU_TLB_V4WBI
 	depends on n
@@ -162,6 +171,7 @@ config CPU_ARM1022
 	depends on ARCH_INTEGRATOR
 	select CPU_32v5
 	select CPU_ABRT_EV4T
+	select CPU_CACHE_VIVT
 	select CPU_COPY_V4WB # can probably do better
 	select CPU_TLB_V4WBI
 	help
@@ -178,6 +188,7 @@ config CPU_ARM1026
 	depends on ARCH_INTEGRATOR
 	select CPU_32v5
 	select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
+	select CPU_CACHE_VIVT
 	select CPU_COPY_V4WB # can probably do better
 	select CPU_TLB_V4WBI
 	help
@@ -195,6 +206,7 @@ config CPU_SA110
 	select CPU_32v4 if !ARCH_RPC
 	select CPU_ABRT_EV4
 	select CPU_CACHE_V4WB
+	select CPU_CACHE_VIVT
 	select CPU_COPY_V4WB
 	select CPU_TLB_V4WB
 	help
@@ -214,6 +226,7 @@ config CPU_SA1100
 	select CPU_32v4
 	select CPU_ABRT_EV4
 	select CPU_CACHE_V4WB
+	select CPU_CACHE_VIVT
 	select CPU_TLB_V4WB
 	select CPU_MINICACHE

@@ -224,6 +237,7 @@ config CPU_XSCALE
 	default y
 	select CPU_32v5
 	select CPU_ABRT_EV5T
+	select CPU_CACHE_VIVT
 	select CPU_TLB_V4WBI
 	select CPU_MINICACHE

@@ -234,6 +248,7 @@ config CPU_V6
 	select CPU_32v6
 	select CPU_ABRT_EV6
 	select CPU_CACHE_V6
+	select CPU_CACHE_VIPT
 	select CPU_COPY_V6
 	select CPU_TLB_V6

@@ -286,6 +301,12 @@ config CPU_CACHE_V4WB
 config CPU_CACHE_V6
 	bool

+config CPU_CACHE_VIVT
+	bool
+
+config CPU_CACHE_VIPT
+	bool
+
 # The copy-page model
 config CPU_COPY_V3
 	bool

--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -325,4 +325,63 @@ extern void flush_dcache_page(struct page *);
 */
 #define flush_icache_page(vma,page)	do { } while (0)

+#define __cacheid_present(val)		(val != read_cpuid(CPUID_ID))
+#define __cacheid_vivt(val)		((val & (15 << 25)) != (14 << 25))
+#define __cacheid_vipt(val)		((val & (15 << 25)) == (14 << 25))
+#define __cacheid_vipt_nonaliasing(val)	((val & (15 << 25 | 1 << 23)) == (14 << 25))
+#define __cacheid_vipt_aliasing(val)	((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))
+
+#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
+
+#define cache_is_vivt()			1
+#define cache_is_vipt()			0
+#define cache_is_vipt_nonaliasing()	0
+#define cache_is_vipt_aliasing()	0
+
+#elif defined(CONFIG_CPU_CACHE_VIPT)
+
+#define cache_is_vivt()			0
+#define cache_is_vipt()			1
+#define cache_is_vipt_nonaliasing()					\
+	({								\
+		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
+		__cacheid_vipt_nonaliasing(__val);			\
+	})
+
+#define cache_is_vipt_aliasing()					\
+	({								\
+		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
+		__cacheid_vipt_aliasing(__val);				\
+	})
+
+#else
+
+#define cache_is_vivt()							\
+	({								\
+		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
+		(!__cacheid_present(__val)) || __cacheid_vivt(__val);	\
+	})
+		
+#define cache_is_vipt()							\
+	({								\
+		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
+		__cacheid_present(__val) && __cacheid_vipt(__val);	\
+	})
+
+#define cache_is_vipt_nonaliasing()					\
+	({								\
+		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
+		__cacheid_present(__val) &&				\
+		 __cacheid_vipt_nonaliasing(__val);			\
+	})
+
+#define cache_is_vipt_aliasing()					\
+	({								\
+		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
+		__cacheid_present(__val) &&				\
+		 __cacheid_vipt_aliasing(__val);			\
+	})
+
+#endif
+
 #endif
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -57,38 +57,6 @@
 		__val;							\
 	})

-#define __cacheid_present(val)		(val != read_cpuid(CPUID_ID))
-#define __cacheid_vivt(val)		((val & (15 << 25)) != (14 << 25))
-#define __cacheid_vipt(val)		((val & (15 << 25)) == (14 << 25))
-#define __cacheid_vipt_nonaliasing(val)	((val & (15 << 25 | 1 << 23)) == (14 << 25))
-#define __cacheid_vipt_aliasing(val)	((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))
-
-#define cache_is_vivt()							\
-	({								\
-		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
-		(!__cacheid_present(__val)) || __cacheid_vivt(__val);	\
-	})
-		
-#define cache_is_vipt()							\
-	({								\
-		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
-		__cacheid_present(__val) && __cacheid_vipt(__val);	\
-	})
-
-#define cache_is_vipt_nonaliasing()					\
-	({								\
-		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
-		__cacheid_present(__val) &&				\
-		 __cacheid_vipt_nonaliasing(__val);			\
-	})
-
-#define cache_is_vipt_aliasing()					\
-	({								\
-		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
-		__cacheid_present(__val) &&				\
-		 __cacheid_vipt_aliasing(__val);			\
-	})
-
 /*
 * This is used to ensure the compiler did actually allocate the register we
 * asked it for some inline assembly sequences.  Apparently we can't trust