Commit a73ce538 authored by David S. Miller's avatar David S. Miller

[TG3]: More Sun onboard 5704 fixes.

- Add TG3_FLG2_SUN_5704, set it at probe time.
- Do not try to use NVRAM on Sun 5704 chips.
- Handle lack of firmware on Sun 5704 chips.
parent 0bcd7365
/*
* tg3.c: Broadcom Tigon3 ethernet driver.
*
* Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)
* Copyright (C) 2001, 2002, 2003 David S. Miller (davem@redhat.com)
* Copyright (C) 2001, 2002 Jeff Garzik (jgarzik@pobox.com)
*/
......@@ -57,8 +57,8 @@
#define DRV_MODULE_NAME "tg3"
#define PFX DRV_MODULE_NAME ": "
#define DRV_MODULE_VERSION "1.7"
#define DRV_MODULE_RELDATE "July 23, 2003"
#define DRV_MODULE_VERSION "1.8"
#define DRV_MODULE_RELDATE "August 1, 2003"
#define TG3_DEF_MAC_MODE 0
#define TG3_DEF_RX_MODE 0
......@@ -3103,18 +3103,20 @@ static void tg3_chip_reset(struct tg3 *tp)
u32 val;
u32 flags_save;
/* Force NVRAM to settle.
* This deals with a chip bug which can result in EEPROM
* corruption.
*/
if (tp->tg3_flags & TG3_FLAG_NVRAM) {
int i;
if (!(tp->tg3_flags2 & TG3_FLG2_SUN_5704)) {
/* Force NVRAM to settle.
* This deals with a chip bug which can result in EEPROM
* corruption.
*/
if (tp->tg3_flags & TG3_FLAG_NVRAM) {
int i;
tw32(NVRAM_SWARB, SWARB_REQ_SET1);
for (i = 0; i < 100000; i++) {
if (tr32(NVRAM_SWARB) & SWARB_GNT1)
break;
udelay(10);
tw32(NVRAM_SWARB, SWARB_REQ_SET1);
for (i = 0; i < 100000; i++) {
if (tr32(NVRAM_SWARB) & SWARB_GNT1)
break;
udelay(10);
}
}
}
......@@ -3207,7 +3209,8 @@ static int tg3_halt(struct tg3 *tp)
udelay(10);
}
if (i >= 100000) {
if (i >= 100000 &&
!(tp->tg3_flags2 & TG3_FLG2_SUN_5704)) {
printk(KERN_ERR PFX "tg3_halt timed out for %s, "
"firmware will not restart magic=%08x\n",
tp->dev->name, val);
......@@ -3951,7 +3954,8 @@ static int tg3_reset_hw(struct tg3 *tp)
break;
udelay(10);
}
if (i >= 100000) {
if (i >= 100000 &&
!(tp->tg3_flags2 & TG3_FLG2_SUN_5704)) {
printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
"firmware will not restart magic=%08x\n",
tp->dev->name, val);
......@@ -5569,6 +5573,9 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
{
int j;
if (tp->tg3_flags2 & TG3_FLG2_SUN_5704)
return;
tw32(GRC_EEPROM_ADDR,
(EEPROM_ADDR_FSM_RESET |
(EEPROM_DEFAULT_CLOCK_PERIOD <<
......@@ -5641,6 +5648,11 @@ static int __devinit tg3_nvram_read(struct tg3 *tp,
{
int i, saw_done_clear;
if (tp->tg3_flags2 & TG3_FLG2_SUN_5704) {
printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 5704\n");
return -EINVAL;
}
if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
return tg3_nvram_read_using_eeprom(tp, offset, val);
......@@ -5909,6 +5921,14 @@ static void __devinit tg3_read_partno(struct tg3 *tp)
unsigned char vpd_data[256];
int i;
if (tp->tg3_flags2 & TG3_FLG2_SUN_5704) {
/* Sun decided not to put the necessary bits in the
* NVRAM of their onboard tg3 parts :(
*/
strcpy(tp->board_part_number, "Sun 5704");
return;
}
for (i = 0; i < 256; i += 4) {
u32 tmp;
......@@ -5965,6 +5985,34 @@ static void __devinit tg3_read_partno(struct tg3 *tp)
strcpy(tp->board_part_number, "none");
}
#ifdef CONFIG_SPARC64
static int __devinit tg3_is_sun_5704(struct tg3 *tp)
{
struct pci_dev *pdev = tp->pdev;
struct pcidev_cookie *pcp = pdev->sysdata;
if (pcp != NULL) {
int node = pcp->prom_node;
u32 venid, devid;
int err;
err = prom_getproperty(node, "subsystem-vendor-id",
(char *) &venid, sizeof(venid));
if (err == 0 || err == -1)
return 0;
err = prom_getproperty(node, "subsystem-id",
(char *) &devid, sizeof(devid));
if (err == 0 || err == -1)
return 0;
if (venid == PCI_VENDOR_ID_SUN &&
devid == PCI_DEVICE_ID_TIGON3_5704)
return 1;
}
return 0;
}
#endif
static int __devinit tg3_get_invariants(struct tg3 *tp)
{
u32 misc_ctrl_reg;
......@@ -5973,6 +6021,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
u16 pci_cmd;
int err;
#ifdef CONFIG_SPARC64
if (tg3_is_sun_5704(tp))
tp->tg3_flags2 |= TG3_FLG2_SUN_5704;
#endif
/* If we have an AMD 762 or Intel ICH/ICH0 chipset, write
* reordering to the mailbox registers done by the host
* controller can cause major troubles. We read back from
......@@ -6337,7 +6390,8 @@ static int __devinit tg3_get_device_address(struct tg3 *tp)
dev->dev_addr[5] = (lo >> 0) & 0xff;
}
/* Next, try NVRAM. */
else if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
else if (!(tp->tg3_flags & TG3_FLG2_SUN_5704) &&
!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
!tg3_nvram_read(tp, mac_offset + 4, &lo)) {
dev->dev_addr[0] = ((hi >> 16) & 0xff);
dev->dev_addr[1] = ((hi >> 24) & 0xff);
......
......@@ -1823,6 +1823,7 @@ struct tg3 {
#define TG3_FLAG_INIT_COMPLETE 0x80000000
u32 tg3_flags2;
#define TG3_FLG2_RESTART_TIMER 0x00000001
#define TG3_FLG2_SUN_5704 0x00000002
u32 split_mode_max_reqs;
#define SPLIT_MODE_5704_MAX_REQ 3
......
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