Commit a7f6e231 authored by Deepak S's avatar Deepak S Committed by Daniel Vetter

drm/i915/vlv: Remove wait for for punit to updates freq.

When GPU is idle on VLV, Request freq to punit should be good enough to
get the voltage back to VNN. Also, make sure gfx clock force applies
before requesting the freq fot vlv.

v2: Do forcewake before setting idle frequency (ville)
    Update function comments to match the code (Deepak)

v3: Fix get/put across idle frequency Request. (Ville)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75244suggested-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarDeepak S <deepak.s@linux.intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent b6e742f6
...@@ -4097,51 +4097,32 @@ static void valleyview_set_rps(struct drm_device *dev, u8 val) ...@@ -4097,51 +4097,32 @@ static void valleyview_set_rps(struct drm_device *dev, u8 val)
trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
} }
/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
* *
* * If Gfx is Idle, then * * If Gfx is Idle, then
* 1. Mask Turbo interrupts * 1. Forcewake Media well.
* 2. Bring up Gfx clock * 2. Request idle freq.
* 3. Change the freq to Rpn and wait till P-Unit updates freq * 3. Release Forcewake of Media well.
* 4. Clear the Force GFX CLK ON bit so that Gfx can down
* 5. Unmask Turbo interrupts
*/ */
static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
{ {
struct drm_device *dev = dev_priv->dev; struct drm_device *dev = dev_priv->dev;
u32 val = dev_priv->rps.idle_freq; u32 val = dev_priv->rps.idle_freq;
/* CHV and latest VLV don't need to force the gfx clock */ /* CHV don't need to force the gfx clock */
if (IS_CHERRYVIEW(dev) || dev->pdev->revision >= 0xd) { if (IS_CHERRYVIEW(dev)) {
valleyview_set_rps(dev_priv->dev, val); valleyview_set_rps(dev_priv->dev, val);
return; return;
} }
/*
* When we are idle. Drop to min voltage state.
*/
if (dev_priv->rps.cur_freq <= val) if (dev_priv->rps.cur_freq <= val)
return; return;
/* Mask turbo interrupt so that they will not come in between */ /* Wake up the media well, as that takes a lot less
I915_WRITE(GEN6_PMINTRMSK, * power than the Render well. */
gen6_sanitize_rps_pm_mask(dev_priv, ~0)); intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
valleyview_set_rps(dev_priv->dev, val);
vlv_force_gfx_clock(dev_priv, true); intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
dev_priv->rps.cur_freq = val;
vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
& GENFREQSTATUS) == 0, 100))
DRM_ERROR("timed out waiting for Punit\n");
gen6_set_rps_thresholds(dev_priv, val);
vlv_force_gfx_clock(dev_priv, false);
I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
} }
void gen6_rps_busy(struct drm_i915_private *dev_priv) void gen6_rps_busy(struct drm_i915_private *dev_priv)
......
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