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Commit aa4d7a4d authored by Ben Skeggs's avatar Ben Skeggs
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drm/nouveau/perfmon: initial infrastructure to expose performance counters 

Internal use only at this point.  Userspace later.
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 2984506f
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Showing with 1616 additions and 2 deletions
drivers/gpu/drm/nouveau/Makefile
View file @ aa4d7a4d
......@@ -246,6 +246,15 @@ nouveau-y += core/engine/mpeg/nv40.o
nouveau-y += core/engine/mpeg/nv44.o
nouveau-y += core/engine/mpeg/nv50.o
nouveau-y += core/engine/mpeg/nv84.o
nouveau-y += core/engine/perfmon/base.o
nouveau-y += core/engine/perfmon/daemon.o
nouveau-y += core/engine/perfmon/nv40.o
nouveau-y += core/engine/perfmon/nv50.o
nouveau-y += core/engine/perfmon/nv84.o
nouveau-y += core/engine/perfmon/nva3.o
nouveau-y += core/engine/perfmon/nvc0.o
nouveau-y += core/engine/perfmon/nve0.o
nouveau-y += core/engine/perfmon/nvf0.o
nouveau-y += core/engine/ppp/nv98.o
nouveau-y += core/engine/ppp/nvc0.o
nouveau-y += core/engine/software/nv04.o
......
drivers/gpu/drm/nouveau/core/engine/device/base.c
View file @ aa4d7a4d
......@@ -77,6 +77,7 @@ static const u64 disable_map[] = {
[NVDEV_SUBDEV_THERM] = NV_DEVICE_DISABLE_CORE,
[NVDEV_SUBDEV_PWR] = NV_DEVICE_DISABLE_CORE,
[NVDEV_ENGINE_DMAOBJ] = NV_DEVICE_DISABLE_CORE,
[NVDEV_ENGINE_PERFMON] = NV_DEVICE_DISABLE_CORE,
[NVDEV_ENGINE_FIFO] = NV_DEVICE_DISABLE_FIFO,
[NVDEV_ENGINE_SW] = NV_DEVICE_DISABLE_FIFO,
[NVDEV_ENGINE_GR] = NV_DEVICE_DISABLE_GRAPH,
......@@ -123,7 +124,8 @@ nouveau_devobj_ctor(struct nouveau_object *parent,
ret = nouveau_parent_create(parent, nv_object(device), oclass, 0, NULL,
(1ULL << NVDEV_ENGINE_DMAOBJ) |
(1ULL << NVDEV_ENGINE_FIFO) |
(1ULL << NVDEV_ENGINE_DISP), &devobj);
(1ULL << NVDEV_ENGINE_DISP) |
(1ULL << NVDEV_ENGINE_PERFMON), &devobj);
*pobject = nv_object(devobj);
if (ret)
return ret;
......
drivers/gpu/drm/nouveau/core/engine/device/nv40.c
View file @ aa4d7a4d
......@@ -43,6 +43,7 @@
#include <engine/graph.h>
#include <engine/mpeg.h>
#include <engine/disp.h>
#include <engine/perfmon.h>
int
nv40_identify(struct nouveau_device *device)
......@@ -68,6 +69,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x41:
device->cname = "NV41";
......@@ -89,6 +91,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x42:
device->cname = "NV42";
......@@ -110,6 +113,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x43:
device->cname = "NV43";
......@@ -131,6 +135,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x45:
device->cname = "NV45";
......@@ -152,6 +157,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x47:
device->cname = "G70";
......@@ -173,6 +179,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x49:
device->cname = "G71";
......@@ -194,6 +201,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x4b:
device->cname = "G73";
......@@ -215,6 +223,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x44:
device->cname = "NV44";
......@@ -236,6 +245,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x46:
device->cname = "G72";
......@@ -257,6 +267,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x4a:
device->cname = "NV44A";
......@@ -278,6 +289,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x4c:
device->cname = "C61";
......@@ -299,6 +311,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x4e:
device->cname = "C51";
......@@ -320,6 +333,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x63:
device->cname = "C73";
......@@ -341,6 +355,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x67:
device->cname = "C67";
......@@ -362,6 +377,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x68:
device->cname = "C68";
......@@ -383,6 +399,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
default:
nv_fatal(device, "unknown Curie chipset\n");
......
drivers/gpu/drm/nouveau/core/engine/device/nv50.c
View file @ aa4d7a4d
......@@ -50,6 +50,7 @@
#include <engine/ppp.h>
#include <engine/copy.h>
#include <engine/disp.h>
#include <engine/perfmon.h>
int
nv50_identify(struct nouveau_device *device)
......@@ -77,6 +78,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv50_perfmon_oclass;
break;
case 0x84:
device->cname = "G84";
......@@ -103,6 +105,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv84_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
break;
case 0x86:
device->cname = "G86";
......@@ -129,6 +132,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv84_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
break;
case 0x92:
device->cname = "G92";
......@@ -155,6 +159,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv84_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
break;
case 0x94:
device->cname = "G94";
......@@ -181,6 +186,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
break;
case 0x96:
device->cname = "G96";
......@@ -207,6 +213,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
break;
case 0x98:
device->cname = "G98";
......@@ -233,6 +240,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
break;
case 0xa0:
device->cname = "G200";
......@@ -259,6 +267,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva0_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
break;
case 0xaa:
device->cname = "MCP77/MCP78";
......@@ -285,6 +294,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
break;
case 0xac:
device->cname = "MCP79/MCP7A";
......@@ -311,6 +321,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
break;
case 0xa3:
device->cname = "GT215";
......@@ -339,6 +350,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
break;
case 0xa5:
device->cname = "GT216";
......@@ -366,6 +378,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
break;
case 0xa8:
device->cname = "GT218";
......@@ -393,6 +406,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
break;
case 0xaf:
device->cname = "MCP89";
......@@ -420,6 +434,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
break;
default:
nv_fatal(device, "unknown Tesla chipset\n");
......
drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
View file @ aa4d7a4d
......@@ -50,6 +50,7 @@
#include <engine/ppp.h>
#include <engine/copy.h>
#include <engine/disp.h>
#include <engine/perfmon.h>
int
nvc0_identify(struct nouveau_device *device)
......@@ -84,6 +85,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break;
case 0xc4:
device->cname = "GF104";
......@@ -114,6 +116,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break;
case 0xc3:
device->cname = "GF106";
......@@ -143,6 +146,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break;
case 0xce:
device->cname = "GF114";
......@@ -173,6 +177,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break;
case 0xcf:
device->cname = "GF116";
......@@ -203,6 +208,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break;
case 0xc1:
device->cname = "GF108";
......@@ -232,6 +238,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break;
case 0xc8:
device->cname = "GF110";
......@@ -262,6 +269,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break;
case 0xd9:
device->cname = "GF119";
......@@ -291,6 +299,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nvd0_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break;
case 0xd7:
device->cname = "GF117";
......@@ -319,6 +328,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nvd0_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break;
default:
nv_fatal(device, "unknown Fermi chipset\n");
......
drivers/gpu/drm/nouveau/core/engine/device/nve0.c
View file @ aa4d7a4d
......@@ -50,6 +50,7 @@
#include <engine/bsp.h>
#include <engine/vp.h>
#include <engine/ppp.h>
#include <engine/perfmon.h>
int
nve0_identify(struct nouveau_device *device)
......@@ -85,6 +86,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
break;
case 0xe7:
device->cname = "GK107";
......@@ -116,6 +118,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
break;
case 0xe6:
device->cname = "GK106";
......@@ -147,6 +150,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
break;
case 0xf0:
device->cname = "GK110";
......@@ -180,6 +184,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
#endif
device->oclass[NVDEV_ENGINE_PERFMON] = &nvf0_perfmon_oclass;
break;
case 0x108:
device->cname = "GK208";
......
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
View file @ aa4d7a4d
......@@ -1138,7 +1138,7 @@ nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
if (ret)
return ret;
nv_subdev(priv)->unit = 0x18001000;
nv_subdev(priv)->unit = 0x08001000;
nv_subdev(priv)->intr = nvc0_graph_intr;
priv->base.units = nvc0_graph_units;
......
drivers/gpu/drm/nouveau/core/engine/perfmon/base.c 0 → 100644
View file @ aa4d7a4d
This diff is collapsed.
drivers/gpu/drm/nouveau/core/engine/perfmon/daemon.c 0 → 100644
View file @ aa4d7a4d
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "priv.h"
static void
pwr_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
{
u32 mask = 0x00000000;
u32 ctrl = 0x00000001;
int i;
for (i = 0; i < ARRAY_SIZE(ctr->signal) && ctr->signal[i]; i++)
mask |= 1 << (ctr->signal[i] - dom->signal);
nv_wr32(ppm, 0x10a504 + (ctr->slot * 0x10), mask);
nv_wr32(ppm, 0x10a50c + (ctr->slot * 0x10), ctrl);
nv_wr32(ppm, 0x10a50c + (ppm->last * 0x10), 0x00000003);
}
static void
pwr_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
{
ctr->ctr = ppm->pwr[ctr->slot];
ctr->clk = ppm->pwr[ppm->last];
}
static void
pwr_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom)
{
int i;
for (i = 0; i <= ppm->last; i++) {
ppm->pwr[i] = nv_rd32(ppm, 0x10a508 + (i * 0x10));
nv_wr32(ppm, 0x10a508 + (i * 0x10), 0x80000000);
}
}
static const struct nouveau_funcdom
pwr_perfctr_func = {
.init = pwr_perfctr_init,
.read = pwr_perfctr_read,
.next = pwr_perfctr_next,
};
const struct nouveau_specdom
nva3_perfmon_pwr[] = {
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x00, "pwr_gr_idle" },
{ 0x04, "pwr_bsp_idle" },
{ 0x05, "pwr_vp_idle" },
{ 0x06, "pwr_ppp_idle" },
{ 0x13, "pwr_ce0_idle" },
{}
}, &pwr_perfctr_func },
{}
};
const struct nouveau_specdom
nvc0_perfmon_pwr[] = {
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x00, "pwr_gr_idle" },
{ 0x04, "pwr_bsp_idle" },
{ 0x05, "pwr_vp_idle" },
{ 0x06, "pwr_ppp_idle" },
{ 0x13, "pwr_ce0_idle" },
{ 0x14, "pwr_ce1_idle" },
{}
}, &pwr_perfctr_func },
{}
};
const struct nouveau_specdom
nve0_perfmon_pwr[] = {
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x00, "pwr_gr_idle" },
{ 0x04, "pwr_bsp_idle" },
{ 0x05, "pwr_vp_idle" },
{ 0x06, "pwr_ppp_idle" },
{ 0x13, "pwr_ce0_idle" },
{ 0x14, "pwr_ce1_idle" },
{ 0x15, "pwr_ce2_idle" },
{}
}, &pwr_perfctr_func },
{}
};
drivers/gpu/drm/nouveau/core/engine/perfmon/nv40.c 0 → 100644
View file @ aa4d7a4d
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv40.h"
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
/*******************************************************************************
* PPM context
******************************************************************************/
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
static void
nv40_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
{
struct nv40_perfmon_priv *priv = (void *)ppm;
struct nv40_perfmon_cntr *cntr = (void *)ctr;
u32 log = ctr->logic_op;
u32 src = 0x00000000;
int i;
for (i = 0; i < 4 && ctr->signal[i]; i++)
src |= (ctr->signal[i] - dom->signal) << (i * 8);
nv_wr32(priv, 0x00a7c0 + dom->addr, 0x00000001);
nv_wr32(priv, 0x00a400 + dom->addr + (cntr->base.slot * 0x40), src);
nv_wr32(priv, 0x00a420 + dom->addr + (cntr->base.slot * 0x40), log);
}
static void
nv40_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
{
struct nv40_perfmon_priv *priv = (void *)ppm;
struct nv40_perfmon_cntr *cntr = (void *)ctr;
switch (cntr->base.slot) {
case 0: cntr->base.ctr = nv_rd32(priv, 0x00a700 + dom->addr); break;
case 1: cntr->base.ctr = nv_rd32(priv, 0x00a6c0 + dom->addr); break;
case 2: cntr->base.ctr = nv_rd32(priv, 0x00a680 + dom->addr); break;
case 3: cntr->base.ctr = nv_rd32(priv, 0x00a740 + dom->addr); break;
}
cntr->base.clk = nv_rd32(priv, 0x00a600 + dom->addr);
}
static void
nv40_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom)
{
struct nv40_perfmon_priv *priv = (void *)ppm;
if (priv->sequence != ppm->sequence) {
nv_wr32(priv, 0x400084, 0x00000020);
priv->sequence = ppm->sequence;
}
}
const struct nouveau_funcdom
nv40_perfctr_func = {
.init = nv40_perfctr_init,
.read = nv40_perfctr_read,
.next = nv40_perfctr_next,
};
static const struct nouveau_specdom
nv40_perfmon[] = {
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{}
};
int
nv40_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nv40_perfmon_oclass *mclass = (void *)oclass;
struct nv40_perfmon_priv *priv;
int ret;
ret = nouveau_perfmon_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
ret = nouveau_perfdom_new(&priv->base, "pm", 0, 0, 0, 4, mclass->doms);
if (ret)
return ret;
nv_engine(priv)->cclass = &nouveau_perfmon_cclass;
nv_engine(priv)->sclass = nouveau_perfmon_sclass;
return 0;
}
struct nouveau_oclass *
nv40_perfmon_oclass = &(struct nv40_perfmon_oclass) {
.base.handle = NV_ENGINE(PERFMON, 0x40),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv40_perfmon_ctor,
.dtor = _nouveau_perfmon_dtor,
.init = _nouveau_perfmon_init,
.fini = _nouveau_perfmon_fini,
},
.doms = nv40_perfmon,
}.base;
drivers/gpu/drm/nouveau/core/engine/perfmon/nv40.h 0 → 100644
View file @ aa4d7a4d
#ifndef __NVKM_PM_NV40_H__
#define __NVKM_PM_NV40_H__
#include "priv.h"
struct nv40_perfmon_oclass {
struct nouveau_oclass base;
const struct nouveau_specdom *doms;
};
struct nv40_perfmon_priv {
struct nouveau_perfmon base;
u32 sequence;
};
int nv40_perfmon_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *data, u32 size,
struct nouveau_object **pobject);
struct nv40_perfmon_cntr {
struct nouveau_perfctr base;
};
extern const struct nouveau_funcdom nv40_perfctr_func;
#endif
drivers/gpu/drm/nouveau/core/engine/perfmon/nv50.c 0 → 100644
View file @ aa4d7a4d
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv40.h"
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
/*******************************************************************************
* PPM context
******************************************************************************/
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
static const struct nouveau_specdom
nv50_perfmon[] = {
{ 0x040, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x100, (const struct nouveau_specsig[]) {
{ 0xc8, "gr_idle" },
{}
}, &nv40_perfctr_func },
{ 0x100, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x020, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x040, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{}
};
struct nouveau_oclass *
nv50_perfmon_oclass = &(struct nv40_perfmon_oclass) {
.base.handle = NV_ENGINE(PERFMON, 0x50),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv40_perfmon_ctor,
.dtor = _nouveau_perfmon_dtor,
.init = _nouveau_perfmon_init,
.fini = _nouveau_perfmon_fini,
},
.doms = nv50_perfmon,
}.base;
drivers/gpu/drm/nouveau/core/engine/perfmon/nv84.c 0 → 100644
View file @ aa4d7a4d
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv40.h"
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
/*******************************************************************************
* PPM context
******************************************************************************/
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
static const struct nouveau_specdom
nv84_perfmon[] = {
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{}
};
struct nouveau_oclass *
nv84_perfmon_oclass = &(struct nv40_perfmon_oclass) {
.base.handle = NV_ENGINE(PERFMON, 0x84),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv40_perfmon_ctor,
.dtor = _nouveau_perfmon_dtor,
.init = _nouveau_perfmon_init,
.fini = _nouveau_perfmon_fini,
},
.doms = nv84_perfmon,
}.base;
drivers/gpu/drm/nouveau/core/engine/perfmon/nva3.c 0 → 100644
View file @ aa4d7a4d
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv40.h"
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
/*******************************************************************************
* PPM context
******************************************************************************/
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
static const struct nouveau_specdom
nva3_perfmon[] = {
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{}
};
static int
nva3_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **object)
{
int ret = nv40_perfmon_ctor(parent, engine, oclass, data, size, object);
if (ret == 0) {
struct nv40_perfmon_priv *priv = (void *)*object;
ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
nva3_perfmon_pwr);
if (ret)
return ret;
priv->base.last = 3;
}
return ret;
}
struct nouveau_oclass *
nva3_perfmon_oclass = &(struct nv40_perfmon_oclass) {
.base.handle = NV_ENGINE(PERFMON, 0xa3),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nva3_perfmon_ctor,
.dtor = _nouveau_perfmon_dtor,
.init = _nouveau_perfmon_init,
.fini = _nouveau_perfmon_fini,
},
.doms = nva3_perfmon,
}.base;
drivers/gpu/drm/nouveau/core/engine/perfmon/nvc0.c 0 → 100644
View file @ aa4d7a4d
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nvc0.h"
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
/*******************************************************************************
* PPM context
******************************************************************************/
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
static const struct nouveau_specdom
nvc0_perfmon_hub[] = {
{}
};
static const struct nouveau_specdom
nvc0_perfmon_gpc[] = {
{}
};
static const struct nouveau_specdom
nvc0_perfmon_part[] = {
{}
};
static void
nvc0_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
{
struct nvc0_perfmon_priv *priv = (void *)ppm;
struct nvc0_perfmon_cntr *cntr = (void *)ctr;
u32 log = ctr->logic_op;
u32 src = 0x00000000;
int i;
for (i = 0; i < 4 && ctr->signal[i]; i++)
src |= (ctr->signal[i] - dom->signal) << (i * 8);
nv_wr32(priv, dom->addr + 0x09c, 0x00040002);
nv_wr32(priv, dom->addr + 0x100, 0x00000000);
nv_wr32(priv, dom->addr + 0x040 + (cntr->base.slot * 0x08), src);
nv_wr32(priv, dom->addr + 0x044 + (cntr->base.slot * 0x08), log);
}
static void
nvc0_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
{
struct nvc0_perfmon_priv *priv = (void *)ppm;
struct nvc0_perfmon_cntr *cntr = (void *)ctr;
switch (cntr->base.slot) {
case 0: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x08c); break;
case 1: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x088); break;
case 2: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x080); break;
case 3: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x090); break;
}
cntr->base.clk = nv_rd32(priv, dom->addr + 0x070);
}
static void
nvc0_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom)
{
struct nvc0_perfmon_priv *priv = (void *)ppm;
nv_wr32(priv, dom->addr + 0x06c, dom->signal_nr - 0x40 + 0x27);
nv_wr32(priv, dom->addr + 0x0ec, 0x00000011);
}
const struct nouveau_funcdom
nvc0_perfctr_func = {
.init = nvc0_perfctr_init,
.read = nvc0_perfctr_read,
.next = nvc0_perfctr_next,
};
int
nvc0_perfmon_fini(struct nouveau_object *object, bool suspend)
{
struct nvc0_perfmon_priv *priv = (void *)object;
nv_mask(priv, 0x000200, 0x10000000, 0x00000000);
nv_mask(priv, 0x000200, 0x10000000, 0x10000000);
return nouveau_perfmon_fini(&priv->base, suspend);
}
static int
nvc0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nvc0_perfmon_priv *priv;
u32 mask;
int ret;
ret = nouveau_perfmon_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
nvc0_perfmon_pwr);
if (ret)
return ret;
/* HUB */
ret = nouveau_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200,
nvc0_perfmon_hub);
if (ret)
return ret;
/* GPC */
mask = (1 << nv_rd32(priv, 0x022430)) - 1;
mask &= ~nv_rd32(priv, 0x022504);
mask &= ~nv_rd32(priv, 0x022584);
ret = nouveau_perfdom_new(&priv->base, "gpc", mask, 0x180000,
0x1000, 0x200, nvc0_perfmon_gpc);
if (ret)
return ret;
/* PART */
mask = (1 << nv_rd32(priv, 0x022438)) - 1;
mask &= ~nv_rd32(priv, 0x022548);
mask &= ~nv_rd32(priv, 0x0225c8);
ret = nouveau_perfdom_new(&priv->base, "part", mask, 0x1a0000,
0x1000, 0x200, nvc0_perfmon_part);
if (ret)
return ret;
nv_engine(priv)->cclass = &nouveau_perfmon_cclass;
nv_engine(priv)->sclass = nouveau_perfmon_sclass;
priv->base.last = 7;
return 0;
}
struct nouveau_oclass
nvc0_perfmon_oclass = {
.handle = NV_ENGINE(PERFMON, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_perfmon_ctor,
.dtor = _nouveau_perfmon_dtor,
.init = _nouveau_perfmon_init,
.fini = nvc0_perfmon_fini,
},
};
drivers/gpu/drm/nouveau/core/engine/perfmon/nvc0.h 0 → 100644
View file @ aa4d7a4d
#ifndef __NVKM_PM_NVC0_H__
#define __NVKM_PM_NVC0_H__
#include "priv.h"
struct nvc0_perfmon_priv {
struct nouveau_perfmon base;
};
struct nvc0_perfmon_cntr {
struct nouveau_perfctr base;
};
extern const struct nouveau_funcdom nvc0_perfctr_func;
int nvc0_perfmon_fini(struct nouveau_object *, bool);
#endif
drivers/gpu/drm/nouveau/core/engine/perfmon/nve0.c 0 → 100644
View file @ aa4d7a4d
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nvc0.h"
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
/*******************************************************************************
* PPM context
******************************************************************************/
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
static const struct nouveau_specdom
nve0_perfmon_hub[] = {
{ 0x60, (const struct nouveau_specsig[]) {
{ 0x47, "hub00_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x40, (const struct nouveau_specsig[]) {
{ 0x27, "hub01_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x60, (const struct nouveau_specsig[]) {
{ 0x47, "hub02_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x60, (const struct nouveau_specsig[]) {
{ 0x47, "hub03_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x40, (const struct nouveau_specsig[]) {
{ 0x03, "host_mmio_rd" },
{ 0x27, "hub04_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x60, (const struct nouveau_specsig[]) {
{ 0x47, "hub05_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0xc0, (const struct nouveau_specsig[]) {
{ 0x74, "host_fb_rd3x" },
{ 0x75, "host_fb_rd3x_2" },
{ 0xa7, "hub06_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x60, (const struct nouveau_specsig[]) {
{ 0x47, "hub07_user_0" },
{}
}, &nvc0_perfctr_func },
{}
};
static const struct nouveau_specdom
nve0_perfmon_gpc[] = {
{ 0xe0, (const struct nouveau_specsig[]) {
{ 0xc7, "gpc00_user_0" },
{}
}, &nvc0_perfctr_func },
{}
};
static const struct nouveau_specdom
nve0_perfmon_part[] = {
{ 0x60, (const struct nouveau_specsig[]) {
{ 0x47, "part00_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x60, (const struct nouveau_specsig[]) {
{ 0x47, "part01_user_0" },
{}
}, &nvc0_perfctr_func },
{}
};
static int
nve0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nvc0_perfmon_priv *priv;
u32 mask;
int ret;
ret = nouveau_perfmon_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
/* PDAEMON */
ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
nve0_perfmon_pwr);
if (ret)
return ret;
/* HUB */
ret = nouveau_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200,
nve0_perfmon_hub);
if (ret)
return ret;
/* GPC */
mask = (1 << nv_rd32(priv, 0x022430)) - 1;
mask &= ~nv_rd32(priv, 0x022504);
mask &= ~nv_rd32(priv, 0x022584);
ret = nouveau_perfdom_new(&priv->base, "gpc", mask, 0x180000,
0x1000, 0x200, nve0_perfmon_gpc);
if (ret)
return ret;
/* PART */
mask = (1 << nv_rd32(priv, 0x022438)) - 1;
mask &= ~nv_rd32(priv, 0x022548);
mask &= ~nv_rd32(priv, 0x0225c8);
ret = nouveau_perfdom_new(&priv->base, "part", mask, 0x1a0000,
0x1000, 0x200, nve0_perfmon_part);
if (ret)
return ret;
nv_engine(priv)->cclass = &nouveau_perfmon_cclass;
nv_engine(priv)->sclass = nouveau_perfmon_sclass;
priv->base.last = 7;
return 0;
}
struct nouveau_oclass
nve0_perfmon_oclass = {
.handle = NV_ENGINE(PERFMON, 0xe0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nve0_perfmon_ctor,
.dtor = _nouveau_perfmon_dtor,
.init = _nouveau_perfmon_init,
.fini = nvc0_perfmon_fini,
},
};
drivers/gpu/drm/nouveau/core/engine/perfmon/nvf0.c 0 → 100644
View file @ aa4d7a4d
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nvc0.h"
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
/*******************************************************************************
* PPM context
******************************************************************************/
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
static int
nvf0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nvc0_perfmon_priv *priv;
int ret;
ret = nouveau_perfmon_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
nve0_perfmon_pwr);
if (ret)
return ret;
nv_engine(priv)->cclass = &nouveau_perfmon_cclass;
nv_engine(priv)->sclass = nouveau_perfmon_sclass;
return 0;
}
struct nouveau_oclass
nvf0_perfmon_oclass = {
.handle = NV_ENGINE(PERFMON, 0xf0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvf0_perfmon_ctor,
.dtor = _nouveau_perfmon_dtor,
.init = _nouveau_perfmon_init,
.fini = nvc0_perfmon_fini,
},
};
drivers/gpu/drm/nouveau/core/engine/perfmon/priv.h 0 → 100644
View file @ aa4d7a4d
#ifndef __NVKM_PERFMON_PRIV_H__
#define __NVKM_PERFMON_PRIV_H__
#include <engine/perfmon.h>
struct nouveau_perfctr {
struct nouveau_object base;
struct list_head head;
struct nouveau_perfsig *signal[4];
int slot;
u32 logic_op;
u32 clk;
u32 ctr;
};
extern struct nouveau_oclass nouveau_perfmon_sclass[];
struct nouveau_perfctx {
struct nouveau_engctx base;
};
extern struct nouveau_oclass nouveau_perfmon_cclass;
struct nouveau_specsig {
u8 signal;
const char *name;
};
struct nouveau_perfsig {
const char *name;
};
struct nouveau_perfdom;
struct nouveau_perfctr *
nouveau_perfsig_wrap(struct nouveau_perfmon *, const char *,
struct nouveau_perfdom **);
struct nouveau_specdom {
u16 signal_nr;
const struct nouveau_specsig *signal;
const struct nouveau_funcdom *func;
};
extern const struct nouveau_specdom nva3_perfmon_pwr[];
extern const struct nouveau_specdom nvc0_perfmon_pwr[];
extern const struct nouveau_specdom nve0_perfmon_pwr[];
struct nouveau_perfdom {
struct list_head head;
struct list_head list;
const struct nouveau_funcdom *func;
char name[32];
u32 addr;
u8 quad;
u32 signal_nr;
struct nouveau_perfsig signal[];
};
struct nouveau_funcdom {
void (*init)(struct nouveau_perfmon *, struct nouveau_perfdom *,
struct nouveau_perfctr *);
void (*read)(struct nouveau_perfmon *, struct nouveau_perfdom *,
struct nouveau_perfctr *);
void (*next)(struct nouveau_perfmon *, struct nouveau_perfdom *);
};
int nouveau_perfdom_new(struct nouveau_perfmon *, const char *, u32,
u32, u32, u32, const struct nouveau_specdom *);
#define nouveau_perfmon_create(p,e,o,d) \
nouveau_perfmon_create_((p), (e), (o), sizeof(**d), (void **)d)
#define nouveau_perfmon_dtor(p) ({ \
struct nouveau_perfmon *c = (p); \
_nouveau_perfmon_dtor(nv_object(c)); \
})
#define nouveau_perfmon_init(p) ({ \
struct nouveau_perfmon *c = (p); \
_nouveau_perfmon_init(nv_object(c)); \
})
#define nouveau_perfmon_fini(p,s) ({ \
struct nouveau_perfmon *c = (p); \
_nouveau_perfmon_fini(nv_object(c), (s)); \
})
int nouveau_perfmon_create_(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, int, void **);
void _nouveau_perfmon_dtor(struct nouveau_object *);
int _nouveau_perfmon_init(struct nouveau_object *);
int _nouveau_perfmon_fini(struct nouveau_object *, bool);
#endif
drivers/gpu/drm/nouveau/core/include/core/class.h
View file @ aa4d7a4d
......@@ -98,6 +98,37 @@ struct nv_dma_class {
u32 conf0;
};
/* Perfmon counter class
*
* XXXX: NV_PERFCTR
*/
#define NV_PERFCTR_CLASS 0x0000ffff
#define NV_PERFCTR_QUERY 0x00000000
#define NV_PERFCTR_SAMPLE 0x00000001
#define NV_PERFCTR_READ 0x00000002
struct nv_perfctr_class {
u16 logic_op;
struct {
char __user *name; /*XXX: use cfu when exposed to userspace */
u32 size;
} signal[4];
};
struct nv_perfctr_query {
u32 iter;
u32 size;
char __user *name; /*XXX: use ctu when exposed to userspace */
};
struct nv_perfctr_sample {
};
struct nv_perfctr_read {
u32 ctr;
u32 clk;
};
/* DMA FIFO channel classes
*
* 006b: NV03_CHANNEL_DMA
......
drivers/gpu/drm/nouveau/core/include/core/device.h
View file @ aa4d7a4d
......@@ -54,6 +54,7 @@ enum nv_subdev_type {
NVDEV_ENGINE_VIC,
NVDEV_ENGINE_VENC,
NVDEV_ENGINE_DISP,
NVDEV_ENGINE_PERFMON,
NVDEV_SUBDEV_NR,
};
......
drivers/gpu/drm/nouveau/core/include/engine/perfmon.h 0 → 100644
View file @ aa4d7a4d
#ifndef __NVKM_PERFMON_H__
#define __NVKM_PERFMON_H__
#include <core/device.h>
#include <core/engine.h>
#include <core/engctx.h>
#include <core/class.h>
struct nouveau_perfdom;
struct nouveau_perfctr;
struct nouveau_perfmon {
struct nouveau_engine base;
struct nouveau_perfctx *context;
void *profile_data;
struct list_head domains;
u32 sequence;
/*XXX: temp for daemon backend */
u32 pwr[8];
u32 last;
};
static inline struct nouveau_perfmon *
nouveau_perfmon(void *obj)
{
return (void *)nv_device(obj)->subdev[NVDEV_ENGINE_PERFMON];
}
extern struct nouveau_oclass *nv40_perfmon_oclass;
extern struct nouveau_oclass *nv50_perfmon_oclass;
extern struct nouveau_oclass *nv84_perfmon_oclass;
extern struct nouveau_oclass *nva3_perfmon_oclass;
extern struct nouveau_oclass nvc0_perfmon_oclass;
extern struct nouveau_oclass nve0_perfmon_oclass;
extern struct nouveau_oclass nvf0_perfmon_oclass;
#endif
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