Commit abc189ea authored by Adam Thomson's avatar Adam Thomson Committed by Mark Brown

ASoC: da7213: Allow PLL disable/bypass when using 32KHz sysclk

Current checking for PLL 32KHz mode fails in driver code when
bypassing the PLL. This is due to an incorrect check of PLL
source type when 32KHz clock is provided. Removal of this check
resolves the issue.
Signed-off-by: default avatarAdam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 1e62c52d
......@@ -1342,7 +1342,7 @@ static int da7213_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
pll_ctrl = 0;
/* Workout input divider based on MCLK rate */
if ((da7213->mclk_rate == 32768) && (source == DA7213_SYSCLK_PLL)) {
if (da7213->mclk_rate == 32768) {
/* 32KHz PLL Mode */
indiv_bits = DA7213_PLL_INDIV_9_TO_18_MHZ;
indiv = DA7213_PLL_INDIV_9_TO_18_MHZ_VAL;
......
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