Commit aed10881 authored by Andrew Vasquez's avatar Andrew Vasquez Committed by James Bottomley

[SCSI] qla2xxx: Query supported RISC registers bits in determining a paused-state.

ISP24xx and above must query the host-status register, not HCCR.
Signed-off-by: default avatarAndrew Vasquez <andrew.vasquez@qlogic.com>
Signed-off-by: default avatarJames Bottomley <James.Bottomley@HansenPartnership.com>
parent e8233ca4
...@@ -149,11 +149,9 @@ qla24xx_pause_risc(struct device_reg_24xx __iomem *reg) ...@@ -149,11 +149,9 @@ qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
int rval = QLA_SUCCESS; int rval = QLA_SUCCESS;
uint32_t cnt; uint32_t cnt;
if (RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE)
return rval;
WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE); WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
for (cnt = 30000; (RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0 && for (cnt = 30000;
((RD_REG_DWORD(&reg->host_status) & HSRX_RISC_PAUSED) == 0) &&
rval == QLA_SUCCESS; cnt--) { rval == QLA_SUCCESS; cnt--) {
if (cnt) if (cnt)
udelay(100); udelay(100);
......
...@@ -878,7 +878,6 @@ struct device_reg_24xx { ...@@ -878,7 +878,6 @@ struct device_reg_24xx {
/* HCCR statuses. */ /* HCCR statuses. */
#define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */ #define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */
#define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */ #define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */
#define HCCRX_RISC_PAUSE BIT_4 /* RISC Pause mode bit. */
/* HCCR commands. */ /* HCCR commands. */
/* NOOP. */ /* NOOP. */
#define HCCRX_NOOP 0x00000000 #define HCCRX_NOOP 0x00000000
......
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