Commit b0f8a6d5 authored by Gavin Wan's avatar Gavin Wan Committed by Alex Deucher

drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.

For SRIOV, since the CP_INT_CNTL_RING0 is programed on host side.
The Guest should not program CP_INT_CNTL_RING0 again.
Signed-off-by: default avatarGavin Wan <Gavin.Wan@amd.com>
Reviewed-by: default avatarMonk Liu <Monk.Liu@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 49d2a388
...@@ -4558,7 +4558,12 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev) ...@@ -4558,7 +4558,12 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
bool enable) bool enable)
{ {
u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); u32 tmp;
if (amdgpu_sriov_vf(adev))
return;
tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
enable ? 1 : 0); enable ? 1 : 0);
......
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