Commit b1a504a6 authored by Cédric Le Goater's avatar Cédric Le Goater Committed by Michael Ellerman

powerpc/xive: Use XIVE_BAD_IRQ instead of zero to catch non configured IPIs

When a CPU is brought up, an IPI number is allocated and recorded
under the XIVE CPU structure. Invalid IPI numbers are tracked with
interrupt number 0x0.

On the PowerNV platform, the interrupt number space starts at 0x10 and
this works fine. However, on the sPAPR platform, it is possible to
allocate the interrupt number 0x0 and this raises an issue when CPU 0
is unplugged. The XIVE spapr driver tracks allocated interrupt numbers
in a bitmask and it is not correctly updated when interrupt number 0x0
is freed. It stays allocated and it is then impossible to reallocate.

Fix by using the XIVE_BAD_IRQ value instead of zero on both platforms.
Reported-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
Fixes: eac1e731 ("powerpc/xive: guest exploitation of the XIVE interrupt controller")
Cc: stable@vger.kernel.org # v4.14+
Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
Reviewed-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
Tested-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200306150143.5551-2-clg@kaod.org
parent a7032637
...@@ -68,13 +68,6 @@ static u32 xive_ipi_irq; ...@@ -68,13 +68,6 @@ static u32 xive_ipi_irq;
/* Xive state for each CPU */ /* Xive state for each CPU */
static DEFINE_PER_CPU(struct xive_cpu *, xive_cpu); static DEFINE_PER_CPU(struct xive_cpu *, xive_cpu);
/*
* A "disabled" interrupt should never fire, to catch problems
* we set its logical number to this
*/
#define XIVE_BAD_IRQ 0x7fffffff
#define XIVE_MAX_IRQ (XIVE_BAD_IRQ - 1)
/* An invalid CPU target */ /* An invalid CPU target */
#define XIVE_INVALID_TARGET (-1) #define XIVE_INVALID_TARGET (-1)
...@@ -1150,7 +1143,7 @@ static int xive_setup_cpu_ipi(unsigned int cpu) ...@@ -1150,7 +1143,7 @@ static int xive_setup_cpu_ipi(unsigned int cpu)
xc = per_cpu(xive_cpu, cpu); xc = per_cpu(xive_cpu, cpu);
/* Check if we are already setup */ /* Check if we are already setup */
if (xc->hw_ipi != 0) if (xc->hw_ipi != XIVE_BAD_IRQ)
return 0; return 0;
/* Grab an IPI from the backend, this will populate xc->hw_ipi */ /* Grab an IPI from the backend, this will populate xc->hw_ipi */
...@@ -1187,7 +1180,7 @@ static void xive_cleanup_cpu_ipi(unsigned int cpu, struct xive_cpu *xc) ...@@ -1187,7 +1180,7 @@ static void xive_cleanup_cpu_ipi(unsigned int cpu, struct xive_cpu *xc)
/* Disable the IPI and free the IRQ data */ /* Disable the IPI and free the IRQ data */
/* Already cleaned up ? */ /* Already cleaned up ? */
if (xc->hw_ipi == 0) if (xc->hw_ipi == XIVE_BAD_IRQ)
return; return;
/* Mask the IPI */ /* Mask the IPI */
...@@ -1343,6 +1336,7 @@ static int xive_prepare_cpu(unsigned int cpu) ...@@ -1343,6 +1336,7 @@ static int xive_prepare_cpu(unsigned int cpu)
if (np) if (np)
xc->chip_id = of_get_ibm_chip_id(np); xc->chip_id = of_get_ibm_chip_id(np);
of_node_put(np); of_node_put(np);
xc->hw_ipi = XIVE_BAD_IRQ;
per_cpu(xive_cpu, cpu) = xc; per_cpu(xive_cpu, cpu) = xc;
} }
......
...@@ -312,7 +312,7 @@ static void xive_native_put_ipi(unsigned int cpu, struct xive_cpu *xc) ...@@ -312,7 +312,7 @@ static void xive_native_put_ipi(unsigned int cpu, struct xive_cpu *xc)
s64 rc; s64 rc;
/* Free the IPI */ /* Free the IPI */
if (!xc->hw_ipi) if (xc->hw_ipi == XIVE_BAD_IRQ)
return; return;
for (;;) { for (;;) {
rc = opal_xive_free_irq(xc->hw_ipi); rc = opal_xive_free_irq(xc->hw_ipi);
...@@ -320,7 +320,7 @@ static void xive_native_put_ipi(unsigned int cpu, struct xive_cpu *xc) ...@@ -320,7 +320,7 @@ static void xive_native_put_ipi(unsigned int cpu, struct xive_cpu *xc)
msleep(OPAL_BUSY_DELAY_MS); msleep(OPAL_BUSY_DELAY_MS);
continue; continue;
} }
xc->hw_ipi = 0; xc->hw_ipi = XIVE_BAD_IRQ;
break; break;
} }
} }
......
...@@ -560,11 +560,11 @@ static int xive_spapr_get_ipi(unsigned int cpu, struct xive_cpu *xc) ...@@ -560,11 +560,11 @@ static int xive_spapr_get_ipi(unsigned int cpu, struct xive_cpu *xc)
static void xive_spapr_put_ipi(unsigned int cpu, struct xive_cpu *xc) static void xive_spapr_put_ipi(unsigned int cpu, struct xive_cpu *xc)
{ {
if (!xc->hw_ipi) if (xc->hw_ipi == XIVE_BAD_IRQ)
return; return;
xive_irq_bitmap_free(xc->hw_ipi); xive_irq_bitmap_free(xc->hw_ipi);
xc->hw_ipi = 0; xc->hw_ipi = XIVE_BAD_IRQ;
} }
#endif /* CONFIG_SMP */ #endif /* CONFIG_SMP */
......
...@@ -5,6 +5,13 @@ ...@@ -5,6 +5,13 @@
#ifndef __XIVE_INTERNAL_H #ifndef __XIVE_INTERNAL_H
#define __XIVE_INTERNAL_H #define __XIVE_INTERNAL_H
/*
* A "disabled" interrupt should never fire, to catch problems
* we set its logical number to this
*/
#define XIVE_BAD_IRQ 0x7fffffff
#define XIVE_MAX_IRQ (XIVE_BAD_IRQ - 1)
/* Each CPU carry one of these with various per-CPU state */ /* Each CPU carry one of these with various per-CPU state */
struct xive_cpu { struct xive_cpu {
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
......
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