Commit b1d37aa0 authored by Maarten Maathuis's avatar Maarten Maathuis Committed by Ben Skeggs

drm/nv50: make the pgraph irq handler loop like the pre-nv50 version

Unset the bit that indicates that a ctxprog can continue at the end.
Signed-off-by: default avatarMaarten Maathuis <madman2003@gmail.com>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent a87ff62a
...@@ -580,86 +580,99 @@ nouveau_pgraph_irq_handler(struct drm_device *dev) ...@@ -580,86 +580,99 @@ nouveau_pgraph_irq_handler(struct drm_device *dev)
static void static void
nv50_pgraph_irq_handler(struct drm_device *dev) nv50_pgraph_irq_handler(struct drm_device *dev)
{ {
uint32_t status, nsource; uint32_t status;
status = nv_rd32(dev, NV03_PGRAPH_INTR); while ((status = nv_rd32(dev, NV03_PGRAPH_INTR))) {
nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE); uint32_t nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
if (status & 0x00000001) { if (status & 0x00000001) {
nouveau_pgraph_intr_notify(dev, nsource); nouveau_pgraph_intr_notify(dev, nsource);
status &= ~0x00000001; status &= ~0x00000001;
nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000001); nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000001);
} }
if (status & 0x00000010) { if (status & 0x00000010) {
nouveau_pgraph_intr_error(dev, nsource | nouveau_pgraph_intr_error(dev, nsource |
NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD); NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD);
status &= ~0x00000010; status &= ~0x00000010;
nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000010); nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000010);
} }
if (status & 0x00001000) { if (status & 0x00001000) {
nv_wr32(dev, 0x400500, 0x00000000); nv_wr32(dev, 0x400500, 0x00000000);
nv_wr32(dev, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH); nv_wr32(dev, NV03_PGRAPH_INTR,
nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev, NV_PGRAPH_INTR_CONTEXT_SWITCH);
NV40_PGRAPH_INTR_EN) & ~NV_PGRAPH_INTR_CONTEXT_SWITCH); nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev,
nv_wr32(dev, 0x400500, 0x00010001); NV40_PGRAPH_INTR_EN) &
~NV_PGRAPH_INTR_CONTEXT_SWITCH);
nv_wr32(dev, 0x400500, 0x00010001);
nv50_graph_context_switch(dev); nv50_graph_context_switch(dev);
status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
} }
if (status & 0x00100000) { if (status & 0x00100000) {
nouveau_pgraph_intr_error(dev, nsource | nouveau_pgraph_intr_error(dev, nsource |
NV03_PGRAPH_NSOURCE_DATA_ERROR); NV03_PGRAPH_NSOURCE_DATA_ERROR);
status &= ~0x00100000; status &= ~0x00100000;
nv_wr32(dev, NV03_PGRAPH_INTR, 0x00100000); nv_wr32(dev, NV03_PGRAPH_INTR, 0x00100000);
} }
if (status & 0x00200000) { if (status & 0x00200000) {
int r; int r;
nouveau_pgraph_intr_error(dev, nsource | nouveau_pgraph_intr_error(dev, nsource |
NV03_PGRAPH_NSOURCE_PROTECTION_ERROR); NV03_PGRAPH_NSOURCE_PROTECTION_ERROR);
NV_ERROR(dev, "magic set 1:\n"); NV_ERROR(dev, "magic set 1:\n");
for (r = 0x408900; r <= 0x408910; r += 4) for (r = 0x408900; r <= 0x408910; r += 4)
NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r, nv_rd32(dev, r)); NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
nv_wr32(dev, 0x408900, nv_rd32(dev, 0x408904) | 0xc0000000); nv_rd32(dev, r));
for (r = 0x408e08; r <= 0x408e24; r += 4) nv_wr32(dev, 0x408900,
NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r, nv_rd32(dev, r)); nv_rd32(dev, 0x408904) | 0xc0000000);
nv_wr32(dev, 0x408e08, nv_rd32(dev, 0x408e08) | 0xc0000000); for (r = 0x408e08; r <= 0x408e24; r += 4)
NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
NV_ERROR(dev, "magic set 2:\n"); nv_rd32(dev, r));
for (r = 0x409900; r <= 0x409910; r += 4) nv_wr32(dev, 0x408e08,
NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r, nv_rd32(dev, r)); nv_rd32(dev, 0x408e08) | 0xc0000000);
nv_wr32(dev, 0x409900, nv_rd32(dev, 0x409904) | 0xc0000000);
for (r = 0x409e08; r <= 0x409e24; r += 4) NV_ERROR(dev, "magic set 2:\n");
NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r, nv_rd32(dev, r)); for (r = 0x409900; r <= 0x409910; r += 4)
nv_wr32(dev, 0x409e08, nv_rd32(dev, 0x409e08) | 0xc0000000); NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
nv_rd32(dev, r));
status &= ~0x00200000; nv_wr32(dev, 0x409900,
nv_wr32(dev, NV03_PGRAPH_NSOURCE, nsource); nv_rd32(dev, 0x409904) | 0xc0000000);
nv_wr32(dev, NV03_PGRAPH_INTR, 0x00200000); for (r = 0x409e08; r <= 0x409e24; r += 4)
} NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
nv_rd32(dev, r));
nv_wr32(dev, 0x409e08,
nv_rd32(dev, 0x409e08) | 0xc0000000);
status &= ~0x00200000;
nv_wr32(dev, NV03_PGRAPH_NSOURCE, nsource);
nv_wr32(dev, NV03_PGRAPH_INTR, 0x00200000);
}
if (status) { if (status) {
NV_INFO(dev, "Unhandled PGRAPH_INTR - 0x%08x\n", status); NV_INFO(dev, "Unhandled PGRAPH_INTR - 0x%08x\n",
nv_wr32(dev, NV03_PGRAPH_INTR, status); status);
} nv_wr32(dev, NV03_PGRAPH_INTR, status);
}
{ {
const int isb = (1 << 16) | (1 << 0); const int isb = (1 << 16) | (1 << 0);
if ((nv_rd32(dev, 0x400500) & isb) != isb) if ((nv_rd32(dev, 0x400500) & isb) != isb)
nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) | isb); nv_wr32(dev, 0x400500,
nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31)); nv_rd32(dev, 0x400500) | isb);
}
} }
nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING); nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
} }
static void static void
......
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