Commit b29ee91c authored by Arnd Bergmann's avatar Arnd Bergmann

Merge branch 'imx/fixes-for-3.6' of git://git.linaro.org/people/shawnguo/linux-2.6 into fixes

* 'imx/fixes-for-3.6' of git://git.linaro.org/people/shawnguo/linux-2.6:
  ARM: dts: imx: fix gpio interrupts property
  ARM: dts: imx53-ard: add regulators for lan9220
  ARM: imx: enable emi_slow_gate clock for imx5
  ARM: imx6q-sabrelite: Setup CLKO IOMUX
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents e4651a9f 65dee07c
No related merge requests found
...@@ -53,7 +53,7 @@ pmic: mc13892@0 { ...@@ -53,7 +53,7 @@ pmic: mc13892@0 {
spi-max-frequency = <6000000>; spi-max-frequency = <6000000>;
reg = <0>; reg = <0>;
interrupt-parent = <&gpio1>; interrupt-parent = <&gpio1>;
interrupts = <8>; interrupts = <8 0x4>;
regulators { regulators {
sw1_reg: sw1 { sw1_reg: sw1 {
......
...@@ -64,12 +64,32 @@ lan9220@f4000000 { ...@@ -64,12 +64,32 @@ lan9220@f4000000 {
reg = <0xf4000000 0x2000000>; reg = <0xf4000000 0x2000000>;
phy-mode = "mii"; phy-mode = "mii";
interrupt-parent = <&gpio2>; interrupt-parent = <&gpio2>;
interrupts = <31>; interrupts = <31 0x8>;
reg-io-width = <4>; reg-io-width = <4>;
/*
* VDD33A and VDDVARIO of LAN9220 are supplied by
* SW4_3V3 of LTC3589. Before the regulator driver
* for this PMIC is available, we use a fixed dummy
* 3V3 regulator to get LAN9220 driver probing work.
*/
vdd33a-supply = <&reg_3p3v>;
vddvario-supply = <&reg_3p3v>;
smsc,irq-push-pull; smsc,irq-push-pull;
}; };
}; };
regulators {
compatible = "simple-bus";
reg_3p3v: 3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
gpio-keys { gpio-keys {
compatible = "gpio-keys"; compatible = "gpio-keys";
......
...@@ -53,6 +53,7 @@ pinctrl_gpio_hog: gpiohog { ...@@ -53,6 +53,7 @@ pinctrl_gpio_hog: gpiohog {
fsl,pins = < fsl,pins = <
144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */ 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */ 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
>; >;
}; };
}; };
......
...@@ -303,6 +303,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, ...@@ -303,6 +303,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
clk_prepare_enable(clk[aips_tz2]); /* fec */ clk_prepare_enable(clk[aips_tz2]); /* fec */
clk_prepare_enable(clk[spba]); clk_prepare_enable(clk[spba]);
clk_prepare_enable(clk[emi_fast_gate]); /* fec */ clk_prepare_enable(clk[emi_fast_gate]); /* fec */
clk_prepare_enable(clk[emi_slow_gate]); /* eim */
clk_prepare_enable(clk[tmax1]); clk_prepare_enable(clk[tmax1]);
clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */ clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */
clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */ clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
......
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