Commit b3dfcb20 authored by Michel Dänzer's avatar Michel Dänzer Committed by Alex Deucher

drm/radeon: Enable DMA_IB_SWAP_ENABLE on big endian hosts.

Fixes GPU hang during DMA ring IB test.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=59672Signed-off-by: default avatarMichel Dänzer <michel.daenzer@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1da80cfa
...@@ -1216,7 +1216,7 @@ void cayman_dma_stop(struct radeon_device *rdev) ...@@ -1216,7 +1216,7 @@ void cayman_dma_stop(struct radeon_device *rdev)
int cayman_dma_resume(struct radeon_device *rdev) int cayman_dma_resume(struct radeon_device *rdev)
{ {
struct radeon_ring *ring; struct radeon_ring *ring;
u32 rb_cntl, dma_cntl; u32 rb_cntl, dma_cntl, ib_cntl;
u32 rb_bufsz; u32 rb_bufsz;
u32 reg_offset, wb_offset; u32 reg_offset, wb_offset;
int i, r; int i, r;
...@@ -1265,7 +1265,11 @@ int cayman_dma_resume(struct radeon_device *rdev) ...@@ -1265,7 +1265,11 @@ int cayman_dma_resume(struct radeon_device *rdev)
WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8); WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8);
/* enable DMA IBs */ /* enable DMA IBs */
WREG32(DMA_IB_CNTL + reg_offset, DMA_IB_ENABLE | CMD_VMID_FORCE); ib_cntl = DMA_IB_ENABLE | CMD_VMID_FORCE;
#ifdef __BIG_ENDIAN
ib_cntl |= DMA_IB_SWAP_ENABLE;
#endif
WREG32(DMA_IB_CNTL + reg_offset, ib_cntl);
dma_cntl = RREG32(DMA_CNTL + reg_offset); dma_cntl = RREG32(DMA_CNTL + reg_offset);
dma_cntl &= ~CTXEMPTY_INT_ENABLE; dma_cntl &= ~CTXEMPTY_INT_ENABLE;
......
...@@ -2313,7 +2313,7 @@ void r600_dma_stop(struct radeon_device *rdev) ...@@ -2313,7 +2313,7 @@ void r600_dma_stop(struct radeon_device *rdev)
int r600_dma_resume(struct radeon_device *rdev) int r600_dma_resume(struct radeon_device *rdev)
{ {
struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
u32 rb_cntl, dma_cntl; u32 rb_cntl, dma_cntl, ib_cntl;
u32 rb_bufsz; u32 rb_bufsz;
int r; int r;
...@@ -2353,7 +2353,11 @@ int r600_dma_resume(struct radeon_device *rdev) ...@@ -2353,7 +2353,11 @@ int r600_dma_resume(struct radeon_device *rdev)
WREG32(DMA_RB_BASE, ring->gpu_addr >> 8); WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
/* enable DMA IBs */ /* enable DMA IBs */
WREG32(DMA_IB_CNTL, DMA_IB_ENABLE); ib_cntl = DMA_IB_ENABLE;
#ifdef __BIG_ENDIAN
ib_cntl |= DMA_IB_SWAP_ENABLE;
#endif
WREG32(DMA_IB_CNTL, ib_cntl);
dma_cntl = RREG32(DMA_CNTL); dma_cntl = RREG32(DMA_CNTL);
dma_cntl &= ~CTXEMPTY_INT_ENABLE; dma_cntl &= ~CTXEMPTY_INT_ENABLE;
......
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