Commit b54942f8 authored by Greg Ungerer's avatar Greg Ungerer Committed by Russell King

[ARM] 4391/1: make at91 debug unit support optional

The AT91x40 family doesn't have the debug unit like its bigger brothers.
But it does have the ID and extension registers (with the bit meanings
the same). Reorganize at91_dbgu.h to cater for this.

This also affects the load uncompressor, since it outputs to the
debug port.
Signed-off-by: default avatarGreg Ungerer <gerg@uclinux.org>
Acked-by: default avatarAndrew Victor <andrew@sanpeople.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent d0f9b55e
...@@ -16,6 +16,7 @@ ...@@ -16,6 +16,7 @@
#ifndef AT91_DBGU_H #ifndef AT91_DBGU_H
#define AT91_DBGU_H #define AT91_DBGU_H
#ifdef AT91_DBGU
#define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */ #define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */
#define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */ #define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */
#define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */ #define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */
...@@ -30,6 +31,15 @@ ...@@ -30,6 +31,15 @@
#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */ #define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */
#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */ #define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */
#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */
#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */
#endif /* AT91_DBGU */
/*
* Some AT91 parts that don't have full DEBUG units still support the ID
* and extensions register.
*/
#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */ #define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */
#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */ #define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */
#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */ #define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */
...@@ -53,7 +63,4 @@ ...@@ -53,7 +63,4 @@
#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */ #define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */
#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */ #define AT91_CIDR_EXT (1 << 31) /* Extension Flag */
#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */
#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */
#endif #endif
...@@ -33,20 +33,24 @@ ...@@ -33,20 +33,24 @@
*/ */
static void putc(int c) static void putc(int c)
{ {
#ifdef AT91_DBGU
void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */
while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY))
barrier(); barrier();
__raw_writel(c, sys + AT91_DBGU_THR); __raw_writel(c, sys + AT91_DBGU_THR);
#endif
} }
static inline void flush(void) static inline void flush(void)
{ {
#ifdef AT91_DBGU
void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */
/* wait for transmission to complete */ /* wait for transmission to complete */
while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY)) while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY))
barrier(); barrier();
#endif
} }
#define arch_decomp_setup() #define arch_decomp_setup()
......
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