Commit b574a192 authored by Mark Brown's avatar Mark Brown

Merge tag 'asoc-fix-v4.4-rc6' into asoc-linus

ASoC: Fixes for v4.4

A collection of small driver specific fixes here, nothing that'll affect
users who don't have the devices concerned.  At least the wm8974 bug
indicates that there's not too many users of some of these devices.

# gpg: Signature made Wed 23 Dec 2015 00:25:40 GMT using RSA key ID 5D5487D0
# gpg: Oops: keyid_from_fingerprint: no pubkey
# gpg: Oops: keyid_from_fingerprint: no pubkey
# gpg: key 00000000 occurs more than once in the trustdb
# gpg: key 16005C11: no public key for trusted key - skipped
# gpg: key 16005C11 marked as ultimately trusted
# gpg: Good signature from "Mark Brown <broonie@sirena.org.uk>"
# gpg:                 aka "Mark Brown <broonie@debian.org>"
# gpg:                 aka "Mark Brown <broonie@kernel.org>"
# gpg:                 aka "Mark Brown <broonie@tardis.ed.ac.uk>"
# gpg:                 aka "Mark Brown <broonie@linaro.org>"
# gpg:                 aka "Mark Brown <Mark.Brown@linaro.org>"
parents 4ef76753 3dd5fc0e
...@@ -85,7 +85,15 @@ static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0); ...@@ -85,7 +85,15 @@ static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0);
static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0); static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 300, 0); static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 300, 0);
static const int deemph_settings[] = { 0, 32000, 44100, 48000 }; static const struct {
int rate;
unsigned int val;
} deemph_settings[] = {
{ 0, ES8328_DACCONTROL6_DEEMPH_OFF },
{ 32000, ES8328_DACCONTROL6_DEEMPH_32k },
{ 44100, ES8328_DACCONTROL6_DEEMPH_44_1k },
{ 48000, ES8328_DACCONTROL6_DEEMPH_48k },
};
static int es8328_set_deemph(struct snd_soc_codec *codec) static int es8328_set_deemph(struct snd_soc_codec *codec)
{ {
...@@ -97,21 +105,22 @@ static int es8328_set_deemph(struct snd_soc_codec *codec) ...@@ -97,21 +105,22 @@ static int es8328_set_deemph(struct snd_soc_codec *codec)
* rate. * rate.
*/ */
if (es8328->deemph) { if (es8328->deemph) {
best = 1; best = 0;
for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) { for (i = 1; i < ARRAY_SIZE(deemph_settings); i++) {
if (abs(deemph_settings[i] - es8328->playback_fs) < if (abs(deemph_settings[i].rate - es8328->playback_fs) <
abs(deemph_settings[best] - es8328->playback_fs)) abs(deemph_settings[best].rate - es8328->playback_fs))
best = i; best = i;
} }
val = best << 1; val = deemph_settings[best].val;
} else { } else {
val = 0; val = ES8328_DACCONTROL6_DEEMPH_OFF;
} }
dev_dbg(codec->dev, "Set deemphasis %d\n", val); dev_dbg(codec->dev, "Set deemphasis %d\n", val);
return snd_soc_update_bits(codec, ES8328_DACCONTROL6, 0x6, val); return snd_soc_update_bits(codec, ES8328_DACCONTROL6,
ES8328_DACCONTROL6_DEEMPH_MASK, val);
} }
static int es8328_get_deemph(struct snd_kcontrol *kcontrol, static int es8328_get_deemph(struct snd_kcontrol *kcontrol,
......
...@@ -153,6 +153,7 @@ int es8328_probe(struct device *dev, struct regmap *regmap); ...@@ -153,6 +153,7 @@ int es8328_probe(struct device *dev, struct regmap *regmap);
#define ES8328_DACCONTROL6_CLICKFREE (1 << 3) #define ES8328_DACCONTROL6_CLICKFREE (1 << 3)
#define ES8328_DACCONTROL6_DAC_INVR (1 << 4) #define ES8328_DACCONTROL6_DAC_INVR (1 << 4)
#define ES8328_DACCONTROL6_DAC_INVL (1 << 5) #define ES8328_DACCONTROL6_DAC_INVL (1 << 5)
#define ES8328_DACCONTROL6_DEEMPH_MASK (3 << 6)
#define ES8328_DACCONTROL6_DEEMPH_OFF (0 << 6) #define ES8328_DACCONTROL6_DEEMPH_OFF (0 << 6)
#define ES8328_DACCONTROL6_DEEMPH_32k (1 << 6) #define ES8328_DACCONTROL6_DEEMPH_32k (1 << 6)
#define ES8328_DACCONTROL6_DEEMPH_44_1k (2 << 6) #define ES8328_DACCONTROL6_DEEMPH_44_1k (2 << 6)
......
...@@ -189,6 +189,7 @@ static int power_vag_event(struct snd_soc_dapm_widget *w, ...@@ -189,6 +189,7 @@ static int power_vag_event(struct snd_soc_dapm_widget *w,
case SND_SOC_DAPM_POST_PMU: case SND_SOC_DAPM_POST_PMU:
snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP); SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
msleep(400);
break; break;
case SND_SOC_DAPM_PRE_PMD: case SND_SOC_DAPM_PRE_PMD:
......
...@@ -574,6 +574,7 @@ static const struct regmap_config wm8974_regmap = { ...@@ -574,6 +574,7 @@ static const struct regmap_config wm8974_regmap = {
.max_register = WM8974_MONOMIX, .max_register = WM8974_MONOMIX,
.reg_defaults = wm8974_reg_defaults, .reg_defaults = wm8974_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8974_reg_defaults), .num_reg_defaults = ARRAY_SIZE(wm8974_reg_defaults),
.cache_type = REGCACHE_FLAT,
}; };
static int wm8974_probe(struct snd_soc_codec *codec) static int wm8974_probe(struct snd_soc_codec *codec)
......
...@@ -223,8 +223,8 @@ static void mcasp_start_tx(struct davinci_mcasp *mcasp) ...@@ -223,8 +223,8 @@ static void mcasp_start_tx(struct davinci_mcasp *mcasp)
/* wait for XDATA to be cleared */ /* wait for XDATA to be cleared */
cnt = 0; cnt = 0;
while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
~XRDATA) && (cnt < 100000)) (cnt < 100000))
cnt++; cnt++;
/* Release TX state machine */ /* Release TX state machine */
......
...@@ -505,6 +505,24 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, ...@@ -505,6 +505,24 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
regmap_update_bits(sai->regmap, FSL_SAI_RCSR, regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
/*
* For sai master mode, after several open/close sai,
* there will be no frame clock, and can't recover
* anymore. Add software reset to fix this issue.
* This is a hardware bug, and will be fix in the
* next sai version.
*/
if (!sai->is_slave_mode) {
/* Software Reset for both Tx and Rx */
regmap_write(sai->regmap,
FSL_SAI_TCSR, FSL_SAI_CSR_SR);
regmap_write(sai->regmap,
FSL_SAI_RCSR, FSL_SAI_CSR_SR);
/* Clear SR bit to finish the reset */
regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
}
} }
break; break;
default: default:
......
...@@ -152,8 +152,10 @@ static int rk_spdif_trigger(struct snd_pcm_substream *substream, ...@@ -152,8 +152,10 @@ static int rk_spdif_trigger(struct snd_pcm_substream *substream,
case SNDRV_PCM_TRIGGER_RESUME: case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR, ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
SPDIF_DMACR_TDE_ENABLE, SPDIF_DMACR_TDE_ENABLE |
SPDIF_DMACR_TDE_ENABLE); SPDIF_DMACR_TDL_MASK,
SPDIF_DMACR_TDE_ENABLE |
SPDIF_DMACR_TDL(16));
if (ret != 0) if (ret != 0)
return ret; return ret;
......
...@@ -42,7 +42,7 @@ ...@@ -42,7 +42,7 @@
#define SPDIF_DMACR_TDL_SHIFT 0 #define SPDIF_DMACR_TDL_SHIFT 0
#define SPDIF_DMACR_TDL(x) ((x) << SPDIF_DMACR_TDL_SHIFT) #define SPDIF_DMACR_TDL(x) ((x) << SPDIF_DMACR_TDL_SHIFT)
#define SPDIF_DMACR_TDL_MASK (0x1f << SDPIF_DMACR_TDL_SHIFT) #define SPDIF_DMACR_TDL_MASK (0x1f << SPDIF_DMACR_TDL_SHIFT)
/* /*
* XFER * XFER
......
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