Commit b5a6455c authored by Zubair Lutfullah Kakakhel's avatar Zubair Lutfullah Kakakhel Committed by Ralf Baechle

MIPS: Detect DSP v3 support

DSPv3 is supported on all MIPSr6 systems which indicate support for DSPv2.

This doesn't require any changes to the kernel's handling of DSP
resources. The patch is to detect support and indicate it in /proc/cpuinfo

DSP v3 introduces a new instruction BPOSGE32C
Signed-off-by: default avatarZubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Reviewed-by: default avatarPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12918/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 157b9394
...@@ -307,6 +307,10 @@ ...@@ -307,6 +307,10 @@
#define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P) #define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P)
#endif #endif
#ifndef cpu_has_dsp3
#define cpu_has_dsp3 (cpu_data[0].ases & MIPS_ASE_DSP3)
#endif
#ifndef cpu_has_mipsmt #ifndef cpu_has_mipsmt
#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) #define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
#endif #endif
......
...@@ -413,5 +413,6 @@ enum cpu_type_enum { ...@@ -413,5 +413,6 @@ enum cpu_type_enum {
#define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */ #define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */
#define MIPS_ASE_VZ 0x00000080 /* Virtualization ASE */ #define MIPS_ASE_VZ 0x00000080 /* Virtualization ASE */
#define MIPS_ASE_MSA 0x00000100 /* MIPS SIMD Architecture */ #define MIPS_ASE_MSA 0x00000100 /* MIPS SIMD Architecture */
#define MIPS_ASE_DSP3 0x00000200 /* Signal Processing ASE Rev 3*/
#endif /* _ASM_CPU_H */ #endif /* _ASM_CPU_H */
...@@ -680,8 +680,11 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) ...@@ -680,8 +680,11 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
c->options |= MIPS_CPU_RIXI; c->options |= MIPS_CPU_RIXI;
if (config3 & MIPS_CONF3_DSP) if (config3 & MIPS_CONF3_DSP)
c->ases |= MIPS_ASE_DSP; c->ases |= MIPS_ASE_DSP;
if (config3 & MIPS_CONF3_DSP2P) if (config3 & MIPS_CONF3_DSP2P) {
c->ases |= MIPS_ASE_DSP2P; c->ases |= MIPS_ASE_DSP2P;
if (cpu_has_mips_r6)
c->ases |= MIPS_ASE_DSP3;
}
if (config3 & MIPS_CONF3_VINT) if (config3 & MIPS_CONF3_VINT)
c->options |= MIPS_CPU_VINT; c->options |= MIPS_CPU_VINT;
if (config3 & MIPS_CONF3_VEIC) if (config3 & MIPS_CONF3_VEIC)
......
...@@ -114,6 +114,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) ...@@ -114,6 +114,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
if (cpu_has_smartmips) seq_printf(m, "%s", " smartmips"); if (cpu_has_smartmips) seq_printf(m, "%s", " smartmips");
if (cpu_has_dsp) seq_printf(m, "%s", " dsp"); if (cpu_has_dsp) seq_printf(m, "%s", " dsp");
if (cpu_has_dsp2) seq_printf(m, "%s", " dsp2"); if (cpu_has_dsp2) seq_printf(m, "%s", " dsp2");
if (cpu_has_dsp3) seq_printf(m, "%s", " dsp3");
if (cpu_has_mipsmt) seq_printf(m, "%s", " mt"); if (cpu_has_mipsmt) seq_printf(m, "%s", " mt");
if (cpu_has_mmips) seq_printf(m, "%s", " micromips"); if (cpu_has_mmips) seq_printf(m, "%s", " micromips");
if (cpu_has_vz) seq_printf(m, "%s", " vz"); if (cpu_has_vz) seq_printf(m, "%s", " vz");
......
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