[PATCH] fbdev: Revive BIOS-less booting for Rage XL cards

The file drivers/video/aty/xlinit.c is currently unused.  This file might be
useful to boot some types of RageXL cards on non-x86 platforms.
Signed-off-by: Antonino Daplas <adaplas@pol.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

drivers/video/aty/Makefile

@@ -5,6 +5,8 @@ obj-$(CONFIG_FB_RADEON) += radeonfb.o
 atyfb-y				:= atyfb_base.o mach64_accel.o mach64_cursor.o
 atyfb-$(CONFIG_FB_ATY_GX)	+= mach64_gx.o
 atyfb-$(CONFIG_FB_ATY_CT)	+= mach64_ct.o
+atyfb-$(CONFIG_FB_ATY_XL_INIT)  += xlinit.o
+
 atyfb-objs			:= $(atyfb-y)
 
 radeonfb-y			:= radeon_base.o radeon_pm.o radeon_monitor.o radeon_accel.o

drivers/video/aty/atyfb.h

@@ -83,13 +83,13 @@ struct pll_ct {
 	u8 pll_gen_cntl;
 	u8 mclk_fb_div;
 	u8 mclk_fb_mult; /* 2 ro 4 */
-/*	u8 sclk_fb_div;*/
+	u8 sclk_fb_div;
 	u8 pll_vclk_cntl;
 	u8 vclk_post_div;
 	u8 vclk_fb_div;
 	u8 pll_ext_cntl;
-/*	u8 ext_vpll_cntl;
-	u8 spll_cntl2;*/
+	u8 ext_vpll_cntl;
+	u8 spll_cntl2;
 	u32 dsp_config; /* Mach64 GTB DSP */
 	u32 dsp_on_off; /* Mach64 GTB DSP */
 	u32 dsp_loop_latency;
@@ -215,7 +215,6 @@ struct atyfb_par {
 #define M64F_XL_DLL		0x00080000
 #define M64F_MFB_FORCE_4	0x00100000
 #define M64F_HW_TRIPLE		0x00200000
-
     /*
      *  Register access
      */
@@ -246,6 +245,19 @@ static inline void aty_st_le32(int regindex, u32 val, const struct atyfb_par *pa
 #endif
 }
 
+static inline void aty_st_le16(int regindex, u16 val,
+			       const struct atyfb_par *par)
+{
+	/* Hack for bloc 1, should be cleanly optimized by compiler */
+	if (regindex >= 0x400)
+		regindex -= 0x800;
+#ifdef CONFIG_ATARI
+	out_le16((volatile u16 *)(par->ati_regbase + regindex), val);
+#else
+	writel(val, par->ati_regbase + regindex);
+#endif
+}
+
 static inline u8 aty_ld_8(int regindex, const struct atyfb_par *par)
 {
 	/* Hack for bloc 1, should be cleanly optimized by compiler */
@@ -343,4 +355,6 @@ static inline void wait_for_idle(struct atyfb_par *par)
 
 extern void aty_reset_engine(const struct atyfb_par *par);
 extern void aty_init_engine(struct atyfb_par *par, struct fb_info *info);
-
+extern int  atyfb_xl_init(struct fb_info *info);
+extern void aty_st_pll_ct(int offset, u8 val, const struct atyfb_par *par);
+extern u8   aty_ld_pll_ct(int offset, const struct atyfb_par *par);

drivers/video/aty/atyfb_base.c

@@ -2279,9 +2279,12 @@ static int __init aty_init(struct fb_info *info, const char *name)
 		par->dac_ops = &aty_dac_ct;
 		par->pll_ops = &aty_pll_ct;
 		par->bus_type = PCI;
+#ifdef CONFIG_FB_ATY_XL_INIT
+		if (IS_XL(par->pci_id))
+			atyfb_xl_init(info);
+#endif
 		par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
 		ramname = aty_ct_ram[par->ram_type];
-
 		/* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
 		if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
 			par->pll_limits.mclk = 63;

drivers/video/aty/xlinit.c

@@ -105,19 +105,6 @@ static const lcd_tbl_t lcd_tbl[] = {
 	{ 0x37,	0x00000000 }
 };
 
-static inline u32 aty_ld_lcd(u8 lcd_reg, struct atyfb_par *par)
-{
-	aty_st_8(LCD_INDEX, lcd_reg, par);
-	return aty_ld_le32(LCD_DATA, par);
-}
-
-static inline void aty_st_lcd(u8 lcd_reg, u32 val,
-			      struct atyfb_par *par)
-{
-	aty_st_8(LCD_INDEX, lcd_reg, par);
-	aty_st_le32(LCD_DATA, val, par);
-}
-
 static void reset_gui(struct atyfb_par *par)
 {
 	aty_st_8(GEN_TEST_CNTL+1, 0x01, par);
@@ -205,7 +192,7 @@ int atyfb_xl_init(struct fb_info *info)
 		// the MCLK, XCLK are 120MHz on victoria card
 		par->mclk_per = 1000000/120;
 		par->xclk_per = 1000000/120;
-		par->features &= ~M64F_MFB_TIMES_4;
+		par->features &= ~M64F_MFB_FORCE_4;
 	}
 	
 	/*