Commit b83db1de authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6

* 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6:
  drm/radeon/kms: enable unmappable vram for evergreen
  drm/radeon/kms: fix tiled db height calculation on 6xx/7xx
  drm/radeon/kms: fix handling of tex lookup disable in cs checker on r2xx
parents 7d2f280e 7e942503
...@@ -495,6 +495,7 @@ int evergreen_blit_init(struct radeon_device *rdev) ...@@ -495,6 +495,7 @@ int evergreen_blit_init(struct radeon_device *rdev)
dev_err(rdev->dev, "(%d) pin blit object failed\n", r); dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
return r; return r;
} }
rdev->mc.active_vram_size = rdev->mc.real_vram_size;
return 0; return 0;
} }
...@@ -502,6 +503,7 @@ void evergreen_blit_fini(struct radeon_device *rdev) ...@@ -502,6 +503,7 @@ void evergreen_blit_fini(struct radeon_device *rdev)
{ {
int r; int r;
rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
if (rdev->r600_blit.shader_obj == NULL) if (rdev->r600_blit.shader_obj == NULL)
return; return;
/* If we can't reserve the bo, unref should be enough to destroy /* If we can't reserve the bo, unref should be enough to destroy
......
...@@ -3180,6 +3180,8 @@ static int r100_cs_track_texture_check(struct radeon_device *rdev, ...@@ -3180,6 +3180,8 @@ static int r100_cs_track_texture_check(struct radeon_device *rdev,
for (u = 0; u < track->num_texture; u++) { for (u = 0; u < track->num_texture; u++) {
if (!track->textures[u].enabled) if (!track->textures[u].enabled)
continue; continue;
if (track->textures[u].lookup_disable)
continue;
robj = track->textures[u].robj; robj = track->textures[u].robj;
if (robj == NULL) { if (robj == NULL) {
DRM_ERROR("No texture bound to unit %u\n", u); DRM_ERROR("No texture bound to unit %u\n", u);
...@@ -3414,6 +3416,7 @@ void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track ...@@ -3414,6 +3416,7 @@ void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track
track->textures[i].robj = NULL; track->textures[i].robj = NULL;
/* CS IB emission code makes sure texture unit are disabled */ /* CS IB emission code makes sure texture unit are disabled */
track->textures[i].enabled = false; track->textures[i].enabled = false;
track->textures[i].lookup_disable = false;
track->textures[i].roundup_w = true; track->textures[i].roundup_w = true;
track->textures[i].roundup_h = true; track->textures[i].roundup_h = true;
if (track->separate_cube) if (track->separate_cube)
......
...@@ -46,6 +46,7 @@ struct r100_cs_track_texture { ...@@ -46,6 +46,7 @@ struct r100_cs_track_texture {
unsigned height_11; unsigned height_11;
bool use_pitch; bool use_pitch;
bool enabled; bool enabled;
bool lookup_disable;
bool roundup_w; bool roundup_w;
bool roundup_h; bool roundup_h;
unsigned compress_format; unsigned compress_format;
......
...@@ -447,6 +447,8 @@ int r200_packet0_check(struct radeon_cs_parser *p, ...@@ -447,6 +447,8 @@ int r200_packet0_check(struct radeon_cs_parser *p,
track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
} }
if (idx_value & R200_TXFORMAT_LOOKUP_DISABLE)
track->textures[i].lookup_disable = true;
switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
case R200_TXFORMAT_I8: case R200_TXFORMAT_I8:
case R200_TXFORMAT_RGB332: case R200_TXFORMAT_RGB332:
......
...@@ -310,7 +310,7 @@ static int r600_cs_track_check(struct radeon_cs_parser *p) ...@@ -310,7 +310,7 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
/* Check depth buffer */ /* Check depth buffer */
if (G_028800_STENCIL_ENABLE(track->db_depth_control) || if (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
G_028800_Z_ENABLE(track->db_depth_control)) { G_028800_Z_ENABLE(track->db_depth_control)) {
u32 nviews, bpe, ntiles, pitch, pitch_align, height, size; u32 nviews, bpe, ntiles, pitch, pitch_align, height, size, slice_tile_max;
if (track->db_bo == NULL) { if (track->db_bo == NULL) {
dev_warn(p->dev, "z/stencil with no depth buffer\n"); dev_warn(p->dev, "z/stencil with no depth buffer\n");
return -EINVAL; return -EINVAL;
...@@ -354,11 +354,11 @@ static int r600_cs_track_check(struct radeon_cs_parser *p) ...@@ -354,11 +354,11 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
} else { } else {
size = radeon_bo_size(track->db_bo); size = radeon_bo_size(track->db_bo);
pitch = G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1; pitch = G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1;
height = size / (pitch * 8 * bpe); slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
height &= ~0x7; slice_tile_max *= 64;
if (!height) height = slice_tile_max / (pitch * 8);
height = 8; if (height > 8192)
height = 8192;
switch (G_028010_ARRAY_MODE(track->db_depth_info)) { switch (G_028010_ARRAY_MODE(track->db_depth_info)) {
case V_028010_ARRAY_1D_TILED_THIN1: case V_028010_ARRAY_1D_TILED_THIN1:
pitch_align = (max((u32)8, (u32)(track->group_size / (8 * bpe))) / 8); pitch_align = (max((u32)8, (u32)(track->group_size / (8 * bpe))) / 8);
...@@ -367,6 +367,8 @@ static int r600_cs_track_check(struct radeon_cs_parser *p) ...@@ -367,6 +367,8 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
__func__, __LINE__, pitch); __func__, __LINE__, pitch);
return -EINVAL; return -EINVAL;
} }
/* don't break userspace */
height &= ~0x7;
if (!IS_ALIGNED(height, 8)) { if (!IS_ALIGNED(height, 8)) {
dev_warn(p->dev, "%s:%d db height (%d) invalid\n", dev_warn(p->dev, "%s:%d db height (%d) invalid\n",
__func__, __LINE__, height); __func__, __LINE__, height);
......
...@@ -2836,6 +2836,7 @@ ...@@ -2836,6 +2836,7 @@
# define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24) # define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24)
# define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24) # define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24)
# define R200_TXFORMAT_ST_ROUTE_SHIFT 24 # define R200_TXFORMAT_ST_ROUTE_SHIFT 24
# define R200_TXFORMAT_LOOKUP_DISABLE (1 << 27)
# define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) # define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28)
# define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) # define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29)
# define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) # define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30)
......
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