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Commit ba73d4c8 authored by David S. Miller's avatar David S. Miller
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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/linville/wireless-2.6.26

parents b8ad0cbc deedf504
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Showing with 10988 additions and 3552 deletions
Documentation/DocBook/Makefile
View file @ ba73d4c8
......@@ -11,7 +11,8 @@ DOCBOOKS := wanbook.xml z8530book.xml mcabook.xml videobook.xml \
procfs-guide.xml writing_usb_driver.xml networking.xml \
kernel-api.xml filesystems.xml lsm.xml usb.xml \
gadget.xml libata.xml mtdnand.xml librs.xml rapidio.xml \
genericirq.xml s390-drivers.xml uio-howto.xml scsi.xml
genericirq.xml s390-drivers.xml uio-howto.xml scsi.xml \
mac80211.xml
###
# The build process is as follows (targets):
......
Documentation/DocBook/mac80211.tmpl 0 → 100644
View file @ ba73d4c8
This diff is collapsed.
drivers/net/wireless/ath5k/ath5k.h
View file @ ba73d4c8
......@@ -140,7 +140,8 @@ enum ath5k_radio {
AR5K_RF5110 = 0,
AR5K_RF5111 = 1,
AR5K_RF5112 = 2,
AR5K_RF5413 = 3,
AR5K_RF2413 = 3,
AR5K_RF5413 = 4,
};
/*
......@@ -168,12 +169,15 @@ struct ath5k_srev_name {
#define AR5K_SREV_VER_AR5212 0x50
#define AR5K_SREV_VER_AR5213 0x55
#define AR5K_SREV_VER_AR5213A 0x59
#define AR5K_SREV_VER_AR2424 0xa0
#define AR5K_SREV_VER_AR5424 0xa3
#define AR5K_SREV_VER_AR2413 0x78
#define AR5K_SREV_VER_AR2414 0x79
#define AR5K_SREV_VER_AR2424 0xa0 /* PCI-E */
#define AR5K_SREV_VER_AR5424 0xa3 /* PCI-E */
#define AR5K_SREV_VER_AR5413 0xa4
#define AR5K_SREV_VER_AR5414 0xa5
#define AR5K_SREV_VER_AR5416 0xc0 /* ? */
#define AR5K_SREV_VER_AR5418 0xca
#define AR5K_SREV_VER_AR5416 0xc0 /* PCI-E */
#define AR5K_SREV_VER_AR5418 0xca /* PCI-E */
#define AR5K_SREV_VER_AR2425 0xe2 /* PCI-E */
#define AR5K_SREV_RAD_5110 0x00
#define AR5K_SREV_RAD_5111 0x10
......@@ -183,8 +187,9 @@ struct ath5k_srev_name {
#define AR5K_SREV_RAD_5112A 0x35
#define AR5K_SREV_RAD_2112 0x40
#define AR5K_SREV_RAD_2112A 0x45
#define AR5K_SREV_RAD_SC0 0x56 /* Found on 2413/2414 */
#define AR5K_SREV_RAD_SC1 0x63 /* Found on 5413/5414 */
#define AR5K_SREV_RAD_SC2 0xa2 /* Found on 2424/5424 */
#define AR5K_SREV_RAD_SC2 0xa2 /* Found on 2424-5/5424 */
#define AR5K_SREV_RAD_5133 0xc0 /* MIMO found on 5418 */
/* IEEE defs */
......@@ -268,12 +273,13 @@ enum ath5k_driver_mode {
#define SHPREAMBLE_FLAG(_ix) \
(HAS_SHPREAMBLE(_ix) ? AR5K_SET_SHORT_PREAMBLE : 0)
/****************\
TX DEFINITIONS
\****************/
/*
* Tx Descriptor
* TX Status
*/
struct ath5k_tx_status {
u16 ts_seqnum;
......@@ -421,7 +427,7 @@ enum ath5k_dmasize {
\****************/
/*
* Rx Descriptor
* RX Status
*/
struct ath5k_rx_status {
u16 rs_datalen;
......@@ -452,8 +458,6 @@ struct ath5k_mib_stats {
};
/**************************\
BEACON TIMERS DEFINITIONS
\**************************/
......@@ -495,29 +499,23 @@ struct ath5k_beacon_state {
#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
/********************\
COMMON DEFINITIONS
\********************/
/*
* Atheros descriptor
* Atheros hardware descriptor
* This is read and written to by the hardware
*/
struct ath5k_desc {
u32 ds_link;
u32 ds_data;
u32 ds_ctl0;
u32 ds_ctl1;
u32 ds_hw[4];
u32 ds_link; /* physical address of the next descriptor */
u32 ds_data; /* physical address of data buffer (skb) */
union {
struct ath5k_rx_status rx;
struct ath5k_tx_status tx;
} ds_us;
#define ds_rxstat ds_us.rx
#define ds_txstat ds_us.tx
struct ath5k_hw_5210_tx_desc ds_tx5210;
struct ath5k_hw_5212_tx_desc ds_tx5212;
struct ath5k_hw_all_rx_desc ds_rx;
} ud;
} __packed;
#define AR5K_RXDESC_INTREQ 0x0020
......@@ -961,6 +959,7 @@ struct ath5k_hw {
u16 ah_phy_revision;
u16 ah_radio_5ghz_revision;
u16 ah_radio_2ghz_revision;
u32 ah_phy_spending;
enum ath5k_version ah_version;
enum ath5k_radio ah_radio;
......@@ -1036,8 +1035,10 @@ struct ath5k_hw {
int (*ah_setup_xtx_desc)(struct ath5k_hw *, struct ath5k_desc *,
unsigned int, unsigned int, unsigned int, unsigned int,
unsigned int, unsigned int);
int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *);
int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *);
int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
struct ath5k_tx_status *);
int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
struct ath5k_rx_status *);
};
/*
......
drivers/net/wireless/ath5k/base.c
View file @ ba73d4c8
This diff is collapsed.
drivers/net/wireless/ath5k/debug.c
View file @ ba73d4c8
......@@ -200,7 +200,8 @@ static ssize_t read_file_tsf(struct file *file, char __user *user_buf,
{
struct ath5k_softc *sc = file->private_data;
char buf[100];
snprintf(buf, sizeof(buf), "0x%016llx\n", ath5k_hw_get_tsf64(sc->ah));
snprintf(buf, sizeof(buf), "0x%016llx\n",
(unsigned long long)ath5k_hw_get_tsf64(sc->ah));
return simple_read_from_buffer(user_buf, count, ppos, buf, 19);
}
......@@ -271,7 +272,8 @@ static ssize_t read_file_beacon(struct file *file, char __user *user_buf,
tsf = ath5k_hw_get_tsf64(sc->ah);
len += snprintf(buf+len, sizeof(buf)-len,
"TSF\t\t0x%016llx\tTU: %08x\n", tsf, TSF_TO_TU(tsf));
"TSF\t\t0x%016llx\tTU: %08x\n",
(unsigned long long)tsf, TSF_TO_TU(tsf));
return simple_read_from_buffer(user_buf, count, ppos, buf, len);
}
......@@ -497,15 +499,18 @@ ath5k_debug_dump_bands(struct ath5k_softc *sc)
}
static inline void
ath5k_debug_printrxbuf(struct ath5k_buf *bf, int done)
ath5k_debug_printrxbuf(struct ath5k_buf *bf, int done,
struct ath5k_rx_status *rs)
{
struct ath5k_desc *ds = bf->desc;
struct ath5k_hw_all_rx_desc *rd = &ds->ud.ds_rx;
printk(KERN_DEBUG "R (%p %llx) %08x %08x %08x %08x %08x %08x %c\n",
ds, (unsigned long long)bf->daddr,
ds->ds_link, ds->ds_data, ds->ds_ctl0, ds->ds_ctl1,
ds->ds_hw[0], ds->ds_hw[1],
!done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!');
ds->ds_link, ds->ds_data,
rd->rx_ctl.rx_control_0, rd->rx_ctl.rx_control_1,
rd->u.rx_stat.rx_status_0, rd->u.rx_stat.rx_status_0,
!done ? ' ' : (rs->rs_status == 0) ? '*' : '!');
}
void
......@@ -513,6 +518,7 @@ ath5k_debug_printrxbuffs(struct ath5k_softc *sc, struct ath5k_hw *ah)
{
struct ath5k_desc *ds;
struct ath5k_buf *bf;
struct ath5k_rx_status rs = {};
int status;
if (likely(!(sc->debug.level & ATH5K_DEBUG_RESET)))
......@@ -524,9 +530,9 @@ ath5k_debug_printrxbuffs(struct ath5k_softc *sc, struct ath5k_hw *ah)
spin_lock_bh(&sc->rxbuflock);
list_for_each_entry(bf, &sc->rxbuf, list) {
ds = bf->desc;
status = ah->ah_proc_rx_desc(ah, ds);
status = ah->ah_proc_rx_desc(ah, ds, &rs);
if (!status)
ath5k_debug_printrxbuf(bf, status == 0);
ath5k_debug_printrxbuf(bf, status == 0, &rs);
}
spin_unlock_bh(&sc->rxbuflock);
}
......@@ -550,19 +556,24 @@ ath5k_debug_dump_skb(struct ath5k_softc *sc,
}
void
ath5k_debug_printtxbuf(struct ath5k_softc *sc,
struct ath5k_buf *bf, int done)
ath5k_debug_printtxbuf(struct ath5k_softc *sc, struct ath5k_buf *bf)
{
struct ath5k_desc *ds = bf->desc;
struct ath5k_hw_5212_tx_desc *td = &ds->ud.ds_tx5212;
struct ath5k_tx_status ts = {};
int done;
if (likely(!(sc->debug.level & ATH5K_DEBUG_RESET)))
return;
done = sc->ah->ah_proc_tx_desc(sc->ah, bf->desc, &ts);
printk(KERN_DEBUG "T (%p %llx) %08x %08x %08x %08x %08x %08x %08x "
"%08x %c\n", ds, (unsigned long long)bf->daddr, ds->ds_link,
ds->ds_data, ds->ds_ctl0, ds->ds_ctl1,
ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3],
!done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!');
ds->ds_data, td->tx_ctl.tx_control_0, td->tx_ctl.tx_control_1,
td->tx_ctl.tx_control_2, td->tx_ctl.tx_control_3,
td->tx_stat.tx_status_0, td->tx_stat.tx_status_1,
done ? ' ' : (ts.ts_status == 0) ? '*' : '!');
}
#endif /* ifdef CONFIG_ATH5K_DEBUG */
drivers/net/wireless/ath5k/debug.h
View file @ ba73d4c8
......@@ -160,8 +160,7 @@ ath5k_debug_dump_skb(struct ath5k_softc *sc,
struct sk_buff *skb, const char *prefix, int tx);
void
ath5k_debug_printtxbuf(struct ath5k_softc *sc,
struct ath5k_buf *bf, int done);
ath5k_debug_printtxbuf(struct ath5k_softc *sc, struct ath5k_buf *bf);
#else /* no debugging */
......@@ -199,8 +198,7 @@ ath5k_debug_dump_skb(struct ath5k_softc *sc,
struct sk_buff *skb, const char *prefix, int tx) {}
static inline void
ath5k_debug_printtxbuf(struct ath5k_softc *sc,
struct ath5k_buf *bf, int done) {}
ath5k_debug_printtxbuf(struct ath5k_softc *sc, struct ath5k_buf *bf) {}
#endif /* ifdef CONFIG_ATH5K_DEBUG */
......
drivers/net/wireless/ath5k/hw.c
View file @ ba73d4c8
This diff is collapsed.
drivers/net/wireless/ath5k/hw.h
View file @ ba73d4c8
......@@ -173,7 +173,10 @@ struct ath5k_eeprom_info {
* (rX: reserved fields possibily used by future versions of the ar5k chipset)
*/
struct ath5k_rx_desc {
/*
* common hardware RX control descriptor
*/
struct ath5k_hw_rx_ctl {
u32 rx_control_0; /* RX control word 0 */
#define AR5K_DESC_RX_CTL0 0x00000000
......@@ -185,69 +188,63 @@ struct ath5k_rx_desc {
} __packed;
/*
* 5210/5211 rx status descriptor
* common hardware RX status descriptor
* 5210/11 and 5212 differ only in the flags defined below
*/
struct ath5k_hw_old_rx_status {
struct ath5k_hw_rx_status {
u32 rx_status_0; /* RX status word 0 */
#define AR5K_OLD_RX_DESC_STATUS0_DATA_LEN 0x00000fff
#define AR5K_OLD_RX_DESC_STATUS0_MORE 0x00001000
#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE 0x00078000
#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE_S 15
#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x07f80000
#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 19
#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA 0x38000000
#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 27
u32 rx_status_1; /* RX status word 1 */
#define AR5K_OLD_RX_DESC_STATUS1_DONE 0x00000001
#define AR5K_OLD_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002
#define AR5K_OLD_RX_DESC_STATUS1_CRC_ERROR 0x00000004
#define AR5K_OLD_RX_DESC_STATUS1_FIFO_OVERRUN 0x00000008
#define AR5K_OLD_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000010
#define AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR 0x000000e0
#define AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR_S 5
#define AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100
#define AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX 0x00007e00
#define AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_S 9
#define AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000
#define AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 15
#define AR5K_OLD_RX_DESC_STATUS1_KEY_CACHE_MISS 0x10000000
} __packed;
/* 5210/5211 */
#define AR5K_5210_RX_DESC_STATUS0_DATA_LEN 0x00000fff
#define AR5K_5210_RX_DESC_STATUS0_MORE 0x00001000
#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE 0x00078000
#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE_S 15
#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x07f80000
#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 19
#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA 0x38000000
#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 27
#define AR5K_5210_RX_DESC_STATUS1_DONE 0x00000001
#define AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002
#define AR5K_5210_RX_DESC_STATUS1_CRC_ERROR 0x00000004
#define AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN 0x00000008
#define AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000010
#define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR 0x000000e0
#define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR_S 5
#define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100
#define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX 0x00007e00
#define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_S 9
#define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000
#define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 15
#define AR5K_5210_RX_DESC_STATUS1_KEY_CACHE_MISS 0x10000000
/* 5212 */
#define AR5K_5212_RX_DESC_STATUS0_DATA_LEN 0x00000fff
#define AR5K_5212_RX_DESC_STATUS0_MORE 0x00001000
#define AR5K_5212_RX_DESC_STATUS0_DECOMP_CRC_ERROR 0x00002000
#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE 0x000f8000
#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE_S 15
#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x0ff00000
#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 20
#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA 0xf0000000
#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 28
#define AR5K_5212_RX_DESC_STATUS1_DONE 0x00000001
#define AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002
#define AR5K_5212_RX_DESC_STATUS1_CRC_ERROR 0x00000004
#define AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000008
#define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR 0x00000010
#define AR5K_5212_RX_DESC_STATUS1_MIC_ERROR 0x00000020
#define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100
#define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX 0x0000fe00
#define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_S 9
#define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x7fff0000
#define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 16
#define AR5K_5212_RX_DESC_STATUS1_KEY_CACHE_MISS 0x80000000
/*
* 5212 rx status descriptor
* common hardware RX error descriptor
*/
struct ath5k_hw_new_rx_status {
u32 rx_status_0; /* RX status word 0 */
#define AR5K_NEW_RX_DESC_STATUS0_DATA_LEN 0x00000fff
#define AR5K_NEW_RX_DESC_STATUS0_MORE 0x00001000
#define AR5K_NEW_RX_DESC_STATUS0_DECOMP_CRC_ERROR 0x00002000
#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE 0x000f8000
#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE_S 15
#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x0ff00000
#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 20
#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA 0xf0000000
#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 28
u32 rx_status_1; /* RX status word 1 */
#define AR5K_NEW_RX_DESC_STATUS1_DONE 0x00000001
#define AR5K_NEW_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002
#define AR5K_NEW_RX_DESC_STATUS1_CRC_ERROR 0x00000004
#define AR5K_NEW_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000008
#define AR5K_NEW_RX_DESC_STATUS1_PHY_ERROR 0x00000010
#define AR5K_NEW_RX_DESC_STATUS1_MIC_ERROR 0x00000020
#define AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100
#define AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX 0x0000fe00
#define AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_S 9
#define AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x7fff0000
#define AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 16
#define AR5K_NEW_RX_DESC_STATUS1_KEY_CACHE_MISS 0x80000000
} __packed;
struct ath5k_hw_rx_error {
u32 rx_error_0; /* RX error word 0 */
......@@ -268,7 +265,10 @@ struct ath5k_hw_rx_error {
#define AR5K_DESC_RX_PHY_ERROR_SERVICE 0xc0
#define AR5K_DESC_RX_PHY_ERROR_TRANSMITOVR 0xe0
struct ath5k_hw_2w_tx_desc {
/*
* 5210/5211 hardware 2-word TX control descriptor
*/
struct ath5k_hw_2w_tx_ctl {
u32 tx_control_0; /* TX control word 0 */
#define AR5K_2W_TX_DESC_CTL0_FRAME_LEN 0x00000fff
......@@ -314,9 +314,9 @@ struct ath5k_hw_2w_tx_desc {
#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS 0x10
/*
* 5212 4-word tx control descriptor
* 5212 hardware 4-word TX control descriptor
*/
struct ath5k_hw_4w_tx_desc {
struct ath5k_hw_4w_tx_ctl {
u32 tx_control_0; /* TX control word 0 */
#define AR5K_4W_TX_DESC_CTL0_FRAME_LEN 0x00000fff
......@@ -374,7 +374,7 @@ struct ath5k_hw_4w_tx_desc {
} __packed;
/*
* Common tx status descriptor
* Common TX status descriptor
*/
struct ath5k_hw_tx_status {
u32 tx_status_0; /* TX status word 0 */
......@@ -414,6 +414,34 @@ struct ath5k_hw_tx_status {
} __packed;
/*
* 5210/5211 hardware TX descriptor
*/
struct ath5k_hw_5210_tx_desc {
struct ath5k_hw_2w_tx_ctl tx_ctl;
struct ath5k_hw_tx_status tx_stat;
} __packed;
/*
* 5212 hardware TX descriptor
*/
struct ath5k_hw_5212_tx_desc {
struct ath5k_hw_4w_tx_ctl tx_ctl;
struct ath5k_hw_tx_status tx_stat;
} __packed;
/*
* common hardware RX descriptor
*/
struct ath5k_hw_all_rx_desc {
struct ath5k_hw_rx_ctl rx_ctl;
union {
struct ath5k_hw_rx_status rx_stat;
struct ath5k_hw_rx_error rx_err;
} u;
} __packed;
/*
* AR5K REGISTER ACCESS
*/
......
drivers/net/wireless/ath5k/initvals.c
View file @ ba73d4c8
......@@ -678,8 +678,8 @@ static const struct ath5k_ini ar5212_ini[] = {
{ AR5K_PHY(644), 0x00806333 },
{ AR5K_PHY(645), 0x00106c10 },
{ AR5K_PHY(646), 0x009c4060 },
/*{ AR5K_PHY(647), 0x1483800a },*/ /* Old value */
{ AR5K_PHY(647), 0x1483800a },
/* { AR5K_PHY(648), 0x018830c6 },*/ /* 2413 */
{ AR5K_PHY(648), 0x01831061 },
{ AR5K_PHY(649), 0x00000400 },
/*{ AR5K_PHY(650), 0x000001b5 },*/
......@@ -1081,6 +1081,207 @@ static const struct ath5k_ini_mode rf5413_ini_mode_end[] = {
{ 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0 } },
};
/* Initial mode-specific settings for RF2413/2414 (Written after ar5212_ini) */
/* XXX: No dumps for turbog yet, so turbog is the same with g here with some
* minor tweaking based on dumps from other chips */
static const struct ath5k_ini_mode rf2413_ini_mode_end[] = {
{ AR5K_TXCFG,
/* b g gTurbo */
{ 0x00000015, 0x00000015, 0x00000015 } },
{ AR5K_USEC_5211,
{ 0x04e01395, 0x12e013ab, 0x098813cf } },
{ AR5K_PHY(10),
{ 0x05020000, 0x0a020001, 0x0a020001 } },
{ AR5K_PHY(13),
{ 0x00000e00, 0x00000e00, 0x00000e00 } },
{ AR5K_PHY(14),
{ 0x0000000a, 0x0000000a, 0x0000000a } },
{ AR5K_PHY(18),
{ 0x001a6a64, 0x001a6a64, 0x001a6a64 } },
{ AR5K_PHY(20),
{ 0x0de8b0da, 0x0c98b0da, 0x0c98b0da } },
{ AR5K_PHY_SIG,
{ 0x7ee80d2e, 0x7ec80d2e, 0x7ec80d2e } },
{ AR5K_PHY_AGCCOARSE,
{ 0x3137665e, 0x3139605e, 0x3139605e } },
{ AR5K_PHY(27),
{ 0x050cb081, 0x050cb081, 0x050cb081 } },
{ AR5K_PHY_RX_DELAY,
{ 0x0000044c, 0x00000898, 0x000007d0 } },
{ AR5K_PHY_FRAME_CTL_5211,
{ 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
{ AR5K_PHY_CCKTXCTL,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ AR5K_PHY(642),
{ 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
{ AR5K_PHY_GAIN_2GHZ,
{ 0x0042c140, 0x0042c140, 0x0042c140 } },
{ 0xa21c,
{ 0x1863800a, 0x1883800a, 0x1883800a } },
{ AR5K_DCU_FP,
{ 0x000003e0, 0x000003e0, 0x000003e0 } },
{ 0x8060,
{ 0x0000000f, 0x0000000f, 0x0000000f } },
{ 0x8118,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 0x811c,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 0x8120,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 0x8124,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 0x8128,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 0x812c,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 0x8130,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 0x8134,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 0x8138,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 0x813c,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 0x8140,
{ 0x800000a8, 0x800000a8, 0x800000a8 } },
{ 0x8144,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ AR5K_PHY_AGC,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ AR5K_PHY(11),
{ 0x0000a000, 0x0000a000, 0x0000a000 } },
{ AR5K_PHY(15),
{ 0x00200400, 0x00200400, 0x00200400 } },
{ AR5K_PHY(19),
{ 0x1284233c, 0x1284233c, 0x1284233c } },
{ AR5K_PHY_SCR,
{ 0x0000001f, 0x0000001f, 0x0000001f } },
{ AR5K_PHY_SLMT,
{ 0x00000080, 0x00000080, 0x00000080 } },
{ AR5K_PHY_SCAL,
{ 0x0000000e, 0x0000000e, 0x0000000e } },
{ AR5K_PHY(86),
{ 0x000000ff, 0x000000ff, 0x000000ff } },
{ AR5K_PHY(96),
{ 0x00000000, 0x00000000, 0x00000000 } },
{ AR5K_PHY(97),
{ 0x02800000, 0x02800000, 0x02800000 } },
{ AR5K_PHY(104),
{ 0x00000000, 0x00000000, 0x00000000 } },
{ AR5K_PHY(120),
{ 0x00000000, 0x00000000, 0x00000000 } },
{ AR5K_PHY(121),
{ 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa } },
{ AR5K_PHY(122),
{ 0x3c466478, 0x3c466478, 0x3c466478 } },
{ AR5K_PHY(123),
{ 0x000000aa, 0x000000aa, 0x000000aa } },
{ AR5K_PHY_SCLOCK,
{ 0x0000000c, 0x0000000c, 0x0000000c } },
{ AR5K_PHY_SDELAY,
{ 0x000000ff, 0x000000ff, 0x000000ff } },
{ AR5K_PHY_SPENDING,
{ 0x00000014, 0x00000014, 0x00000014 } },
{ 0xa228,
{ 0x000009b5, 0x000009b5, 0x000009b5 } },
{ 0xa23c,
{ 0x93c889af, 0x93c889af, 0x93c889af } },
{ 0xa24c,
{ 0x00000001, 0x00000001, 0x00000001 } },
{ 0xa250,
{ 0x0000a000, 0x0000a000, 0x0000a000 } },
{ 0xa254,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 0xa258,
{ 0x0cc75380, 0x0cc75380, 0x0cc75380 } },
{ 0xa25c,
{ 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01 } },
{ 0xa260,
{ 0x5f690f01, 0x5f690f01, 0x5f690f01 } },
{ 0xa264,
{ 0x00418a11, 0x00418a11, 0x00418a11 } },
{ 0xa268,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 0xa26c,
{ 0x0c30c16a, 0x0c30c16a, 0x0c30c16a } },
{ 0xa270,
{ 0x00820820, 0x00820820, 0x00820820 } },
{ 0xa274,
{ 0x001b7caa, 0x001b7caa, 0x001b7caa } },
{ 0xa278,
{ 0x1ce739ce, 0x1ce739ce, 0x1ce739ce } },
{ 0xa27c,
{ 0x051701ce, 0x051701ce, 0x051701ce } },
{ 0xa300,
{ 0x18010000, 0x18010000, 0x18010000 } },
{ 0xa304,
{ 0x30032602, 0x30032602, 0x30032602 } },
{ 0xa308,
{ 0x48073e06, 0x48073e06, 0x48073e06 } },
{ 0xa30c,
{ 0x560b4c0a, 0x560b4c0a, 0x560b4c0a } },
{ 0xa310,
{ 0x641a600f, 0x641a600f, 0x641a600f } },
{ 0xa314,
{ 0x784f6e1b, 0x784f6e1b, 0x784f6e1b } },
{ 0xa318,
{ 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } },
{ 0xa31c,
{ 0x8ecf865b, 0x8ecf865b, 0x8ecf865b } },
{ 0xa320,
{ 0x9d4f970f, 0x9d4f970f, 0x9d4f970f } },
{ 0xa324,
{ 0xa5cfa18f, 0xa5cfa18f, 0xa5cfa18f } },
{ 0xa328,
{ 0xb55faf1f, 0xb55faf1f, 0xb55faf1f } },
{ 0xa32c,
{ 0xbddfb99f, 0xbddfb99f, 0xbddfb99f } },
{ 0xa330,
{ 0xcd7fc73f, 0xcd7fc73f, 0xcd7fc73f } },
{ 0xa334,
{ 0xd5ffd1bf, 0xd5ffd1bf, 0xd5ffd1bf } },
{ 0xa338,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 0xa33c,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 0xa340,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 0xa344,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 0xa348,
{ 0x3fffffff, 0x3fffffff, 0x3fffffff } },
{ 0xa34c,
{ 0x3fffffff, 0x3fffffff, 0x3fffffff } },
{ 0xa350,
{ 0x3fffffff, 0x3fffffff, 0x3fffffff } },
{ 0xa354,
{ 0x0003ffff, 0x0003ffff, 0x0003ffff } },
{ 0xa358,
{ 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f } },
{ 0xa35c,
{ 0x066c420f, 0x066c420f, 0x066c420f } },
{ 0xa360,
{ 0x0f282207, 0x0f282207, 0x0f282207 } },
{ 0xa364,
{ 0x17601685, 0x17601685, 0x17601685 } },
{ 0xa368,
{ 0x1f801104, 0x1f801104, 0x1f801104 } },
{ 0xa36c,
{ 0x37a00c03, 0x37a00c03, 0x37a00c03 } },
{ 0xa370,
{ 0x3fc40883, 0x3fc40883, 0x3fc40883 } },
{ 0xa374,
{ 0x57c00803, 0x57c00803, 0x57c00803 } },
{ 0xa378,
{ 0x5fd80682, 0x5fd80682, 0x5fd80682 } },
{ 0xa37c,
{ 0x7fe00482, 0x7fe00482, 0x7fe00482 } },
{ 0xa380,
{ 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba } },
{ 0xa384,
{ 0xf3307ff0, 0xf3307ff0, 0xf3307ff0 } },
};
/*
* Initial BaseBand Gain settings for RF5111/5112 (AR5210 comes with
* RF5110 only so initial BB Gain settings are included in AR5K_AR5210_INI)
......@@ -1290,29 +1491,57 @@ int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
/* Second set of mode-specific settings */
if (ah->ah_radio == AR5K_RF5111){
ath5k_hw_ini_mode_registers(ah,
ARRAY_SIZE(ar5212_rf5111_ini_mode_end),
ar5212_rf5111_ini_mode_end, mode);
/* Baseband gain table */
ath5k_hw_ini_registers(ah,
ARRAY_SIZE(rf5111_ini_bbgain),
rf5111_ini_bbgain, change_channel);
} else if (ah->ah_radio == AR5K_RF5112){
ath5k_hw_ini_mode_registers(ah,
ARRAY_SIZE(ar5212_rf5112_ini_mode_end),
ar5212_rf5112_ini_mode_end, mode);
/* Baseband gain table */
ath5k_hw_ini_registers(ah,
ARRAY_SIZE(rf5112_ini_bbgain),
rf5112_ini_bbgain, change_channel);
} else if (ah->ah_radio == AR5K_RF5413){
ath5k_hw_ini_mode_registers(ah,
ARRAY_SIZE(rf5413_ini_mode_end),
rf5413_ini_mode_end, mode);
ath5k_hw_ini_registers(ah,
ARRAY_SIZE(rf5112_ini_bbgain),
rf5112_ini_bbgain, change_channel);
} else if (ah->ah_radio == AR5K_RF2413) {
if (mode < 2) {
ATH5K_ERR(ah->ah_sc,
"unsupported channel mode: %d\n", mode);
return -EINVAL;
}
mode = mode - 2;
/* Override a setting from ar5212_ini */
ath5k_hw_reg_write(ah, 0x018830c6, AR5K_PHY(648));
ath5k_hw_ini_mode_registers(ah,
ARRAY_SIZE(rf2413_ini_mode_end),
rf2413_ini_mode_end, mode);
/* Baseband gain table */
ath5k_hw_ini_registers(ah,
ARRAY_SIZE(rf5112_ini_bbgain),
rf5112_ini_bbgain, change_channel);
}
/* For AR5211 */
} else if (ah->ah_version == AR5K_AR5211) {
......
drivers/net/wireless/ath5k/phy.c
View file @ ba73d4c8
......@@ -666,6 +666,75 @@ static const struct ath5k_ini_rf rfregs_5413[] = {
{ 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
};
/* RF2413/2414 mode-specific init registers */
static const struct ath5k_ini_rf rfregs_2413[] = {
{ 1, AR5K_RF_BUFFER_CONTROL_4,
{ 0x00000020, 0x00000020, 0x00000020 } },
{ 2, AR5K_RF_BUFFER_CONTROL_3,
{ 0x02001408, 0x02001408, 0x02001408 } },
{ 3, AR5K_RF_BUFFER_CONTROL_6,
{ 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
{ 6, AR5K_RF_BUFFER,
{ 0xf0000000, 0xf0000000, 0xf0000000 } },
{ 6, AR5K_RF_BUFFER,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 6, AR5K_RF_BUFFER,
{ 0x03000000, 0x03000000, 0x03000000 } },
{ 6, AR5K_RF_BUFFER,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 6, AR5K_RF_BUFFER,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 6, AR5K_RF_BUFFER,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 6, AR5K_RF_BUFFER,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 6, AR5K_RF_BUFFER,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 6, AR5K_RF_BUFFER,
{ 0x40400000, 0x40400000, 0x40400000 } },
{ 6, AR5K_RF_BUFFER,
{ 0x65050000, 0x65050000, 0x65050000 } },
{ 6, AR5K_RF_BUFFER,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 6, AR5K_RF_BUFFER,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 6, AR5K_RF_BUFFER,
{ 0x00420000, 0x00420000, 0x00420000 } },
{ 6, AR5K_RF_BUFFER,
{ 0x00b50000, 0x00b50000, 0x00b50000 } },
{ 6, AR5K_RF_BUFFER,
{ 0x00030000, 0x00030000, 0x00030000 } },
{ 6, AR5K_RF_BUFFER,
{ 0x00f70000, 0x00f70000, 0x00f70000 } },
{ 6, AR5K_RF_BUFFER,
{ 0x009d0000, 0x009d0000, 0x009d0000 } },
{ 6, AR5K_RF_BUFFER,
{ 0x00220000, 0x00220000, 0x00220000 } },
{ 6, AR5K_RF_BUFFER,
{ 0x04220000, 0x04220000, 0x04220000 } },
{ 6, AR5K_RF_BUFFER,
{ 0x00230018, 0x00230018, 0x00230018 } },
{ 6, AR5K_RF_BUFFER,
{ 0x00280050, 0x00280050, 0x00280050 } },
{ 6, AR5K_RF_BUFFER,
{ 0x005000c3, 0x005000c3, 0x005000c3 } },
{ 6, AR5K_RF_BUFFER,
{ 0x0004007f, 0x0004007f, 0x0004007f } },
{ 6, AR5K_RF_BUFFER,
{ 0x00000458, 0x00000458, 0x00000458 } },
{ 6, AR5K_RF_BUFFER,
{ 0x00000000, 0x00000000, 0x00000000 } },
{ 6, AR5K_RF_BUFFER,
{ 0x0000c000, 0x0000c000, 0x0000c000 } },
{ 6, AR5K_RF_BUFFER_CONTROL_5,
{ 0x00400230, 0x00400230, 0x00400230 } },
{ 7, AR5K_RF_BUFFER,
{ 0x00006400, 0x00006400, 0x00006400 } },
{ 7, AR5K_RF_BUFFER,
{ 0x00000800, 0x00000800, 0x00000800 } },
{ 7, AR5K_RF_BUFFER_CONTROL_2,
{ 0x0000000e, 0x0000000e, 0x0000000e } },
};
/* Initial RF Gain settings for RF5112 */
static const struct ath5k_ini_rfgain rfgain_5112[] = {
......@@ -805,6 +874,74 @@ static const struct ath5k_ini_rfgain rfgain_5413[] = {
{ AR5K_RF_GAIN(63), { 0x000000f9, 0x000000f9 } },
};
/* Initial RF Gain settings for RF2413 */
static const struct ath5k_ini_rfgain rfgain_2413[] = {
{ AR5K_RF_GAIN(0), { 0x00000000 } },
{ AR5K_RF_GAIN(1), { 0x00000040 } },
{ AR5K_RF_GAIN(2), { 0x00000080 } },
{ AR5K_RF_GAIN(3), { 0x00000181 } },
{ AR5K_RF_GAIN(4), { 0x000001c1 } },
{ AR5K_RF_GAIN(5), { 0x00000001 } },
{ AR5K_RF_GAIN(6), { 0x00000041 } },
{ AR5K_RF_GAIN(7), { 0x00000081 } },
{ AR5K_RF_GAIN(8), { 0x00000168 } },
{ AR5K_RF_GAIN(9), { 0x000001a8 } },
{ AR5K_RF_GAIN(10), { 0x000001e8 } },
{ AR5K_RF_GAIN(11), { 0x00000028 } },
{ AR5K_RF_GAIN(12), { 0x00000068 } },
{ AR5K_RF_GAIN(13), { 0x00000189 } },
{ AR5K_RF_GAIN(14), { 0x000001c9 } },
{ AR5K_RF_GAIN(15), { 0x00000009 } },
{ AR5K_RF_GAIN(16), { 0x00000049 } },
{ AR5K_RF_GAIN(17), { 0x00000089 } },
{ AR5K_RF_GAIN(18), { 0x00000190 } },
{ AR5K_RF_GAIN(19), { 0x000001d0 } },
{ AR5K_RF_GAIN(20), { 0x00000010 } },
{ AR5K_RF_GAIN(21), { 0x00000050 } },
{ AR5K_RF_GAIN(22), { 0x00000090 } },
{ AR5K_RF_GAIN(23), { 0x00000191 } },
{ AR5K_RF_GAIN(24), { 0x000001d1 } },
{ AR5K_RF_GAIN(25), { 0x00000011 } },
{ AR5K_RF_GAIN(26), { 0x00000051 } },
{ AR5K_RF_GAIN(27), { 0x00000091 } },
{ AR5K_RF_GAIN(28), { 0x00000178 } },
{ AR5K_RF_GAIN(29), { 0x000001b8 } },
{ AR5K_RF_GAIN(30), { 0x000001f8 } },
{ AR5K_RF_GAIN(31), { 0x00000038 } },
{ AR5K_RF_GAIN(32), { 0x00000078 } },
{ AR5K_RF_GAIN(33), { 0x00000199 } },
{ AR5K_RF_GAIN(34), { 0x000001d9 } },
{ AR5K_RF_GAIN(35), { 0x00000019 } },
{ AR5K_RF_GAIN(36), { 0x00000059 } },
{ AR5K_RF_GAIN(37), { 0x00000099 } },
{ AR5K_RF_GAIN(38), { 0x000000d9 } },
{ AR5K_RF_GAIN(39), { 0x000000f9 } },
{ AR5K_RF_GAIN(40), { 0x000000f9 } },
{ AR5K_RF_GAIN(41), { 0x000000f9 } },
{ AR5K_RF_GAIN(42), { 0x000000f9 } },
{ AR5K_RF_GAIN(43), { 0x000000f9 } },
{ AR5K_RF_GAIN(44), { 0x000000f9 } },
{ AR5K_RF_GAIN(45), { 0x000000f9 } },
{ AR5K_RF_GAIN(46), { 0x000000f9 } },
{ AR5K_RF_GAIN(47), { 0x000000f9 } },
{ AR5K_RF_GAIN(48), { 0x000000f9 } },
{ AR5K_RF_GAIN(49), { 0x000000f9 } },
{ AR5K_RF_GAIN(50), { 0x000000f9 } },
{ AR5K_RF_GAIN(51), { 0x000000f9 } },
{ AR5K_RF_GAIN(52), { 0x000000f9 } },
{ AR5K_RF_GAIN(53), { 0x000000f9 } },
{ AR5K_RF_GAIN(54), { 0x000000f9 } },
{ AR5K_RF_GAIN(55), { 0x000000f9 } },
{ AR5K_RF_GAIN(56), { 0x000000f9 } },
{ AR5K_RF_GAIN(57), { 0x000000f9 } },
{ AR5K_RF_GAIN(58), { 0x000000f9 } },
{ AR5K_RF_GAIN(59), { 0x000000f9 } },
{ AR5K_RF_GAIN(60), { 0x000000f9 } },
{ AR5K_RF_GAIN(61), { 0x000000f9 } },
{ AR5K_RF_GAIN(62), { 0x000000f9 } },
{ AR5K_RF_GAIN(63), { 0x000000f9 } },
};
static const struct ath5k_gain_opt rfgain_opt_5112 = {
1,
8,
......@@ -955,7 +1092,6 @@ static s32 ath5k_hw_rfregs_gain_adjust(struct ath5k_hw *ah)
go = &rfgain_opt_5111;
break;
case AR5K_RF5112:
case AR5K_RF5413: /* ??? */
go = &rfgain_opt_5112;
break;
default:
......@@ -1226,8 +1362,21 @@ static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah,
rf = ah->ah_rf_banks;
rf_ini = rfregs_5413;
rf_size = ARRAY_SIZE(rfregs_5413);
if (ah->ah_radio == AR5K_RF5413) {
rf_ini = rfregs_5413;
rf_size = ARRAY_SIZE(rfregs_5413);
} else if (ah->ah_radio == AR5K_RF2413) {
rf_ini = rfregs_2413;
rf_size = ARRAY_SIZE(rfregs_2413);
if (mode < 2) {
ATH5K_ERR(ah->ah_sc,
"invalid channel mode: %i\n", mode);
return -EINVAL;
}
mode = mode - 2;
} else {
return -EINVAL;
}
/* Copy values to modify them */
for (i = 0; i < rf_size; i++) {
......@@ -1286,6 +1435,10 @@ int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel *channel,
ah->ah_rf_banks_size = sizeof(rfregs_5413);
func = ath5k_hw_rf5413_rfregs;
break;
case AR5K_RF2413:
ah->ah_rf_banks_size = sizeof(rfregs_2413);
func = ath5k_hw_rf5413_rfregs;
break;
default:
return -EINVAL;
}
......@@ -1324,6 +1477,11 @@ int ath5k_hw_rfgain(struct ath5k_hw *ah, unsigned int freq)
ath5k_rfg = rfgain_5413;
size = ARRAY_SIZE(rfgain_5413);
break;
case AR5K_RF2413:
ath5k_rfg = rfgain_2413;
size = ARRAY_SIZE(rfgain_2413);
freq = 0; /* only 2Ghz */
break;
default:
return -EINVAL;
}
......@@ -1398,7 +1556,6 @@ int ath5k_hw_set_rfgain_opt(struct ath5k_hw *ah)
ah->ah_gain.g_active = 1;
break;
case AR5K_RF5112:
case AR5K_RF5413: /* ??? */
ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
ah->ah_gain.g_step =
&rfgain_opt_5112.go_step[ah->ah_gain.g_step_idx];
......@@ -2019,6 +2176,15 @@ ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
return -EINVAL;
}
/*
* RF2413 for some reason can't
* transmit anything if we call
* this funtion, so we skip it
* until we fix txpower.
*/
if (ah->ah_radio == AR5K_RF2413)
return 0;
/* Reset TX power values */
memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
ah->ah_txpower.txp_tpc = tpc;
......
drivers/net/wireless/ath5k/reg.h
View file @ ba73d4c8
......@@ -1923,7 +1923,9 @@ after DFS is enabled */
#define AR5K_PHY_SDELAY_32MHZ 0x000000ff
#define AR5K_PHY_SPENDING 0x99f8
#define AR5K_PHY_SPENDING_RF5111 0x00000018
#define AR5K_PHY_SPENDING_RF5112 0x00000014
#define AR5K_PHY_SPENDING_RF5112 0x00000014 /* <- i 've only seen this on 2425 dumps ! */
#define AR5K_PHY_SPENDING_RF5112A 0x0000000e /* but since i only have 5112A-based chips */
#define AR5K_PHY_SPENDING_RF5424 0x00000012 /* to test it might be also for old 5112. */
/*
* Misc PHY/radio registers [5110 - 5111]
......
drivers/net/wireless/b43/b43.h
View file @ ba73d4c8
......@@ -99,6 +99,8 @@
#define B43_MMIO_TSF_2 0x636 /* core rev < 3 only */
#define B43_MMIO_TSF_3 0x638 /* core rev < 3 only */
#define B43_MMIO_RNG 0x65A
#define B43_MMIO_IFSCTL 0x688 /* Interframe space control */
#define B43_MMIO_IFSCTL_USE_EDCF 0x0004
#define B43_MMIO_POWERUP_DELAY 0x6A8
/* SPROM boardflags_lo values */
......@@ -587,15 +589,13 @@ struct b43_phy {
/* Data structures for DMA transmission, per 80211 core. */
struct b43_dma {
struct b43_dmaring *tx_ring0;
struct b43_dmaring *tx_ring1;
struct b43_dmaring *tx_ring2;
struct b43_dmaring *tx_ring3;
struct b43_dmaring *tx_ring4;
struct b43_dmaring *tx_ring5;
struct b43_dmaring *rx_ring0;
struct b43_dmaring *rx_ring3; /* only available on core.rev < 5 */
struct b43_dmaring *tx_ring_AC_BK; /* Background */
struct b43_dmaring *tx_ring_AC_BE; /* Best Effort */
struct b43_dmaring *tx_ring_AC_VI; /* Video */
struct b43_dmaring *tx_ring_AC_VO; /* Voice */
struct b43_dmaring *tx_ring_mcast; /* Multicast */
struct b43_dmaring *rx_ring;
};
/* Context information for a noise calculation (Link Quality). */
......@@ -621,6 +621,35 @@ struct b43_key {
u8 algorithm;
};
/* SHM offsets to the QOS data structures for the 4 different queues. */
#define B43_QOS_PARAMS(queue) (B43_SHM_SH_EDCFQ + \
(B43_NR_QOSPARAMS * sizeof(u16) * (queue)))
#define B43_QOS_BACKGROUND B43_QOS_PARAMS(0)
#define B43_QOS_BESTEFFORT B43_QOS_PARAMS(1)
#define B43_QOS_VIDEO B43_QOS_PARAMS(2)
#define B43_QOS_VOICE B43_QOS_PARAMS(3)
/* QOS parameter hardware data structure offsets. */
#define B43_NR_QOSPARAMS 22
enum {
B43_QOSPARAM_TXOP = 0,
B43_QOSPARAM_CWMIN,
B43_QOSPARAM_CWMAX,
B43_QOSPARAM_CWCUR,
B43_QOSPARAM_AIFS,
B43_QOSPARAM_BSLOTS,
B43_QOSPARAM_REGGAP,
B43_QOSPARAM_STATUS,
};
/* QOS parameters for a queue. */
struct b43_qos_params {
/* The QOS parameters */
struct ieee80211_tx_queue_params p;
/* Does this need to get uploaded to hardware? */
bool need_hw_update;
};
struct b43_wldev;
/* Data structure for the WLAN parts (802.11 cores) of the b43 chip. */
......@@ -673,6 +702,12 @@ struct b43_wl {
struct sk_buff *current_beacon;
bool beacon0_uploaded;
bool beacon1_uploaded;
/* The current QOS parameters for the 4 queues.
* This is protected by the irq_lock. */
struct b43_qos_params qos_params[4];
/* Workqueue for updating QOS parameters in hardware. */
struct work_struct qos_update_work;
};
/* In-memory representation of a cached microcode file. */
......
drivers/net/wireless/b43/dma.c
View file @ ba73d4c8
This diff is collapsed.
drivers/net/wireless/b43/dma.h
View file @ ba73d4c8
......@@ -245,6 +245,9 @@ struct b43_dmaring {
enum b43_dmatype type;
/* Boolean. Is this ring stopped at ieee80211 level? */
bool stopped;
/* The QOS priority assigned to this ring. Only used for TX rings.
* This is the mac80211 "queue" value. */
u8 queue_prio;
/* Lock, only used for TX. */
spinlock_t lock;
struct b43_wldev *dev;
......@@ -253,7 +256,13 @@ struct b43_dmaring {
int max_used_slots;
/* Last time we injected a ring overflow. */
unsigned long last_injected_overflow;
#endif /* CONFIG_B43_DEBUG */
/* Statistics: Number of successfully transmitted packets */
u64 nr_succeed_tx_packets;
/* Statistics: Number of failed TX packets */
u64 nr_failed_tx_packets;
/* Statistics: Total number of TX plus all retries. */
u64 nr_total_packet_tries;
#endif /* CONFIG_B43_DEBUG */
};
static inline u32 b43_dma_read(struct b43_dmaring *ring, u16 offset)
......
drivers/net/wireless/b43/main.c
View file @ ba73d4c8
......@@ -78,6 +78,11 @@ static int modparam_nohwcrypt;
module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
int b43_modparam_qos = 1;
module_param_named(qos, b43_modparam_qos, int, 0444);
MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
static const struct ssb_device_id b43_ssb_tbl[] = {
SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
......@@ -1589,11 +1594,10 @@ static void b43_interrupt_tasklet(struct b43_wldev *dev)
/* Check the DMA reason registers for received data. */
if (dma_reason[0] & B43_DMAIRQ_RX_DONE)
b43_dma_rx(dev->dma.rx_ring0);
if (dma_reason[3] & B43_DMAIRQ_RX_DONE)
b43_dma_rx(dev->dma.rx_ring3);
b43_dma_rx(dev->dma.rx_ring);
B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
......@@ -2708,10 +2712,178 @@ static int b43_op_tx(struct ieee80211_hw *hw,
return NETDEV_TX_OK;
}
/* Locking: wl->irq_lock */
static void b43_qos_params_upload(struct b43_wldev *dev,
const struct ieee80211_tx_queue_params *p,
u16 shm_offset)
{
u16 params[B43_NR_QOSPARAMS];
int cw_min, cw_max, aifs, bslots, tmp;
unsigned int i;
const u16 aCWmin = 0x0001;
const u16 aCWmax = 0x03FF;
/* Calculate the default values for the parameters, if needed. */
switch (shm_offset) {
case B43_QOS_VOICE:
aifs = (p->aifs == -1) ? 2 : p->aifs;
cw_min = (p->cw_min == 0) ? ((aCWmin + 1) / 4 - 1) : p->cw_min;
cw_max = (p->cw_max == 0) ? ((aCWmin + 1) / 2 - 1) : p->cw_max;
break;
case B43_QOS_VIDEO:
aifs = (p->aifs == -1) ? 2 : p->aifs;
cw_min = (p->cw_min == 0) ? ((aCWmin + 1) / 2 - 1) : p->cw_min;
cw_max = (p->cw_max == 0) ? aCWmin : p->cw_max;
break;
case B43_QOS_BESTEFFORT:
aifs = (p->aifs == -1) ? 3 : p->aifs;
cw_min = (p->cw_min == 0) ? aCWmin : p->cw_min;
cw_max = (p->cw_max == 0) ? aCWmax : p->cw_max;
break;
case B43_QOS_BACKGROUND:
aifs = (p->aifs == -1) ? 7 : p->aifs;
cw_min = (p->cw_min == 0) ? aCWmin : p->cw_min;
cw_max = (p->cw_max == 0) ? aCWmax : p->cw_max;
break;
default:
B43_WARN_ON(1);
return;
}
if (cw_min <= 0)
cw_min = aCWmin;
if (cw_max <= 0)
cw_max = aCWmin;
bslots = b43_read16(dev, B43_MMIO_RNG) % cw_min;
memset(&params, 0, sizeof(params));
params[B43_QOSPARAM_TXOP] = p->txop * 32;
params[B43_QOSPARAM_CWMIN] = cw_min;
params[B43_QOSPARAM_CWMAX] = cw_max;
params[B43_QOSPARAM_CWCUR] = cw_min;
params[B43_QOSPARAM_AIFS] = aifs;
params[B43_QOSPARAM_BSLOTS] = bslots;
params[B43_QOSPARAM_REGGAP] = bslots + aifs;
for (i = 0; i < ARRAY_SIZE(params); i++) {
if (i == B43_QOSPARAM_STATUS) {
tmp = b43_shm_read16(dev, B43_SHM_SHARED,
shm_offset + (i * 2));
/* Mark the parameters as updated. */
tmp |= 0x100;
b43_shm_write16(dev, B43_SHM_SHARED,
shm_offset + (i * 2),
tmp);
} else {
b43_shm_write16(dev, B43_SHM_SHARED,
shm_offset + (i * 2),
params[i]);
}
}
}
/* Update the QOS parameters in hardware. */
static void b43_qos_update(struct b43_wldev *dev)
{
struct b43_wl *wl = dev->wl;
struct b43_qos_params *params;
unsigned long flags;
unsigned int i;
/* Mapping of mac80211 queues to b43 SHM offsets. */
static const u16 qos_shm_offsets[] = {
[0] = B43_QOS_VOICE,
[1] = B43_QOS_VIDEO,
[2] = B43_QOS_BESTEFFORT,
[3] = B43_QOS_BACKGROUND,
};
BUILD_BUG_ON(ARRAY_SIZE(qos_shm_offsets) != ARRAY_SIZE(wl->qos_params));
b43_mac_suspend(dev);
spin_lock_irqsave(&wl->irq_lock, flags);
for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
params = &(wl->qos_params[i]);
if (params->need_hw_update) {
b43_qos_params_upload(dev, &(params->p),
qos_shm_offsets[i]);
params->need_hw_update = 0;
}
}
spin_unlock_irqrestore(&wl->irq_lock, flags);
b43_mac_enable(dev);
}
static void b43_qos_clear(struct b43_wl *wl)
{
struct b43_qos_params *params;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
params = &(wl->qos_params[i]);
memset(&(params->p), 0, sizeof(params->p));
params->p.aifs = -1;
params->need_hw_update = 1;
}
}
/* Initialize the core's QOS capabilities */
static void b43_qos_init(struct b43_wldev *dev)
{
struct b43_wl *wl = dev->wl;
unsigned int i;
/* Upload the current QOS parameters. */
for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++)
wl->qos_params[i].need_hw_update = 1;
b43_qos_update(dev);
/* Enable QOS support. */
b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
b43_write16(dev, B43_MMIO_IFSCTL,
b43_read16(dev, B43_MMIO_IFSCTL)
| B43_MMIO_IFSCTL_USE_EDCF);
}
static void b43_qos_update_work(struct work_struct *work)
{
struct b43_wl *wl = container_of(work, struct b43_wl, qos_update_work);
struct b43_wldev *dev;
mutex_lock(&wl->mutex);
dev = wl->current_dev;
if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED)))
b43_qos_update(dev);
mutex_unlock(&wl->mutex);
}
static int b43_op_conf_tx(struct ieee80211_hw *hw,
int queue,
int _queue,
const struct ieee80211_tx_queue_params *params)
{
struct b43_wl *wl = hw_to_b43_wl(hw);
unsigned long flags;
unsigned int queue = (unsigned int)_queue;
struct b43_qos_params *p;
if (queue >= ARRAY_SIZE(wl->qos_params)) {
/* Queue not available or don't support setting
* params on this queue. Return success to not
* confuse mac80211. */
return 0;
}
spin_lock_irqsave(&wl->irq_lock, flags);
p = &(wl->qos_params[queue]);
memcpy(&(p->p), params, sizeof(p->p));
p->need_hw_update = 1;
spin_unlock_irqrestore(&wl->irq_lock, flags);
queue_work(hw->workqueue, &wl->qos_update_work);
return 0;
}
......@@ -3732,6 +3904,7 @@ static int b43_op_start(struct ieee80211_hw *hw)
memset(wl->mac_addr, 0, ETH_ALEN);
wl->filter_flags = 0;
wl->radiotap_enabled = 0;
b43_qos_clear(wl);
/* First register RFkill.
* LEDs that are registered later depend on it. */
......@@ -3773,6 +3946,7 @@ static void b43_op_stop(struct ieee80211_hw *hw)
struct b43_wldev *dev = wl->current_dev;
b43_rfkill_exit(dev);
cancel_work_sync(&(wl->qos_update_work));
mutex_lock(&wl->mutex);
if (b43_status(dev) >= B43_STAT_STARTED)
......@@ -3835,6 +4009,16 @@ static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw,
return 0;
}
static void b43_op_sta_notify(struct ieee80211_hw *hw,
struct ieee80211_vif *vif,
enum sta_notify_cmd notify_cmd,
const u8 *addr)
{
struct b43_wl *wl = hw_to_b43_wl(hw);
B43_WARN_ON(!vif || wl->vif != vif);
}
static const struct ieee80211_ops b43_hw_ops = {
.tx = b43_op_tx,
.conf_tx = b43_op_conf_tx,
......@@ -3851,6 +4035,7 @@ static const struct ieee80211_ops b43_hw_ops = {
.set_retry_limit = b43_op_set_retry_limit,
.set_tim = b43_op_beacon_set_tim,
.beacon_update = b43_op_ibss_beacon_update,
.sta_notify = b43_op_sta_notify,
};
/* Hard-reset the chip. Do not call this directly.
......@@ -4122,7 +4307,7 @@ static int b43_wireless_init(struct ssb_device *dev)
hw->max_signal = 100;
hw->max_rssi = -110;
hw->max_noise = -110;
hw->queues = 1; /* FIXME: hardware has more queues */
hw->queues = b43_modparam_qos ? 4 : 1;
SET_IEEE80211_DEV(hw, dev->dev);
if (is_valid_ether_addr(sprom->et1mac))
SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
......@@ -4138,6 +4323,7 @@ static int b43_wireless_init(struct ssb_device *dev)
spin_lock_init(&wl->shm_lock);
mutex_init(&wl->mutex);
INIT_LIST_HEAD(&wl->devlist);
INIT_WORK(&wl->qos_update_work, b43_qos_update_work);
ssb_set_devtypedata(dev, wl);
b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
......
drivers/net/wireless/b43/main.h
View file @ ba73d4c8
......@@ -38,6 +38,10 @@
/* Magic helper macro to pad structures. Ignore those above. It's magic. */
#define PAD_BYTES(nr_bytes) P4D_BYTES( __LINE__ , (nr_bytes))
extern int b43_modparam_qos;
/* Lightweight function to convert a frequency (in Mhz) to a channel number. */
static inline u8 b43_freq_to_channel_5ghz(int freq)
{
......
drivers/net/wireless/b43/xmit.c
View file @ ba73d4c8
......@@ -705,30 +705,3 @@ void b43_tx_resume(struct b43_wldev *dev)
{
b43_dma_tx_resume(dev);
}
#if 0
static void upload_qos_parms(struct b43_wldev *dev,
const u16 * parms, u16 offset)
{
int i;
for (i = 0; i < B43_NR_QOSPARMS; i++) {
b43_shm_write16(dev, B43_SHM_SHARED,
offset + (i * 2), parms[i]);
}
}
#endif
/* Initialize the QoS parameters */
void b43_qos_init(struct b43_wldev *dev)
{
/* FIXME: This function must probably be called from the mac80211
* config callback. */
return;
b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
//FIXME kill magic
b43_write16(dev, 0x688, b43_read16(dev, 0x688) | 0x4);
/*TODO: We might need some stack support here to get the values. */
}
drivers/net/wireless/b43/xmit.h
View file @ ba73d4c8
......@@ -302,18 +302,6 @@ void b43_handle_hwtxstatus(struct b43_wldev *dev,
void b43_tx_suspend(struct b43_wldev *dev);
void b43_tx_resume(struct b43_wldev *dev);
#define B43_NR_QOSPARMS 22
enum {
B43_QOSPARM_TXOP = 0,
B43_QOSPARM_CWMIN,
B43_QOSPARM_CWMAX,
B43_QOSPARM_CWCUR,
B43_QOSPARM_AIFS,
B43_QOSPARM_BSLOTS,
B43_QOSPARM_REGGAP,
B43_QOSPARM_STATUS,
};
void b43_qos_init(struct b43_wldev *dev);
/* Helper functions for converting the key-table index from "firmware-format"
* to "raw-format" and back. The firmware API changed for this at some revision.
......
drivers/net/wireless/iwlwifi/Kconfig
View file @ ba73d4c8
config IWLCORE
tristate "Intel Wireless Wifi Core"
depends on PCI && MAC80211 && WLAN_80211 && EXPERIMENTAL
config IWL4965
tristate "Intel Wireless WiFi 4965AGN"
depends on PCI && MAC80211 && WLAN_80211 && EXPERIMENTAL
select FW_LOADER
select IWLCORE
---help---
Select to build the driver supporting the:
......
drivers/net/wireless/iwlwifi/Makefile
View file @ ba73d4c8
obj-$(CONFIG_IWLCORE) += iwlcore.o
iwlcore-objs = iwl-core.o
obj-$(CONFIG_IWL3945) += iwl3945.o
iwl3945-objs = iwl3945-base.o iwl-3945.o iwl-3945-rs.o
......
drivers/net/wireless/iwlwifi/iwl-3945-commands.h
View file @ ba73d4c8
......@@ -666,26 +666,26 @@ struct iwl3945_rx_frame_hdr {
u8 payload[0];
} __attribute__ ((packed));
#define RX_RES_STATUS_NO_CRC32_ERROR __constant_cpu_to_le32(1 << 0)
#define RX_RES_STATUS_NO_RXE_OVERFLOW __constant_cpu_to_le32(1 << 1)
#define RX_RES_PHY_FLAGS_BAND_24_MSK __constant_cpu_to_le16(1 << 0)
#define RX_RES_PHY_FLAGS_MOD_CCK_MSK __constant_cpu_to_le16(1 << 1)
#define RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK __constant_cpu_to_le16(1 << 2)
#define RX_RES_PHY_FLAGS_NARROW_BAND_MSK __constant_cpu_to_le16(1 << 3)
#define RX_RES_PHY_FLAGS_ANTENNA_MSK __constant_cpu_to_le16(0xf0)
#define RX_RES_STATUS_SEC_TYPE_MSK (0x7 << 8)
#define RX_RES_STATUS_SEC_TYPE_NONE (0x0 << 8)
#define RX_RES_STATUS_SEC_TYPE_WEP (0x1 << 8)
#define RX_RES_STATUS_SEC_TYPE_CCMP (0x2 << 8)
#define RX_RES_STATUS_SEC_TYPE_TKIP (0x3 << 8)
#define RX_RES_STATUS_DECRYPT_TYPE_MSK (0x3 << 11)
#define RX_RES_STATUS_NOT_DECRYPT (0x0 << 11)
#define RX_RES_STATUS_DECRYPT_OK (0x3 << 11)
#define RX_RES_STATUS_BAD_ICV_MIC (0x1 << 11)
#define RX_RES_STATUS_BAD_KEY_TTAK (0x2 << 11)
#define RX_RES_STATUS_NO_CRC32_ERROR __constant_cpu_to_le32(1 << 0)
#define RX_RES_STATUS_NO_RXE_OVERFLOW __constant_cpu_to_le32(1 << 1)
#define RX_RES_PHY_FLAGS_BAND_24_MSK __constant_cpu_to_le16(1 << 0)
#define RX_RES_PHY_FLAGS_MOD_CCK_MSK __constant_cpu_to_le16(1 << 1)
#define RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK __constant_cpu_to_le16(1 << 2)
#define RX_RES_PHY_FLAGS_NARROW_BAND_MSK __constant_cpu_to_le16(1 << 3)
#define RX_RES_PHY_FLAGS_ANTENNA_MSK __constant_cpu_to_le16(0xf0)
#define RX_RES_STATUS_SEC_TYPE_MSK (0x7 << 8)
#define RX_RES_STATUS_SEC_TYPE_NONE (0x0 << 8)
#define RX_RES_STATUS_SEC_TYPE_WEP (0x1 << 8)
#define RX_RES_STATUS_SEC_TYPE_CCMP (0x2 << 8)
#define RX_RES_STATUS_SEC_TYPE_TKIP (0x3 << 8)
#define RX_RES_STATUS_DECRYPT_TYPE_MSK (0x3 << 11)
#define RX_RES_STATUS_NOT_DECRYPT (0x0 << 11)
#define RX_RES_STATUS_DECRYPT_OK (0x3 << 11)
#define RX_RES_STATUS_BAD_ICV_MIC (0x1 << 11)
#define RX_RES_STATUS_BAD_KEY_TTAK (0x2 << 11)
struct iwl3945_rx_frame_end {
__le32 status;
......
drivers/net/wireless/iwlwifi/iwl-3945-core.h 0 → 100644
View file @ ba73d4c8
/******************************************************************************
*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
* USA
*
* The full GNU General Public License is included in this distribution
* in the file called LICENSE.GPL.
*
* Contact Information:
* Tomas Winkler <tomas.winkler@intel.com>
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#ifndef __iwl_3945_dev_h__
#define __iwl_3945_dev_h__
#define IWL_PCI_DEVICE(dev, subdev, cfg) \
.vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \
.subvendor = PCI_ANY_ID, .subdevice = (subdev), \
.driver_data = (kernel_ulong_t)&(cfg)
#define IWL_SKU_G 0x1
#define IWL_SKU_A 0x2
struct iwl_3945_cfg {
const char *name;
const char *fw_name;
unsigned int sku;
};
#endif /* __iwl_dev_h__ */
drivers/net/wireless/iwlwifi/iwl-3945-debug.h
View file @ ba73d4c8
......@@ -40,6 +40,15 @@ do { if (iwl3945_debug_level & (level)) \
do { if ((iwl3945_debug_level & (level)) && net_ratelimit()) \
printk(KERN_ERR DRV_NAME": %c %s " fmt, \
in_interrupt() ? 'I' : 'U', __FUNCTION__ , ## args); } while (0)
static inline void iwl3945_print_hex_dump(int level, void *p, u32 len)
{
if (!(iwl3945_debug_level & level))
return;
print_hex_dump(KERN_DEBUG, "iwl data: ", DUMP_PREFIX_OFFSET, 16, 1,
p, len, 1);
}
#else
static inline void IWL_DEBUG(int level, const char *fmt, ...)
{
......@@ -47,7 +56,12 @@ static inline void IWL_DEBUG(int level, const char *fmt, ...)
static inline void IWL_DEBUG_LIMIT(int level, const char *fmt, ...)
{
}
#endif /* CONFIG_IWL3945_DEBUG */
static inline void iwl3945_print_hex_dump(int level, void *p, u32 len)
{
}
#endif /* CONFIG_IWL3945_DEBUG */
/*
* To use the debug system;
......@@ -143,6 +157,7 @@ static inline void IWL_DEBUG_LIMIT(int level, const char *fmt, ...)
IWL_DEBUG_LIMIT(IWL_DL_ASSOC | IWL_DL_INFO, f, ## a)
#define IWL_DEBUG_HT(f, a...) IWL_DEBUG(IWL_DL_HT, f, ## a)
#define IWL_DEBUG_STATS(f, a...) IWL_DEBUG(IWL_DL_STATS, f, ## a)
#define IWL_DEBUG_STATS_LIMIT(f, a...) IWL_DEBUG_LIMIT(IWL_DL_STATS, f, ## a)
#define IWL_DEBUG_TX_REPLY(f, a...) IWL_DEBUG(IWL_DL_TX_REPLY, f, ## a)
#define IWL_DEBUG_QOS(f, a...) IWL_DEBUG(IWL_DL_QOS, f, ## a)
#define IWL_DEBUG_RADIO(f, a...) IWL_DEBUG(IWL_DL_RADIO, f, ## a)
......
drivers/net/wireless/iwlwifi/iwl-3945-hw.h
View file @ ba73d4c8
......@@ -321,180 +321,6 @@ struct iwl3945_eeprom {
#define PCI_REG_WUM8 0x0E8
#define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000)
/*=== CSR (control and status registers) ===*/
#define CSR_BASE (0x000)
#define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
#define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
#define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
#define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
#define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
#define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
#define CSR_GP_CNTRL (CSR_BASE+0x024)
/*
* Hardware revision info
* Bit fields:
* 31-8: Reserved
* 7-4: Type of device: 0x0 = 4965, 0xd = 3945
* 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
* 1-0: "Dash" value, as in A-1, etc.
*/
#define CSR_HW_REV (CSR_BASE+0x028)
/* EEPROM reads */
#define CSR_EEPROM_REG (CSR_BASE+0x02c)
#define CSR_EEPROM_GP (CSR_BASE+0x030)
#define CSR_GP_UCODE (CSR_BASE+0x044)
#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
/* Analog phase-lock-loop configuration (3945 only)
* Set bit 24. */
#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
/* Bits for CSR_HW_IF_CONFIG_REG */
#define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MB (0x00000100)
#define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MM (0x00000200)
#define CSR_HW_IF_CONFIG_REG_BIT_SKU_MRC (0x00000400)
#define CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE (0x00000800)
#define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000)
#define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000)
#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
* acknowledged (reset) by host writing "1" to flagged bits. */
#define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
#define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
#define CSR_INT_BIT_DNLD (1 << 28) /* uCode Download */
#define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
#define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
#define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
#define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
#define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
#define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses, 3945 */
#define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
#define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
#define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \
CSR_INT_BIT_HW_ERR | \
CSR_INT_BIT_FH_TX | \
CSR_INT_BIT_SW_ERR | \
CSR_INT_BIT_RF_KILL | \
CSR_INT_BIT_SW_RX | \
CSR_INT_BIT_WAKEUP | \
CSR_INT_BIT_ALIVE)
/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
#define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
#define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
#define CSR_FH_INT_BIT_RX_CHNL2 (1 << 18) /* Rx channel 2 (3945 only) */
#define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
#define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
#define CSR_FH_INT_BIT_TX_CHNL6 (1 << 6) /* Tx channel 6 (3945 only) */
#define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
#define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
#define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
CSR_FH_INT_BIT_RX_CHNL2 | \
CSR_FH_INT_BIT_RX_CHNL1 | \
CSR_FH_INT_BIT_RX_CHNL0)
#define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL6 | \
CSR_FH_INT_BIT_TX_CHNL1 | \
CSR_FH_INT_BIT_TX_CHNL0)
/* RESET */
#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
#define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
#define CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
/* GP (general purpose) CONTROL */
#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
#define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
/* EEPROM REG */
#define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
#define CSR_EEPROM_REG_BIT_CMD (0x00000002)
/* EEPROM GP */
#define CSR_EEPROM_GP_VALID_MSK (0x00000006)
#define CSR_EEPROM_GP_BAD_SIGNATURE (0x00000000)
#define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
/* UCODE DRV GP */
#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
#define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
/* GPIO */
#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC CSR_GPIO_IN_BIT_AUX_POWER
/* GI Chicken Bits */
#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
/* CSR_ANA_PLL_CFG */
#define CSR_ANA_PLL_CFG_SH (0x00880300)
/*=== HBUS (Host-side Bus) ===*/
#define HBUS_BASE (0x400)
/*
* Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
* structures, error log, event log, verifying uCode load).
* First write to address register, then read from or write to data register
* to complete the job. Once the address register is set up, accesses to
* data registers auto-increment the address by one dword.
* Bit usage for address registers (read or write):
* 0-31: memory address within device
*/
#define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c)
#define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010)
#define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018)
#define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c)
/*
* Registers for accessing device's internal peripheral registers
* (e.g. SCD, BSM, etc.). First write to address register,
* then read from or write to data register to complete the job.
* Bit usage for address registers (read or write):
* 0-15: register address (offset) within device
* 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
*/
#define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044)
#define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048)
#define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c)
#define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050)
/*
* Per-Tx-queue write pointer (index, really!) (3945 and 4965).
* Indicates index to next TFD that driver will fill (1 past latest filled).
* Bit usage:
* 0-7: queue write index
* 11-8: queue selector
*/
#define HBUS_TARG_WRPTR (HBUS_BASE+0x060)
/* SCD (3945 Tx Frame Scheduler) */
#define SCD_BASE (CSR_BASE + 0x2E00)
......
drivers/net/wireless/iwlwifi/iwl-3945-rs.c
View file @ ba73d4c8
......@@ -158,9 +158,9 @@ static void iwl3945_clear_window(struct iwl3945_rate_scale_data *window)
{
window->data = 0;
window->success_counter = 0;
window->success_ratio = IWL_INVALID_VALUE;
window->success_ratio = -1;
window->counter = 0;
window->average_tpt = IWL_INVALID_VALUE;
window->average_tpt = IWL_INV_TPT;
window->stamp = 0;
}
......@@ -459,22 +459,23 @@ static void rs_tx_status(void *priv_rate,
struct iwl3945_rs_sta *rs_sta;
struct ieee80211_supported_band *sband;
IWL_DEBUG_RATE("enter\n");
sband = local->hw.wiphy->bands[local->hw.conf.channel->band];
IWL_DEBUG_RATE("enter\n");
retries = tx_resp->retry_count;
/* FIXME : this is wrong */
first_index = &sband->bitrates[0] - tx_resp->control.tx_rate;
first_index = tx_resp->control.tx_rate->hw_value;
if ((first_index < 0) || (first_index >= IWL_RATE_COUNT)) {
IWL_DEBUG_RATE("leave: Rate out of bounds: %d\n", first_index);
return;
}
rcu_read_lock();
sta = sta_info_get(local, hdr->addr1);
if (!sta || !sta->rate_ctrl_priv) {
if (sta)
sta_info_put(sta);
rcu_read_unlock();
IWL_DEBUG_RATE("leave: No STA priv data to update!\n");
return;
}
......@@ -547,7 +548,7 @@ static void rs_tx_status(void *priv_rate,
spin_unlock_irqrestore(&rs_sta->lock, flags);
sta_info_put(sta);
rcu_read_unlock();
IWL_DEBUG_RATE("leave\n");
......@@ -633,7 +634,7 @@ static u16 iwl3945_get_adjacent_rate(struct iwl3945_rs_sta *rs_sta,
*
*/
static void rs_get_rate(void *priv_rate, struct net_device *dev,
struct ieee80211_supported_band *band,
struct ieee80211_supported_band *sband,
struct sk_buff *skb,
struct rate_selection *sel)
{
......@@ -643,9 +644,9 @@ static void rs_get_rate(void *priv_rate, struct net_device *dev,
int index;
struct iwl3945_rs_sta *rs_sta;
struct iwl3945_rate_scale_data *window = NULL;
int current_tpt = IWL_INVALID_VALUE;
int low_tpt = IWL_INVALID_VALUE;
int high_tpt = IWL_INVALID_VALUE;
int current_tpt = IWL_INV_TPT;
int low_tpt = IWL_INV_TPT;
int high_tpt = IWL_INV_TPT;
u32 fail_count;
s8 scale_action = 0;
unsigned long flags;
......@@ -658,6 +659,8 @@ static void rs_get_rate(void *priv_rate, struct net_device *dev,
IWL_DEBUG_RATE("enter\n");
rcu_read_lock();
sta = sta_info_get(local, hdr->addr1);
/* Send management frames and broadcast/multicast data using lowest
......@@ -667,16 +670,15 @@ static void rs_get_rate(void *priv_rate, struct net_device *dev,
is_multicast_ether_addr(hdr->addr1) ||
!sta || !sta->rate_ctrl_priv) {
IWL_DEBUG_RATE("leave: No STA priv data to update!\n");
sel->rate = rate_lowest(local, band, sta);
if (sta)
sta_info_put(sta);
sel->rate = rate_lowest(local, sband, sta);
rcu_read_unlock();
return;
}
rate_mask = sta->supp_rates[band->band];
rate_mask = sta->supp_rates[sband->band];
index = min(sta->last_txrate_idx & 0xffff, IWL_RATE_COUNT - 1);
if (priv->band == IEEE80211_BAND_5GHZ)
if (sband->band == IEEE80211_BAND_5GHZ)
rate_mask = rate_mask << IWL_FIRST_OFDM_RATE;
rs_sta = (void *)sta->rate_ctrl_priv;
......@@ -708,7 +710,7 @@ static void rs_get_rate(void *priv_rate, struct net_device *dev,
if (((fail_count <= IWL_RATE_MIN_FAILURE_TH) &&
(window->success_counter < IWL_RATE_MIN_SUCCESS_TH))) {
window->average_tpt = IWL_INVALID_VALUE;
window->average_tpt = IWL_INV_TPT;
spin_unlock_irqrestore(&rs_sta->lock, flags);
IWL_DEBUG_RATE("Invalid average_tpt on rate %d: "
......@@ -727,7 +729,7 @@ static void rs_get_rate(void *priv_rate, struct net_device *dev,
current_tpt = window->average_tpt;
high_low = iwl3945_get_adjacent_rate(rs_sta, index, rate_mask,
band->band);
sband->band);
low = high_low & 0xff;
high = (high_low >> 8) & 0xff;
......@@ -744,19 +746,16 @@ static void rs_get_rate(void *priv_rate, struct net_device *dev,
if ((window->success_ratio < IWL_RATE_DECREASE_TH) || !current_tpt) {
IWL_DEBUG_RATE("decrease rate because of low success_ratio\n");
scale_action = -1;
} else if ((low_tpt == IWL_INVALID_VALUE) &&
(high_tpt == IWL_INVALID_VALUE))
} else if ((low_tpt == IWL_INV_TPT) && (high_tpt == IWL_INV_TPT))
scale_action = 1;
else if ((low_tpt != IWL_INVALID_VALUE) &&
(high_tpt != IWL_INVALID_VALUE)
&& (low_tpt < current_tpt)
&& (high_tpt < current_tpt)) {
else if ((low_tpt != IWL_INV_TPT) && (high_tpt != IWL_INV_TPT) &&
(low_tpt < current_tpt) && (high_tpt < current_tpt)) {
IWL_DEBUG_RATE("No action -- low [%d] & high [%d] < "
"current_tpt [%d]\n",
low_tpt, high_tpt, current_tpt);
scale_action = 0;
} else {
if (high_tpt != IWL_INVALID_VALUE) {
if (high_tpt != IWL_INV_TPT) {
if (high_tpt > current_tpt)
scale_action = 1;
else {
......@@ -764,7 +763,7 @@ static void rs_get_rate(void *priv_rate, struct net_device *dev,
("decrease rate because of high tpt\n");
scale_action = -1;
}
} else if (low_tpt != IWL_INVALID_VALUE) {
} else if (low_tpt != IWL_INV_TPT) {
if (low_tpt > current_tpt) {
IWL_DEBUG_RATE
("decrease rate because of low tpt\n");
......@@ -806,16 +805,16 @@ static void rs_get_rate(void *priv_rate, struct net_device *dev,
out:
sta->last_txrate_idx = index;
if (priv->band == IEEE80211_BAND_5GHZ)
if (sband->band == IEEE80211_BAND_5GHZ)
sta->txrate_idx = sta->last_txrate_idx - IWL_FIRST_OFDM_RATE;
else
sta->txrate_idx = sta->last_txrate_idx;
sta_info_put(sta);
rcu_read_unlock();
IWL_DEBUG_RATE("leave: %d\n", index);
sel->rate = &priv->ieee_rates[index];
sel->rate = &sband->bitrates[sta->txrate_idx];
}
static struct rate_control_ops rs_ops = {
......@@ -843,13 +842,15 @@ int iwl3945_fill_rs_info(struct ieee80211_hw *hw, char *buf, u8 sta_id)
unsigned long now = jiffies;
u32 max_time = 0;
rcu_read_lock();
sta = sta_info_get(local, priv->stations[sta_id].sta.sta.addr);
if (!sta || !sta->rate_ctrl_priv) {
if (sta) {
sta_info_put(sta);
if (sta)
IWL_DEBUG_RATE("leave - no private rate data!\n");
} else
else
IWL_DEBUG_RATE("leave - no station!\n");
rcu_read_unlock();
return sprintf(buf, "station %d not found\n", sta_id);
}
......@@ -890,7 +891,7 @@ int iwl3945_fill_rs_info(struct ieee80211_hw *hw, char *buf, u8 sta_id)
i = j;
}
spin_unlock_irqrestore(&rs_sta->lock, flags);
sta_info_put(sta);
rcu_read_unlock();
/* Display the average rate of all samples taken.
*
......@@ -927,11 +928,12 @@ void iwl3945_rate_scale_init(struct ieee80211_hw *hw, s32 sta_id)
return;
}
rcu_read_lock();
sta = sta_info_get(local, priv->stations[sta_id].sta.sta.addr);
if (!sta || !sta->rate_ctrl_priv) {
if (sta)
sta_info_put(sta);
IWL_DEBUG_RATE("leave - no private rate data!\n");
rcu_read_unlock();
return;
}
......@@ -958,7 +960,7 @@ void iwl3945_rate_scale_init(struct ieee80211_hw *hw, s32 sta_id)
break;
}
sta_info_put(sta);
rcu_read_unlock();
spin_unlock_irqrestore(&rs_sta->lock, flags);
rssi = priv->last_rx_rssi;
......
drivers/net/wireless/iwlwifi/iwl-3945-rs.h
View file @ ba73d4c8
......@@ -36,8 +36,8 @@ struct iwl3945_rate_info {
u8 next_rs; /* next rate used in rs algo */
u8 prev_rs_tgg; /* previous rate used in TGG rs algo */
u8 next_rs_tgg; /* next rate used in TGG rs algo */
u8 table_rs_index; /* index in rate scale table cmd */
u8 prev_table_rs; /* prev in rate table cmd */
u8 table_rs_index; /* index in rate scale table cmd */
u8 prev_table_rs; /* prev in rate table cmd */
};
/*
......@@ -159,7 +159,7 @@ enum {
#define IWL_RATES_MASK ((1 << IWL_RATE_COUNT) - 1)
#define IWL_INVALID_VALUE -1
#define IWL_INV_TPT -1
#define IWL_MIN_RSSI_VAL -100
#define IWL_MAX_RSSI_VAL 0
......
drivers/net/wireless/iwlwifi/iwl-3945.c
View file @ ba73d4c8
This diff is collapsed.
drivers/net/wireless/iwlwifi/iwl-3945.h
View file @ ba73d4c8
......@@ -40,10 +40,17 @@
extern struct pci_device_id iwl3945_hw_card_ids[];
#define DRV_NAME "iwl3945"
#include "iwl-3945-hw.h"
#include "iwl-csr.h"
#include "iwl-prph.h"
#include "iwl-3945-hw.h"
#include "iwl-3945-debug.h"
/* Change firmware file name, using "-" and incrementing number,
* *only* when uCode interface or architecture changes so that it
* is not compatible with earlier drivers.
* This number will also appear in << 8 position of 1st dword of uCode file */
#define IWL3945_UCODE_API "-1"
/* Default noise level to report when noise measurement is not available.
* This may be because we're:
* 1) Not associated (4965, no beacon statistics being sent to driver)
......@@ -109,6 +116,9 @@ struct iwl3945_queue {
* space less than this */
} __attribute__ ((packed));
int iwl3945_queue_space(const struct iwl3945_queue *q);
int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i);
#define MAX_NUM_OF_TBS (20)
/* One for each TFD */
......@@ -558,16 +568,6 @@ extern int iwl3945_is_network_packet(struct iwl3945_priv *priv,
struct ieee80211_hdr *header);
extern int iwl3945_power_init_handle(struct iwl3945_priv *priv);
extern int iwl3945_eeprom_init(struct iwl3945_priv *priv);
#ifdef CONFIG_IWL3945_DEBUG
extern void iwl3945_report_frame(struct iwl3945_priv *priv,
struct iwl3945_rx_packet *pkt,
struct ieee80211_hdr *header, int group100);
#else
static inline void iwl3945_report_frame(struct iwl3945_priv *priv,
struct iwl3945_rx_packet *pkt,
struct ieee80211_hdr *header,
int group100) {}
#endif
extern void iwl3945_handle_data_packet_monitor(struct iwl3945_priv *priv,
struct iwl3945_rx_mem_buffer *rxb,
void *data, short len,
......@@ -691,6 +691,7 @@ struct iwl3945_priv {
struct ieee80211_hw *hw;
struct ieee80211_channel *ieee_channels;
struct ieee80211_rate *ieee_rates;
struct iwl_3945_cfg *cfg; /* device configuration */
/* temporary frame storage list */
struct list_head free_frames;
......@@ -800,7 +801,6 @@ struct iwl3945_priv {
struct iwl3945_tx_queue txq[IWL_MAX_NUM_QUEUES];
unsigned long status;
u32 config;
int last_rx_rssi; /* From Rx packet statisitics */
int last_rx_noise; /* From beacon statistics */
......@@ -830,7 +830,6 @@ struct iwl3945_priv {
int is_open;
u8 mac80211_registered;
int is_abg;
u32 notif_missed_beacons;
......@@ -950,16 +949,6 @@ static inline int is_channel_ibss(const struct iwl3945_channel_info *ch)
return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0;
}
static inline int iwl3945_rate_index_from_plcp(int plcp)
{
int i;
for (i = 0; i < IWL_RATE_COUNT; i++)
if (iwl3945_rates[i].plcp == plcp)
return i;
return -1;
}
extern const struct iwl3945_channel_info *iwl3945_get_channel_info(
const struct iwl3945_priv *priv, enum ieee80211_band band, u16 channel);
......
drivers/net/wireless/iwlwifi/iwl-4965-commands.h
View file @ ba73d4c8
......@@ -875,26 +875,26 @@ struct iwl4965_rx_frame_hdr {
u8 payload[0];
} __attribute__ ((packed));
#define RX_RES_STATUS_NO_CRC32_ERROR __constant_cpu_to_le32(1 << 0)
#define RX_RES_STATUS_NO_RXE_OVERFLOW __constant_cpu_to_le32(1 << 1)
#define RX_RES_PHY_FLAGS_BAND_24_MSK __constant_cpu_to_le16(1 << 0)
#define RX_RES_PHY_FLAGS_MOD_CCK_MSK __constant_cpu_to_le16(1 << 1)
#define RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK __constant_cpu_to_le16(1 << 2)
#define RX_RES_PHY_FLAGS_NARROW_BAND_MSK __constant_cpu_to_le16(1 << 3)
#define RX_RES_PHY_FLAGS_ANTENNA_MSK __constant_cpu_to_le16(0xf0)
#define RX_RES_STATUS_SEC_TYPE_MSK (0x7 << 8)
#define RX_RES_STATUS_SEC_TYPE_NONE (0x0 << 8)
#define RX_RES_STATUS_SEC_TYPE_WEP (0x1 << 8)
#define RX_RES_STATUS_SEC_TYPE_CCMP (0x2 << 8)
#define RX_RES_STATUS_SEC_TYPE_TKIP (0x3 << 8)
#define RX_RES_STATUS_DECRYPT_TYPE_MSK (0x3 << 11)
#define RX_RES_STATUS_NOT_DECRYPT (0x0 << 11)
#define RX_RES_STATUS_DECRYPT_OK (0x3 << 11)
#define RX_RES_STATUS_BAD_ICV_MIC (0x1 << 11)
#define RX_RES_STATUS_BAD_KEY_TTAK (0x2 << 11)
#define RX_RES_STATUS_NO_CRC32_ERROR __constant_cpu_to_le32(1 << 0)
#define RX_RES_STATUS_NO_RXE_OVERFLOW __constant_cpu_to_le32(1 << 1)
#define RX_RES_PHY_FLAGS_BAND_24_MSK __constant_cpu_to_le16(1 << 0)
#define RX_RES_PHY_FLAGS_MOD_CCK_MSK __constant_cpu_to_le16(1 << 1)
#define RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK __constant_cpu_to_le16(1 << 2)
#define RX_RES_PHY_FLAGS_NARROW_BAND_MSK __constant_cpu_to_le16(1 << 3)
#define RX_RES_PHY_FLAGS_ANTENNA_MSK __constant_cpu_to_le16(0xf0)
#define RX_RES_STATUS_SEC_TYPE_MSK (0x7 << 8)
#define RX_RES_STATUS_SEC_TYPE_NONE (0x0 << 8)
#define RX_RES_STATUS_SEC_TYPE_WEP (0x1 << 8)
#define RX_RES_STATUS_SEC_TYPE_CCMP (0x2 << 8)
#define RX_RES_STATUS_SEC_TYPE_TKIP (0x3 << 8)
#define RX_RES_STATUS_DECRYPT_TYPE_MSK (0x3 << 11)
#define RX_RES_STATUS_NOT_DECRYPT (0x0 << 11)
#define RX_RES_STATUS_DECRYPT_OK (0x3 << 11)
#define RX_RES_STATUS_BAD_ICV_MIC (0x1 << 11)
#define RX_RES_STATUS_BAD_KEY_TTAK (0x2 << 11)
struct iwl4965_rx_frame_end {
__le32 status;
......
drivers/net/wireless/iwlwifi/iwl-4965-debug.h
View file @ ba73d4c8
......@@ -40,15 +40,30 @@ do { if (iwl4965_debug_level & (level)) \
do { if ((iwl4965_debug_level & (level)) && net_ratelimit()) \
printk(KERN_ERR DRV_NAME": %c %s " fmt, \
in_interrupt() ? 'I' : 'U', __FUNCTION__ , ## args); } while (0)
static inline void iwl4965_print_hex_dump(int level, void *p, u32 len)
{
if (!(iwl4965_debug_level & level))
return;
print_hex_dump(KERN_DEBUG, "iwl data: ", DUMP_PREFIX_OFFSET, 16, 1,
p, len, 1);
}
#else
static inline void IWL_DEBUG(int level, const char *fmt, ...)
{
}
static inline void IWL_DEBUG_LIMIT(int level, const char *fmt, ...)
{
}
static inline void iwl4965_print_hex_dump(int level, void *p, u32 len)
{
}
#endif /* CONFIG_IWL4965_DEBUG */
/*
* To use the debug system;
*
......@@ -143,6 +158,7 @@ static inline void IWL_DEBUG_LIMIT(int level, const char *fmt, ...)
IWL_DEBUG_LIMIT(IWL_DL_ASSOC | IWL_DL_INFO, f, ## a)
#define IWL_DEBUG_HT(f, a...) IWL_DEBUG(IWL_DL_HT, f, ## a)
#define IWL_DEBUG_STATS(f, a...) IWL_DEBUG(IWL_DL_STATS, f, ## a)
#define IWL_DEBUG_STATS_LIMIT(f, a...) IWL_DEBUG_LIMIT(IWL_DL_STATS, f, ## a)
#define IWL_DEBUG_TX_REPLY(f, a...) IWL_DEBUG(IWL_DL_TX_REPLY, f, ## a)
#define IWL_DEBUG_QOS(f, a...) IWL_DEBUG(IWL_DL_QOS, f, ## a)
#define IWL_DEBUG_RADIO(f, a...) IWL_DEBUG(IWL_DL_RADIO, f, ## a)
......
drivers/net/wireless/iwlwifi/iwl-4965-hw.h
View file @ ba73d4c8
......@@ -410,181 +410,6 @@ struct iwl4965_eeprom {
#define PCI_REG_WUM8 0x0E8
#define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000)
/*=== CSR (control and status registers) ===*/
#define CSR_BASE (0x000)
#define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
#define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
#define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
#define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
#define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
#define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
#define CSR_GP_CNTRL (CSR_BASE+0x024)
/*
* Hardware revision info
* Bit fields:
* 31-8: Reserved
* 7-4: Type of device: 0x0 = 4965, 0xd = 3945
* 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
* 1-0: "Dash" value, as in A-1, etc.
*
* NOTE: Revision step affects calculation of CCK txpower for 4965.
*/
#define CSR_HW_REV (CSR_BASE+0x028)
/* EEPROM reads */
#define CSR_EEPROM_REG (CSR_BASE+0x02c)
#define CSR_EEPROM_GP (CSR_BASE+0x030)
#define CSR_GP_UCODE (CSR_BASE+0x044)
#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
/*
* Indicates hardware rev, to determine CCK backoff for txpower calculation.
* Bit fields:
* 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
*/
#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
/* Hardware interface configuration bits */
#define CSR_HW_IF_CONFIG_REG_BIT_KEDRON_R (0x00000010)
#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00)
#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
#define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
* acknowledged (reset) by host writing "1" to flagged bits. */
#define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
#define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
#define CSR_INT_BIT_DNLD (1 << 28) /* uCode Download */
#define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
#define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
#define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
#define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
#define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
#define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses, 3945 */
#define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
#define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
#define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \
CSR_INT_BIT_HW_ERR | \
CSR_INT_BIT_FH_TX | \
CSR_INT_BIT_SW_ERR | \
CSR_INT_BIT_RF_KILL | \
CSR_INT_BIT_SW_RX | \
CSR_INT_BIT_WAKEUP | \
CSR_INT_BIT_ALIVE)
/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
#define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
#define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
#define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
#define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
#define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
#define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
#define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
CSR_FH_INT_BIT_RX_CHNL1 | \
CSR_FH_INT_BIT_RX_CHNL0)
#define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \
CSR_FH_INT_BIT_TX_CHNL0)
/* RESET */
#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
#define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
#define CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
/* GP (general purpose) CONTROL */
#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
#define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
/* EEPROM REG */
#define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
#define CSR_EEPROM_REG_BIT_CMD (0x00000002)
/* EEPROM GP */
#define CSR_EEPROM_GP_VALID_MSK (0x00000006)
#define CSR_EEPROM_GP_BAD_SIGNATURE (0x00000000)
#define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
/* UCODE DRV GP */
#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
#define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
/* GPIO */
#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC CSR_GPIO_IN_BIT_AUX_POWER
/* GI Chicken Bits */
#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
/*=== HBUS (Host-side Bus) ===*/
#define HBUS_BASE (0x400)
/*
* Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
* structures, error log, event log, verifying uCode load).
* First write to address register, then read from or write to data register
* to complete the job. Once the address register is set up, accesses to
* data registers auto-increment the address by one dword.
* Bit usage for address registers (read or write):
* 0-31: memory address within device
*/
#define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c)
#define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010)
#define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018)
#define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c)
/*
* Registers for accessing device's internal peripheral registers
* (e.g. SCD, BSM, etc.). First write to address register,
* then read from or write to data register to complete the job.
* Bit usage for address registers (read or write):
* 0-15: register address (offset) within device
* 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
*/
#define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044)
#define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048)
#define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c)
#define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050)
/*
* Per-Tx-queue write pointer (index, really!) (3945 and 4965).
* Driver sets this to indicate index to next TFD that driver will fill
* (1 past latest filled).
* Bit usage:
* 0-7: queue write index (0-255)
* 11-8: queue selector (0-15)
*/
#define HBUS_TARG_WRPTR (HBUS_BASE+0x060)
#define HBUS_TARG_MBX_C (HBUS_BASE+0x030)
#define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
#define TFD_QUEUE_SIZE_MAX (256)
#define IWL_NUM_SCAN_RATES (2)
......
drivers/net/wireless/iwlwifi/iwl-4965-rs.c
View file @ ba73d4c8
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drivers/net/wireless/iwlwifi/iwl-4965-rs.h
View file @ ba73d4c8
......@@ -259,7 +259,7 @@ static inline u8 iwl4965_get_prev_ieee_rate(u8 rate_index)
return rate;
}
extern int iwl4965_rate_index_from_plcp(int plcp);
extern int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags);
/**
* iwl4965_fill_rs_info - Fill an output text buffer with the rate representation
......
drivers/net/wireless/iwlwifi/iwl-4965.c
View file @ ba73d4c8
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drivers/net/wireless/iwlwifi/iwl-4965.h
View file @ ba73d4c8
......@@ -41,9 +41,17 @@ extern struct pci_device_id iwl4965_hw_card_ids[];
#define DRV_NAME "iwl4965"
#include "iwl-4965-hw.h"
#include "iwl-csr.h"
#include "iwl-prph.h"
#include "iwl-4965-debug.h"
/* Change firmware file name, using "-" and incrementing number,
* *only* when uCode interface or architecture changes so that it
* is not compatible with earlier drivers.
* This number will also appear in << 8 position of 1st dword of uCode file */
#define IWL4965_UCODE_API "-1"
/* Default noise level to report when noise measurement is not available.
* This may be because we're:
* 1) Not associated (4965, no beacon statistics being sent to driver)
......@@ -633,16 +641,6 @@ extern int iwl4965_is_network_packet(struct iwl4965_priv *priv,
struct ieee80211_hdr *header);
extern int iwl4965_power_init_handle(struct iwl4965_priv *priv);
extern int iwl4965_eeprom_init(struct iwl4965_priv *priv);
#ifdef CONFIG_IWL4965_DEBUG
extern void iwl4965_report_frame(struct iwl4965_priv *priv,
struct iwl4965_rx_packet *pkt,
struct ieee80211_hdr *header, int group100);
#else
static inline void iwl4965_report_frame(struct iwl4965_priv *priv,
struct iwl4965_rx_packet *pkt,
struct ieee80211_hdr *header,
int group100) {}
#endif
extern void iwl4965_handle_data_packet_monitor(struct iwl4965_priv *priv,
struct iwl4965_rx_mem_buffer *rxb,
void *data, short len,
......@@ -767,6 +765,9 @@ extern int iwl4965_set_fat_chan_info(struct iwl4965_priv *priv,
const struct iwl4965_eeprom_channel *eeprom_ch,
u8 fat_extension_channel);
extern void iwl4965_rf_kill_ct_config(struct iwl4965_priv *priv);
extern void iwl4965_hwrate_to_tx_control(struct iwl4965_priv *priv,
u32 rate_n_flags,
struct ieee80211_tx_control *control);
#ifdef CONFIG_IWL4965_HT
void iwl4965_init_ht_hw_capab(struct ieee80211_ht_info *ht_info,
......@@ -808,11 +809,10 @@ struct iwl4965_kw {
#define IWL_OPERATION_MODE_MIXED 2
#define IWL_OPERATION_MODE_20MHZ 3
#define IWL_EXT_CHANNEL_OFFSET_AUTO 0
#define IWL_EXT_CHANNEL_OFFSET_ABOVE 1
#define IWL_EXT_CHANNEL_OFFSET_ 2
#define IWL_EXT_CHANNEL_OFFSET_BELOW 3
#define IWL_EXT_CHANNEL_OFFSET_MAX 4
#define IWL_EXT_CHANNEL_OFFSET_NONE 0
#define IWL_EXT_CHANNEL_OFFSET_ABOVE 1
#define IWL_EXT_CHANNEL_OFFSET_RESERVE1 2
#define IWL_EXT_CHANNEL_OFFSET_BELOW 3
#define NRG_NUM_PREV_STAT_L 20
#define NUM_RX_CHAINS (3)
......@@ -974,6 +974,7 @@ struct iwl4965_priv {
struct ieee80211_hw *hw;
struct ieee80211_channel *ieee_channels;
struct ieee80211_rate *ieee_rates;
struct iwl_cfg *cfg;
/* temporary frame storage list */
struct list_head free_frames;
......@@ -1104,7 +1105,6 @@ struct iwl4965_priv {
u32 scd_base_addr; /* scheduler sram base address */
unsigned long status;
u32 config;
int last_rx_rssi; /* From Rx packet statisitics */
int last_rx_noise; /* From beacon statistics */
......@@ -1134,7 +1134,6 @@ struct iwl4965_priv {
int is_open;
u8 mac80211_registered;
int is_abg;
u32 notif_missed_beacons;
......
drivers/net/wireless/iwlwifi/iwl-core.c 0 → 100644
View file @ ba73d4c8
/******************************************************************************
*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
* USA
*
* The full GNU General Public License is included in this distribution
* in the file called LICENSE.GPL.
*
* Contact Information:
* Tomas Winkler <tomas.winkler@intel.com>
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*****************************************************************************/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/version.h>
#include "iwl-4965-debug.h"
#include "iwl-core.h"
MODULE_DESCRIPTION("iwl core");
MODULE_VERSION(IWLWIFI_VERSION);
MODULE_AUTHOR(DRV_COPYRIGHT);
MODULE_LICENSE("GPL/BSD");
#ifdef CONFIG_IWL4965_DEBUG
u32 iwl4965_debug_level;
EXPORT_SYMBOL(iwl4965_debug_level);
#endif
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drivers/net/wireless/libertas/cmd.h
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......@@ -57,5 +57,7 @@ int lbs_cmd_802_11_set_wep(struct lbs_private *priv, uint16_t cmd_action,
struct assoc_request *assoc);
int lbs_cmd_802_11_enable_rsn(struct lbs_private *priv, uint16_t cmd_action,
uint16_t *enable);
int lbs_cmd_802_11_key_material(struct lbs_private *priv, uint16_t cmd_action,
struct assoc_request *assoc);
#endif /* _LBS_CMD_H */
drivers/net/wireless/libertas/cmdresp.c
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drivers/net/wireless/zd1211rw/zd_chip.c
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......@@ -809,6 +809,7 @@ static int hw_init_hmac(struct zd_chip *chip)
{ CR_AFTER_PNP, 0x1 },
{ CR_WEP_PROTECT, 0x114 },
{ CR_IFS_VALUE, IFS_VALUE_DEFAULT },
{ CR_CAM_MODE, MODE_AP_WDS},
};
ZD_ASSERT(mutex_is_locked(&chip->mutex));
......
drivers/net/wireless/zd1211rw/zd_chip.h
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net/mac80211/wpa.c
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net/mac80211/wpa.h
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net/wireless/nl80211.c
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