drm/amd/display: Refactor DIO stream encoder

* Pull duplicate audio_clock_info struct to stream_encoder.h
* Generalize sec_gsp7* to sec_gsp_pps*
* Expose enc1 and enc2 stream encoder audio funcs
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

@@ -377,10 +377,10 @@ void dcn10_log_hw_state(struct dc *dc,
 			DTN_INFO("[%-3d]: %-9d %-18d %-21d %-15d %-16d %-17d\n",
 				enc->id,
 				s.dsc_mode,
-				s.sec_gsp7_line_num,
+				s.sec_gsp_pps_line_num,
 				s.vbid6_line_reference,
 				s.vbid6_line_num,
-				s.sec_gsp7_enable,
+				s.sec_gsp_pps_enable,
 				s.sec_stream_enable);
 			DTN_INFO("\n");
 		}

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c

@@ -351,13 +351,12 @@ static void enc2_read_state(struct stream_encoder *enc, struct enc_state *s)
 	REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode);
 	if (s->dsc_mode) {
 		REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width);
-		REG_GET(DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, &s->sec_gsp7_line_num);
+		REG_GET(DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, &s->sec_gsp_pps_line_num);
 
-		REG_GET(DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, &s->sec_gsp7_line_num);
 		REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference);
 		REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num);
 
-		REG_GET(DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, &s->sec_gsp7_enable);
+		REG_GET(DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, &s->sec_gsp_pps_enable);
 		REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable);
 	}
 }
@@ -448,7 +447,7 @@ static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
 	return two_pix;
 }
 
-static void enc2_stream_encoder_dp_unblank(
+void enc2_stream_encoder_dp_unblank(
 		struct stream_encoder *enc,
 		const struct encoder_unblank_param *param)
 {
@@ -530,7 +529,7 @@ static void enc2_dp_set_odm_combine(
 	REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, odm_combine);
 }
 
-static void enc2_stream_encoder_dp_set_stream_attribute(
+void enc2_stream_encoder_dp_set_stream_attribute(
 	struct stream_encoder *enc,
 	struct dc_crtc_timing *crtc_timing,
 	enum dc_color_space output_color_space,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h

@@ -94,4 +94,14 @@ void dcn20_stream_encoder_construct(
 	const struct dcn10_stream_encoder_shift *se_shift,
 	const struct dcn10_stream_encoder_mask *se_mask);
 
+void enc2_stream_encoder_dp_set_stream_attribute(
+	struct stream_encoder *enc,
+	struct dc_crtc_timing *crtc_timing,
+	enum dc_color_space output_color_space,
+	uint32_t enable_sdp_splitting);
+
+void enc2_stream_encoder_dp_unblank(
+	struct stream_encoder *enc,
+	const struct encoder_unblank_param *param);
+
 #endif /* __DC_STREAM_ENCODER_DCN20_H__ */

drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h

@@ -113,10 +113,10 @@ struct stream_encoder {
 struct enc_state {
 	uint32_t dsc_mode;  // DISABLED  0; 1 or 2 indicate enabled state.
 	uint32_t dsc_slice_width;
-	uint32_t sec_gsp7_line_num;
+	uint32_t sec_gsp_pps_line_num;
 	uint32_t vbid6_line_reference;
 	uint32_t vbid6_line_num;
-	uint32_t sec_gsp7_enable;
+	uint32_t sec_gsp_pps_enable;
 	uint32_t sec_stream_enable;
 };
 #endif