[PATCH] ppc64: rename perf counter register #defines

This patch makes some cleanups to the #defines for various fields in the
MMCR0 performance monitor control register.  Specifically, the names of a
couple of bits are changed so that: a) they are a bit less cumbersomely
long and b) they match the names used in the hardware documentation.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

arch/ppc64/oprofile/op_model_power4.c

@@ -97,7 +97,7 @@ static void power4_cpu_setup(void *unused)
 	mtspr(SPRN_MMCR0, mmcr0);
 
 	mmcr0 |= MMCR0_FCM1|MMCR0_PMXE|MMCR0_FCECE;
-	mmcr0 |= MMCR0_PMC1INTCONTROL|MMCR0_PMCNINTCONTROL;
+	mmcr0 |= MMCR0_PMC1CE|MMCR0_PMCjCE;
 	mtspr(SPRN_MMCR0, mmcr0);
 
 	mtspr(SPRN_MMCR1, mmcr1_val);

arch/ppc64/oprofile/op_model_rs64.c

@@ -119,7 +119,7 @@ static void rs64_cpu_setup(void *unused)
 
 	mmcr0 |= MMCR0_FCM1|MMCR0_PMXE|MMCR0_FCECE;
 	/* Only applies to POWER3, but should be safe on RS64 */
-	mmcr0 |= MMCR0_PMC1INTCONTROL|MMCR0_PMCNINTCONTROL;
+	mmcr0 |= MMCR0_PMC1CE|MMCR0_PMCjCE;
 	mtspr(SPRN_MMCR0, mmcr0);
 
 	dbg("setup on cpu %d, mmcr0 %lx\n", smp_processor_id(),

include/asm-ppc64/processor.h

@@ -331,8 +331,8 @@
 #define   MMCR0_FCECE	0x02000000UL /* freeze counters on enabled condition or event */
 /* time base exception enable */
 #define   MMCR0_TBEE	0x00400000UL /* time base exception enable */
-#define   MMCR0_PMC1INTCONTROL	0x00008000UL /* PMC1 count enable*/
-#define   MMCR0_PMCNINTCONTROL	0x00004000UL /* PMCn count enable*/
+#define   MMCR0_PMC1CE	0x00008000UL /* PMC1 count enable*/
+#define   MMCR0_PMCjCE	0x00004000UL /* PMCj count enable*/
 #define   MMCR0_TRIGGER	0x00002000UL /* TRIGGER enable */
 #define   MMCR0_PMAO	0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */
 #define   MMCR0_SHRFC	0x00000040UL /* SHRre freeze conditions between threads */