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Commit bd08b0a9 authored by Andrew Morton's avatar Andrew Morton Committed by Linus Torvalds
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[PATCH] Fix support for the Motorola PrPMC800 

From: Tom Rini <trini@kernel.crashing.org>

Makes the Motorola PrPMC800 platform functional again.  This comes from Randy
Vinson <rvinson@mvista.com>.
parent 51a58c58
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Showing with 1123 additions and 433 deletions
arch/ppc/Kconfig
View file @ bd08b0a9
......@@ -609,7 +609,7 @@ config PPC_OF
config PPC_GEN550
bool
depends on SANDPOINT || MCPN765 || SPRUCE || PPLUS || PCORE || PRPMC750 || K2
depends on SANDPOINT || MCPN765 || SPRUCE || PPLUS || PCORE || PRPMC750 || K2 || PRPMC800
default y
config FORCE
......@@ -622,6 +622,15 @@ config GT64260
depends on EV64260
default y
config NONMONARCH_SUPPORT
bool "Enable Non-Monarch Support"
depends on PRPMC800
config HARRIER
bool
depends on PRPMC800
default y
config EPIC_SERIAL_MODE
bool
depends on 6xx && (LOPEC || SANDPOINT)
......@@ -640,6 +649,10 @@ config CPC710_DATA_GATHERING
bool "Enable CPC710 data gathering"
depends on K2
config HARRIER_STORE_GATHERING
bool "Enable Harrier store gathering"
depends on HARRIER
config MVME5100_IPMC761_PRESENT
bool "MVME5100 configured with an IPMC761"
depends on MVME5100
......
arch/ppc/configs/prpmc800_defconfig
View file @ bd08b0a9
This diff is collapsed.
arch/ppc/platforms/Makefile
View file @ bd08b0a9
......@@ -43,7 +43,7 @@ obj-$(CONFIG_PCORE) += pcore.o
obj-$(CONFIG_POWERPMC250) += powerpmc250.o
obj-$(CONFIG_PPLUS) += pplus.o
obj-$(CONFIG_PRPMC750) += prpmc750.o
obj-$(CONFIG_PRPMC800) += prpmc800_setup.o prpmc800_pci.o
obj-$(CONFIG_PRPMC800) += prpmc800.o
obj-$(CONFIG_SANDPOINT) += sandpoint.o
obj-$(CONFIG_SPRUCE) += spruce.o
......
arch/ppc/platforms/prpmc800.h
View file @ bd08b0a9
......@@ -5,21 +5,22 @@
*
* Author: Dale Farnsworth <dale.farnsworth@mvista.com>
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
/*
* From Processor to PCI:
* PCI Mem Space: 0x80000000 - 0xa0000000 -> 0x80000000 - 0xa0000000 (512 MB)
* PCI I/O Space: 0xfe400000 - 0xfeef0000 -> 0x00000000 - 0x00b00000 (11 MB)
* Note: Must skip 0xfe000000-0xfe400000 for CONFIG_HIGHMEM/PKMAP area
* Copyright 2001 MontaVista Software Inc.
*
* From PCI to Processor:
* System Memory: 0x00000000 -> 0x00000000
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/*
* From Processor to PCI:
* PCI Mem Space: 0x80000000 - 0xa0000000 -> 0x80000000 - 0xa0000000 (512 MB)
* PCI I/O Space: 0xfe400000 - 0xfeef0000 -> 0x00000000 - 0x00b00000 (11 MB)
* Note: Must skip 0xfe000000-0xfe400000 for CONFIG_HIGHMEM/PKMAP area
*
* From PCI to Processor:
* System Memory: 0x00000000 -> 0x00000000
*/
#ifndef __ASMPPC_PRPMC800_H
#define __ASMPPC_PRPMC800_H
......@@ -37,18 +38,29 @@
#define PRPMC800_PCI_MEM_START 0x80000000U
#define PRPMC800_PCI_MEM_END 0x9fffffffU
#define PRPMC800_NM_PROC_PCI_MEM_START 0x40000000U
#define PRPMC800_NM_PROC_PCI_MEM_END 0xdfffffffU
#define PRPMC800_NM_PCI_MEM_START 0x40000000U
#define PRPMC800_NM_PCI_MEM_END 0xdfffffffU
#define PRPMC800_PCI_DRAM_OFFSET 0x00000000U
#define PRPMC800_PCI_PHY_MEM_OFFSET 0x00000000U
#define PRPMC800_ISA_IO_BASE PRPMC800_PROC_PCI_IO_START
#define PRPMC800_ISA_MEM_BASE 0x00000000U
#define PRPMC800_HARRIER_XCSR_BASE 0xfeff0000
#define PRPMC800_HARRIER_XCSR_BASE HARRIER_DEFAULT_XCSR_BASE
#define PRPMC800_HARRIER_MPIC_BASE 0xff000000
#define PRPMC800_SERIAL_1 0xfeff00c0
#define PRPMC800_BASE_BAUD 1843200
/*
* interrupt vector number and priority for harrier internal interrupt
* sources
*/
#define PRPMC800_INT_IRQ 16
#define PRPMC800_INT_PRI 15
#endif /* __ASMPPC_PRPMC800_H */
#endif /* __ASMPPC_PRPMC800_H */
arch/ppc/platforms/prpmc800_pci.c deleted 100644 → 0
View file @ 51a58c58
/*
* arch/ppc/platforms/prpmc800_pci.c
*
* PCI support for Motorola PrPMC800
*
* Author: Dale Farnsworth <dale.farnsworth@mvista.com>
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <asm/byteorder.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <platforms/prpmc800.h>
#include <asm/harrier.h>
/*
* Motorola PrPMC750/PrPMC800 in PrPMCBASE or PrPMC-Carrier
* Combined irq tables. Only Base has IDSEL 14, only Carrier has 21 and 22.
*/
static inline int
prpmc_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
{
static char pci_irq_table[][4] =
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
{12, 0, 0, 0}, /* IDSEL 14 - Ethernet, base */
{0, 0, 0, 0}, /* IDSEL 15 - unused */
{10, 11, 12, 9}, /* IDSEL 16 - PMC A1, PMC1 */
{10, 11, 12, 9}, /* IDSEL 17 - PrPMC-A-B, PMC2-B */
{11, 12, 9, 10}, /* IDSEL 18 - PMC A1-B, PMC1-B */
{0, 0, 0, 0}, /* IDSEL 19 - unused */
{9, 10, 11, 12}, /* IDSEL 20 - P2P Bridge */
{11, 12, 9, 10}, /* IDSEL 21 - PMC A2, carrier */
{12, 9, 10, 11}, /* IDSEL 22 - PMC A2-B, carrier */
};
const long min_idsel = 14, max_idsel = 22, irqs_per_slot = 4;
return PCI_IRQ_TABLE_LOOKUP;
};
void __init
prpmc800_find_bridges(void)
{
struct pci_controller* hose;
int host_bridge;
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = PRPMC800_PCI_PHY_MEM_OFFSET;
pci_init_resource(&hose->io_resource,
PRPMC800_PCI_IO_START,
PRPMC800_PCI_IO_END,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
PRPMC800_PCI_MEM_START,
PRPMC800_PCI_MEM_END,
IORESOURCE_MEM,
"PCI host bridge");
hose->io_space.start = PRPMC800_PCI_IO_START;
hose->io_space.end = PRPMC800_PCI_IO_END;
hose->mem_space.start = PRPMC800_PCI_MEM_START;
hose->mem_space.end = PRPMC800_PCI_MEM_END;
hose->io_base_virt = (void *)PRPMC800_ISA_IO_BASE;
setup_indirect_pci(hose,
PRPMC800_PCI_CONFIG_ADDR,
PRPMC800_PCI_CONFIG_DATA);
/* Get host bridge vendor/dev id */
early_read_config_dword(hose,
0,
PCI_DEVFN(0,0),
PCI_VENDOR_ID,
&host_bridge);
switch (host_bridge) {
case HARRIER_VEND_DEV_ID:
if (harrier_init(hose,
PRPMC800_HARRIER_XCSR_BASE,
PRPMC800_PROC_PCI_MEM_START,
PRPMC800_PROC_PCI_MEM_END,
PRPMC800_PROC_PCI_IO_START,
PRPMC800_PROC_PCI_IO_END,
PRPMC800_HARRIER_MPIC_BASE) != 0) {
printk("Could not initialize HARRIER bridge\n");
}
break;
default:
printk("Host bridge 0x%x not supported\n", host_bridge);
}
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pcibios_fixup = NULL;
ppc_md.pcibios_fixup_bus = NULL;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = prpmc_map_irq;
}
arch/ppc/syslib/Makefile
View file @ bd08b0a9
......@@ -57,8 +57,8 @@ obj-$(CONFIG_PPLUS) += hawk_common.o open_pic.o i8259.o \
indirect_pci.o todc_time.o pci_auto.o
obj-$(CONFIG_PRPMC750) += open_pic.o indirect_pci.o pci_auto.o \
hawk_common.o
obj-$(CONFIG_PRPMC800) += open_pic.o indirect_pci.o pci_auto.o \
hawk_common.o harrier.o
obj-$(CONFIG_HARRIER) += harrier.o
obj-$(CONFIG_PRPMC800) += open_pic.o indirect_pci.o pci_auto.o
obj-$(CONFIG_SANDPOINT) += i8259.o open_pic.o pci_auto.o todc_time.o
obj-$(CONFIG_SPRUCE) += cpc700_pic.o indirect_pci.o pci_auto.o \
todc_time.o
......
arch/ppc/syslib/harrier.c
View file @ bd08b0a9
......@@ -14,6 +14,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/harrier_defs.h>
#include <asm/byteorder.h>
#include <asm/io.h>
......@@ -23,6 +24,93 @@
#include <asm/open_pic.h>
#include <asm/harrier.h>
/* define defaults for inbound windows */
#define HARRIER_ITAT_DEFAULT (HARRIER_ITAT_ENA | \
HARRIER_ITAT_MEM | \
HARRIER_ITAT_WPE | \
HARRIER_ITAT_GBL)
#define HARRIER_MPAT_DEFAULT (HARRIER_ITAT_ENA | \
HARRIER_ITAT_MEM | \
HARRIER_ITAT_WPE | \
HARRIER_ITAT_GBL)
/*
* Initialize the inbound window size on a non-monarch harrier.
*/
void __init harrier_setup_nonmonarch(uint ppc_reg_base, uint in0_size)
{
u16 temps;
u32 temp;
if (in0_size > HARRIER_ITSZ_2GB) {
printk
("harrier_setup_nonmonarch: Invalid window size code %d\n",
in0_size);
return;
}
/* Clear the PCI memory enable bit. If we don't, then when the
* inbound windows are enabled below, the corresponding BARs will be
* "live" and start answering to PCI memory reads from their default
* addresses (0x0), which overlap with system RAM.
*/
temps = in_le16((u16 *) (ppc_reg_base +
HARRIER_XCSR_CONFIG(PCI_COMMAND)));
temps &= ~(PCI_COMMAND_MEMORY);
out_le16((u16 *) (ppc_reg_base + HARRIER_XCSR_CONFIG(PCI_COMMAND)),
temps);
/* Setup a non-prefetchable inbound window */
out_le32((u32 *) (ppc_reg_base +
HARRIER_XCSR_CONFIG(HARRIER_ITSZ0_OFF)), in0_size);
temp = in_le32((u32 *) (ppc_reg_base +
HARRIER_XCSR_CONFIG(HARRIER_ITAT0_OFF)));
temp &= ~HARRIER_ITAT_PRE;
temp |= HARRIER_ITAT_DEFAULT;
out_le32((u32 *) (ppc_reg_base +
HARRIER_XCSR_CONFIG(HARRIER_ITAT0_OFF)), temp);
/* Enable the message passing block */
temp = in_le32((u32 *) (ppc_reg_base +
HARRIER_XCSR_CONFIG(HARRIER_MPAT_OFF)));
temp |= HARRIER_MPAT_DEFAULT;
out_le32((u32 *) (ppc_reg_base +
HARRIER_XCSR_CONFIG(HARRIER_MPAT_OFF)), temp);
}
void __init harrier_release_eready(uint ppc_reg_base)
{
ulong temp;
/*
* Set EREADY to allow the line to be pulled up after everyone is
* ready.
*/
temp = in_be32((uint *) (ppc_reg_base + HARRIER_MISC_CSR_OFF));
temp |= HARRIER_EREADY;
out_be32((uint *) (ppc_reg_base + HARRIER_MISC_CSR_OFF), temp);
}
void __init harrier_wait_eready(uint ppc_reg_base)
{
ulong temp;
/*
* Poll the ERDYS line until it goes high to indicate that all
* non-monarch PrPMCs are ready for bus enumeration (or that there are
* no PrPMCs present).
*/
/* FIXME: Add a timeout of some kind to prevent endless waits. */
do {
temp = in_be32((uint *) (ppc_reg_base + HARRIER_MISC_CSR_OFF));
} while (!(temp & HARRIER_ERDYS));
}
/*
* Initialize the Motorola MCG Harrier host bridge.
*
......@@ -40,25 +128,25 @@ harrier_init(struct pci_controller *hose,
ulong processor_pci_mem_start,
ulong processor_pci_mem_end,
ulong processor_pci_io_start,
ulong processor_pci_io_end,
ulong processor_mpic_base)
ulong processor_pci_io_end, ulong processor_mpic_base)
{
uint addr, offset;
uint addr, offset;
/*
* Some sanity checks...
*/
if (((processor_pci_mem_start&0xffff0000) != processor_pci_mem_start) ||
((processor_pci_io_start &0xffff0000) != processor_pci_io_start)) {
if (((processor_pci_mem_start & 0xffff0000) != processor_pci_mem_start)
|| ((processor_pci_io_start & 0xffff0000) !=
processor_pci_io_start)) {
printk("harrier_init: %s\n",
"PPC to PCI mappings must start on 64 KB boundaries");
"PPC to PCI mappings must start on 64 KB boundaries");
return -1;
}
if (((processor_pci_mem_end &0x0000ffff) != 0x0000ffff) ||
((processor_pci_io_end &0x0000ffff) != 0x0000ffff)) {
if (((processor_pci_mem_end & 0x0000ffff) != 0x0000ffff) ||
((processor_pci_io_end & 0x0000ffff) != 0x0000ffff)) {
printk("harrier_init: PPC to PCI mappings %s\n",
"must end just before a 64 KB boundaries");
"must end just before a 64 KB boundaries");
return -1;
}
......@@ -67,19 +155,19 @@ harrier_init(struct pci_controller *hose,
((processor_pci_io_end - processor_pci_io_start) !=
(hose->io_space.end - hose->io_space.start))) {
printk("harrier_init: %s\n",
"PPC and PCI memory or I/O space sizes don't match");
"PPC and PCI memory or I/O space sizes don't match");
return -1;
}
if ((processor_mpic_base & 0xfffc0000) != processor_mpic_base) {
printk("harrier_init: %s\n",
"MPIC address must start on 256 KB boundary");
"MPIC address must start on 256 KB boundary");
return -1;
}
if ((pci_dram_offset & 0xffff0000) != pci_dram_offset) {
printk("harrier_init: %s\n",
"pci_dram_offset must be multiple of 64 KB");
"pci_dram_offset must be multiple of 64 KB");
return -1;
}
......@@ -89,28 +177,32 @@ harrier_init(struct pci_controller *hose,
* the PCI bus.
*
* Note: Don't need to 'AND' start/end addresses with 0xffff0000
* because sanity check above ensures that they are properly
* aligned.
* because sanity check above ensures that they are properly
* aligned.
*/
/* Set up PPC->PCI Mem mapping */
addr = processor_pci_mem_start | (processor_pci_mem_end >> 16);
#ifdef CONFIG_HARRIER_STORE_GATHERING
offset = (hose->mem_space.start - processor_pci_mem_start) | 0x9a;
#else
offset = (hose->mem_space.start - processor_pci_mem_start) | 0x92;
out_be32((uint *)(ppc_reg_base + HARRIER_OTAD0_OFF), addr);
out_be32((uint *)(ppc_reg_base + HARRIER_OTOF0_OFF), offset);
#endif
out_be32((uint *) (ppc_reg_base + HARRIER_OTAD0_OFF), addr);
out_be32((uint *) (ppc_reg_base + HARRIER_OTOF0_OFF), offset);
/* Set up PPC->PCI I/O mapping -- Contiguous I/O space */
addr = processor_pci_io_start | (processor_pci_io_end >> 16);
offset = (hose->io_space.start - processor_pci_io_start) | 0x80;
out_be32((uint *)(ppc_reg_base + HARRIER_OTAD1_OFF), addr);
out_be32((uint *)(ppc_reg_base + HARRIER_OTOF1_OFF), offset);
out_be32((uint *) (ppc_reg_base + HARRIER_OTAD1_OFF), addr);
out_be32((uint *) (ppc_reg_base + HARRIER_OTOF1_OFF), offset);
/* Enable MPIC */
OpenPIC_Addr = (void *)processor_mpic_base;
addr = (processor_mpic_base >> 16) | 1;
out_be16((ushort *)(ppc_reg_base + HARRIER_MBAR_OFF), addr);
out_8((u_char *)(ppc_reg_base + HARRIER_MPIC_CSR_OFF),
HARRIER_MPIC_OPI_ENABLE);
out_be16((ushort *) (ppc_reg_base + HARRIER_MBAR_OFF), addr);
out_8((u_char *) (ppc_reg_base + HARRIER_MPIC_CSR_OFF),
HARRIER_MPIC_OPI_ENABLE);
return 0;
}
......@@ -127,22 +219,22 @@ harrier_init(struct pci_controller *hose,
#define MB (1024*1024UL)
static uint harrier_size_table[] __initdata = {
0 * MB, /* 0 ==> 0 MB */
32 * MB, /* 1 ==> 32 MB */
64 * MB, /* 2 ==> 64 MB */
64 * MB, /* 3 ==> 64 MB */
128 * MB, /* 4 ==> 128 MB */
128 * MB, /* 5 ==> 128 MB */
128 * MB, /* 6 ==> 128 MB */
256 * MB, /* 7 ==> 256 MB */
256 * MB, /* 8 ==> 256 MB */
256 * MB, /* 9 ==> 256 MB */
512 * MB, /* a ==> 512 MB */
512 * MB, /* b ==> 512 MB */
512 * MB, /* c ==> 512 MB */
1024 * MB, /* d ==> 1024 MB */
1024 * MB, /* e ==> 1024 MB */
2048 * MB, /* f ==> 2048 MB */
0 * MB, /* 0 ==> 0 MB */
32 * MB, /* 1 ==> 32 MB */
64 * MB, /* 2 ==> 64 MB */
64 * MB, /* 3 ==> 64 MB */
128 * MB, /* 4 ==> 128 MB */
128 * MB, /* 5 ==> 128 MB */
128 * MB, /* 6 ==> 128 MB */
256 * MB, /* 7 ==> 256 MB */
256 * MB, /* 8 ==> 256 MB */
256 * MB, /* 9 ==> 256 MB */
512 * MB, /* a ==> 512 MB */
512 * MB, /* b ==> 512 MB */
512 * MB, /* c ==> 512 MB */
1024 * MB, /* d ==> 1024 MB */
1024 * MB, /* e ==> 1024 MB */
2048 * MB, /* f ==> 2048 MB */
};
/*
......@@ -152,23 +244,22 @@ static uint harrier_size_table[] __initdata = {
* memory. Assumes that the memory controller registers are already mapped
* into virtual memory--too early to use ioremap().
*/
unsigned long __init
harrier_get_mem_size(uint xcsr_base)
unsigned long __init harrier_get_mem_size(uint xcsr_base)
{
ulong last_addr;
int i;
uint vend_dev_id;
uint *size_table;
uint val;
uint *csrp;
uint size;
int size_table_entries;
ulong last_addr;
int i;
uint vend_dev_id;
uint *size_table;
uint val;
uint *csrp;
uint size;
int size_table_entries;
vend_dev_id = in_be32((uint *)xcsr_base + PCI_VENDOR_ID);
vend_dev_id = in_be32((uint *) xcsr_base + PCI_VENDOR_ID);
if (((vend_dev_id & 0xffff0000) >> 16) != PCI_VENDOR_ID_MOTOROLA) {
printk("harrier_get_mem_size: %s (0x%x)\n",
"Not a Motorola Memory Controller", vend_dev_id);
"Not a Motorola Memory Controller", vend_dev_id);
return 0;
}
......@@ -177,18 +268,17 @@ harrier_get_mem_size(uint xcsr_base)
if (vend_dev_id == PCI_DEVICE_ID_MOTOROLA_HARRIER) {
size_table = harrier_size_table;
size_table_entries = sizeof(harrier_size_table) /
sizeof(harrier_size_table[0]);
}
else {
sizeof(harrier_size_table[0]);
} else {
printk("harrier_get_mem_size: %s (0x%x)\n",
"Not a Harrier", vend_dev_id);
"Not a Harrier", vend_dev_id);
return 0;
}
last_addr = 0;
csrp = (uint *)(xcsr_base + HARRIER_SDBA_OFF);
for (i=0; i<8; i++) {
csrp = (uint *) (xcsr_base + HARRIER_SDBA_OFF);
for (i = 0; i < 8; i++) {
val = in_be32(csrp++);
if (val & 0x100) { /* If enabled */
......@@ -198,8 +288,8 @@ harrier_get_mem_size(uint xcsr_base)
break; /* Register not set correctly */
}
size = size_table[size];
val &= ~(size-1);
val &= ~(size - 1);
val += size;
if (val > last_addr) {
......
include/asm-ppc/harrier.h
View file @ bd08b0a9
/*
* include/asm-ppc/harrier.h
* arch/ppc/kernel/harrier.h
*
* Definitions for Motorola MCG Harrier North Bridge & Memory controller
*
* Author: Dale Farnsworth
* dale.farnsworth@mvista.com
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
* Modified by: Randy Vinson
* rvinson@mvista.com
*
* Copyright 2001-2002 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __ASMPPC_HARRIER_H
#define __ASMPPC_HARRIER_H
#include <linux/types.h>
#include <asm/pci-bridge.h>
#define HARRIER_VEND_DEV_ID 0x480b1057
/*
* Define outbound register offsets.
*/
#define HARRIER_OTAD0_OFF 0x220
#define HARRIER_OTOF0_OFF 0x224
#define HARRIER_OTAD1_OFF 0x228
#define HARRIER_OTOF1_OFF 0x22c
#define HARRIER_OTAD2_OFF 0x230
#define HARRIER_OTOF2_OFF 0x234
#define HARRIER_OTAD3_OFF 0x238
#define HARRIER_OTOF3_OFF 0x23c
/*
* Define inbound register offsets.
*/
#define HARRIER_ITSZ0_OFF 0x348
#define HARRIER_ITSZ1_OFF 0x350
#define HARRIER_ITSZ2_OFF 0x358
#define HARRIER_ITSZ3_OFF 0x360
/*
* Define the Memory Controller register offsets.
*/
#define HARRIER_SDBA_OFF 0x110
#define HARRIER_SDBB_OFF 0x114
#define HARRIER_SDBC_OFF 0x118
#define HARRIER_SDBD_OFF 0x11c
#define HARRIER_SDBE_OFF 0x120
#define HARRIER_SDBF_OFF 0x124
#define HARRIER_SDBG_OFF 0x128
#define HARRIER_SDBH_OFF 0x12c
#define HARRIER_SDB_ENABLE 0x00000100
#define HARRIER_SDB_SIZE_MASK 0xf
#define HARRIER_SDB_SIZE_SHIFT 16
#define HARRIER_SDB_BASE_MASK 0xff
#define HARRIER_SDB_BASE_SHIFT 24
#define HARRIER_SERIAL_0_OFF 0xc0
#define HARRIER_REVI_OFF 0x05
#define HARRIER_UCTL_OFF 0xd0
#define HARRIER_XTAL64_MASK 0x02
#define HARRIER_MISC_CSR_OFF 0x1c
#define HARRIER_RSTOUT_MASK 0x01
#define HARRIER_MBAR_OFF 0xe0
#define HARRIER_MPIC_CSR_OFF 0xe4
#define HARRIER_MPIC_OPI_ENABLE 0x40
#define HARRIER_MPIC_IFEVP_OFF 0x10200
#define HARRIER_MPIC_IFEDE_OFF 0x10210
#define HARRIER_FEEN_OFF 0x40
#define HARRIER_FEST_OFF 0x44
#define HARRIER_FEMA_OFF 0x48
#define HARRIER_FE_DMA 0x80
#define HARRIER_FE_MIDB 0x40
#define HARRIER_FE_MIM0 0x20
#define HARRIER_FE_MIM1 0x10
#define HARRIER_FE_MIP 0x08
#define HARRIER_FE_UA0 0x04
#define HARRIER_FE_UA1 0x02
#define HARRIER_FE_ABT 0x01
struct pci_controller;
int harrier_init(struct pci_controller *hose,
uint ppc_reg_base,
ulong processor_pci_mem_start,
......@@ -97,4 +36,10 @@ unsigned long harrier_get_mem_size(uint smc_base);
int harrier_mpic_init(unsigned int pci_mem_offset);
void harrier_setup_nonmonarch(uint ppc_reg_base,
uint in0_size);
void harrier_release_eready(uint ppc_reg_base);
void harrier_wait_eready(uint ppc_reg_base);
#endif /* __ASMPPC_HARRIER_H */
include/linux/harrier_defs.h 0 → 100644
View file @ bd08b0a9
/*
* asm-ppc/harrier_defs.h
*
* Definitions for Motorola MCG Harrier North Bridge & Memory controller
*
* Author: Dale Farnsworth
* dale.farnsworth@mvista.com
*
* Extracted from asm-ppc/harrier.h by:
* Randy Vinson
* rvinson@mvista.com
*
* Copyright 2001-2002 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __ASMPPC_HARRIER_DEFS_H
#define __ASMPPC_HARRIER_DEFS_H
#define HARRIER_DEFAULT_XCSR_BASE 0xfeff0000
#define HARRIER_VEND_DEV_ID 0x1057480b
#define HARRIER_VENI_OFF 0x00
#define HARRIER_REVI_OFF 0x05
#define HARRIER_UCTL_OFF 0xd0
#define HARRIER_XTAL64_MASK 0x02
#define HARRIER_MISC_CSR_OFF 0x1c
#define HARRIER_RSTOUT 0x01000000
#define HARRIER_SYSCON 0x08000000
#define HARRIER_EREADY 0x10000000
#define HARRIER_ERDYS 0x20000000
/* Function exception registers */
#define HARRIER_FEEN_OFF 0x40 /* enable */
#define HARRIER_FEST_OFF 0x44 /* status */
#define HARRIER_FEMA_OFF 0x48 /* mask */
#define HARRIER_FECL_OFF 0x4c /* clear */
#define HARRIER_FE_DMA 0x80
#define HARRIER_FE_MIDB 0x40
#define HARRIER_FE_MIM0 0x20
#define HARRIER_FE_MIM1 0x10
#define HARRIER_FE_MIP 0x08
#define HARRIER_FE_UA0 0x04
#define HARRIER_FE_UA1 0x02
#define HARRIER_FE_ABT 0x01
#define HARRIER_SERIAL_0_OFF 0xc0
#define HARRIER_MBAR_OFF 0xe0
#define HARRIER_MBAR_MSK 0xfffc0000
#define HARRIER_MPIC_CSR_OFF 0xe4
#define HARRIER_MPIC_OPI_ENABLE 0x40
#define HARRIER_MPIC_IFEVP_OFF 0x10200
#define HARRIER_MPIC_IFEVP_VECT_MSK 0xff
#define HARRIER_MPIC_IFEDE_OFF 0x10210
/*
* Define the Memory Controller register offsets.
*/
#define HARRIER_SDBA_OFF 0x110
#define HARRIER_SDBB_OFF 0x114
#define HARRIER_SDBC_OFF 0x118
#define HARRIER_SDBD_OFF 0x11c
#define HARRIER_SDBE_OFF 0x120
#define HARRIER_SDBF_OFF 0x124
#define HARRIER_SDBG_OFF 0x128
#define HARRIER_SDBH_OFF 0x12c
#define HARRIER_SDB_ENABLE 0x00000100
#define HARRIER_SDB_SIZE_MASK 0xf
#define HARRIER_SDB_SIZE_SHIFT 16
#define HARRIER_SDB_BASE_MASK 0xff
#define HARRIER_SDB_BASE_SHIFT 24
/*
* Define outbound register offsets.
*/
#define HARRIER_OTAD0_OFF 0x220
#define HARRIER_OTOF0_OFF 0x224
#define HARRIER_OTAD1_OFF 0x228
#define HARRIER_OTOF1_OFF 0x22c
#define HARRIER_OTAD2_OFF 0x230
#define HARRIER_OTOF2_OFF 0x234
#define HARRIER_OTAD3_OFF 0x238
#define HARRIER_OTOF3_OFF 0x23c
#define HARRIER_OTADX_START_MSK 0xffff0000UL
#define HARRIER_OTADX_END_MSK 0x0000ffffUL
#define HARRIER_OTOFX_OFF_MSK 0xffff0000UL
#define HARRIER_OTOFX_ENA 0x80UL
#define HARRIER_OTOFX_WPE 0x10UL
#define HARRIER_OTOFX_SGE 0x08UL
#define HARRIER_OTOFX_RAE 0x04UL
#define HARRIER_OTOFX_MEM 0x02UL
#define HARRIER_OTOFX_IOM 0x01UL
/*
* Define generic message passing register offsets
*/
/* Mirrored registers (visible from both PowerPC and PCI space) */
#define HARRIER_XCSR_MP_BASE_OFF 0x290 /* base offset in XCSR space */
#define HARRIER_PMEP_MP_BASE_OFF 0x100 /* base offset in PMEM space */
#define HARRIER_MGOM0_OFF 0x00 /* outbound msg 0 */
#define HARRIER_MGOM1_OFF 0x04 /* outbound msg 1 */
#define HARRIER_MGOD_OFF 0x08 /* outbound doorbells */
#define HARRIER_MGIM0_OFF 0x10 /* inbound msg 0 */
#define HARRIER_MGIM1_OFF 0x14 /* inbound msg 1 */
#define HARRIER_MGID_OFF 0x18 /* inbound doorbells */
/* PowerPC-only registers */
#define HARRIER_MGIDM_OFF 0x20 /* inbound doorbell mask */
/* PCI-only registers */
#define HARRIER_PMEP_MGST_OFF 0x20 /* (outbound) interrupt status */
#define HARRIER_PMEP_MGMS_OFF 0x24 /* (outbound) interrupt mask */
#define HARRIER_MG_OMI0 (1<<4)
#define HARRIER_MG_OMI1 (1<<5)
#define HARRIER_PMEP_MGODM_OFF 0x28 /* outbound doorbell mask */
/*
* Define PCI configuration space register offsets
*/
#define HARRIER_XCSR_TO_PCFS_OFF 0x300
/*
* Define message passing attribute register offset
*/
#define HARRIER_MPAT_OFF 0x44
/*
* Define inbound attribute register offsets.
*/
#define HARRIER_ITSZ0_OFF 0x48
#define HARRIER_ITAT0_OFF 0x4c
#define HARRIER_ITSZ1_OFF 0x50
#define HARRIER_ITAT1_OFF 0x54
#define HARRIER_ITSZ2_OFF 0x58
#define HARRIER_ITAT2_OFF 0x5c
#define HARRIER_ITSZ3_OFF 0x60
#define HARRIER_ITAT3_OFF 0x64
/* inbound translation size constants */
#define HARRIER_ITSZ_MSK 0xff
#define HARRIER_ITSZ_4KB 0x00
#define HARRIER_ITSZ_8KB 0x01
#define HARRIER_ITSZ_16KB 0x02
#define HARRIER_ITSZ_32KB 0x03
#define HARRIER_ITSZ_64KB 0x04
#define HARRIER_ITSZ_128KB 0x05
#define HARRIER_ITSZ_256KB 0x06
#define HARRIER_ITSZ_512KB 0x07
#define HARRIER_ITSZ_1MB 0x08
#define HARRIER_ITSZ_2MB 0x09
#define HARRIER_ITSZ_4MB 0x0A
#define HARRIER_ITSZ_8MB 0x0B
#define HARRIER_ITSZ_16MB 0x0C
#define HARRIER_ITSZ_32MB 0x0D
#define HARRIER_ITSZ_64MB 0x0E
#define HARRIER_ITSZ_128MB 0x0F
#define HARRIER_ITSZ_256MB 0x10
#define HARRIER_ITSZ_512MB 0x11
#define HARRIER_ITSZ_1GB 0x12
#define HARRIER_ITSZ_2GB 0x13
/* inbound translation offset */
#define HARRIER_ITOF_SHIFT 0x10
#define HARRIER_ITOF_MSK 0xffff
/* inbound translation atttributes */
#define HARRIER_ITAT_PRE (1<<3)
#define HARRIER_ITAT_RAE (1<<4)
#define HARRIER_ITAT_WPE (1<<5)
#define HARRIER_ITAT_MEM (1<<6)
#define HARRIER_ITAT_ENA (1<<7)
#define HARRIER_ITAT_GBL (1<<16)
#define HARRIER_LBA_OFF 0x80
#define HARRIER_LBA_MSK (1<<31)
#define HARRIER_XCSR_SIZE 1024
/* macros to calculate message passing register offsets */
#define HARRIER_MP_XCSR(x) ((u32)HARRIER_XCSR_MP_BASE_OFF + (u32)x)
#define HARRIER_MP_PMEP(x) ((u32)HARRIER_PMEP_MP_BASE_OFF + (u32)x)
/*
* Define PCI configuration space register offsets
*/
#define HARRIER_MPBAR_OFF PCI_BASE_ADDRESS_0
#define HARRIER_ITBAR0_OFF PCI_BASE_ADDRESS_1
#define HARRIER_ITBAR1_OFF PCI_BASE_ADDRESS_2
#define HARRIER_ITBAR2_OFF PCI_BASE_ADDRESS_3
#define HARRIER_ITBAR3_OFF PCI_BASE_ADDRESS_4
#define HARRIER_XCSR_CONFIG(x) ((u32)HARRIER_XCSR_TO_PCFS_OFF + (u32)x)
#endif /* __ASMPPC_HARRIER_DEFS_H */
include/linux/pci_ids.h
View file @ bd08b0a9
......@@ -759,6 +759,7 @@
#define PCI_DEVICE_ID_MOTOROLA_FALCON 0x4802
#define PCI_DEVICE_ID_MOTOROLA_HAWK 0x4803
#define PCI_DEVICE_ID_MOTOROLA_CPX8216 0x4806
#define PCI_DEVICE_ID_MOTOROLA_HARRIER 0x480b
#define PCI_VENDOR_ID_PROMISE 0x105a
#define PCI_DEVICE_ID_PROMISE_20265 0x0d30
......
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