Commit c0a7c002 authored by Jan Kotas's avatar Jan Kotas Committed by Mauro Carvalho Chehab

media: dt-bindings: Update bindings for Cadence CSI2TX version 2.1

This patch adds a DT bindings documentation for
Cadence CSI2TX v2.1 controller.
Signed-off-by: default avatarJan Kotas <jank@cadence.com>
Acked-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: default avatarSakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+samsung@kernel.org>
parent 24c8ac89
...@@ -5,7 +5,8 @@ The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to ...@@ -5,7 +5,8 @@ The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
4 CSI lanes in output, and up to 4 different pixel streams in input. 4 CSI lanes in output, and up to 4 different pixel streams in input.
Required properties: Required properties:
- compatible: must be set to "cdns,csi2tx" - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3"
for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1
- reg: base address and size of the memory mapped region - reg: base address and size of the memory mapped region
- clocks: phandles to the clocks driving the controller - clocks: phandles to the clocks driving the controller
- clock-names: must contain: - clock-names: must contain:
......
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