drm/amd/display: Calculate link bandwidth in a common function

[why]
Currently link bandwidth is calculated in various places using the same
multi-step formula. Doing this in one common place makes sure the same
formula will indeed be applied to all link bandwidth calculations.
It also makes it possible to apply link-setting-specific adjustments
that affect effective link bandwidth.

[how]
Replace all implementations of link bandwidth calculation with a call
to a function.
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/core/dc_link.c

@@ -2390,11 +2390,6 @@ static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
 			&stream->link->cur_link_settings);
 	link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
 
-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
-	if (stream->link->fec_state != dc_link_fec_not_ready)
-		link_rate_in_mbytes_per_sec = (link_rate_in_mbytes_per_sec * 970)/1000;
-#endif
-
 	mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
 
 	return dc_fixpt_div_int(mbytes_per_sec, 54);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c

@@ -225,6 +225,7 @@ static void dsc2_disable(struct display_stream_compressor *dsc)
 static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps)
 {
 	int i;
+	int bits_per_pixel = pps->bits_per_pixel;
 
 	DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):");
 	DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major);
@@ -235,7 +236,7 @@ static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_co
 	DC_LOG_DSC("\tconvert_rgb %d", pps->convert_rgb);
 	DC_LOG_DSC("\tsimple_422 %d", pps->simple_422);
 	DC_LOG_DSC("\tvbr_enable %d", pps->vbr_enable);
-	DC_LOG_DSC("\tbits_per_pixel %d", pps->bits_per_pixel);
+	DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", bits_per_pixel, bits_per_pixel / 16, ((bits_per_pixel % 16) * 10000) / 16);
 	DC_LOG_DSC("\tpic_height %d", pps->pic_height);
 	DC_LOG_DSC("\tpic_width %d", pps->pic_width);
 	DC_LOG_DSC("\tslice_height %d", pps->slice_height);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

@@ -849,15 +849,11 @@ bool dc_check_and_fit_timing_into_bandwidth_with_dsc_legacy(
 {
 	int requiredBandwidth_Kbps;
 	bool stream_fits_into_bandwidth = false;
-	int link_rate_kbytes_per_sec = link->verified_link_cap.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
-	int total_link_bandwdith_kbps = link->verified_link_cap.lane_count * link_rate_kbytes_per_sec * 8;
-
-	if (link->preferred_link_setting.lane_count !=
-			LANE_COUNT_UNKNOWN &&
-			link->preferred_link_setting.link_rate !=
-					LINK_RATE_UNKNOWN) {
-		link_rate_kbytes_per_sec =  link->preferred_link_setting.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
-		total_link_bandwdith_kbps =  link->preferred_link_setting.lane_count * link_rate_kbytes_per_sec * 8;
+	int total_link_bandwdith_kbps = dc_link_bandwidth_kbps(link, &link->verified_link_cap);
+
+	if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
+			link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) {
+		total_link_bandwdith_kbps = dc_link_bandwidth_kbps(link, &link->preferred_link_setting);
 	}
 
 	timing->flags.DSC = 0;