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Commit c354f77b authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'uniphier-dt-v5.7' of... 

Merge tag 'uniphier-dt-v5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into arm/dt

UniPhier ARM SoC DT updates for v5.7

- Rename nodes to avoid dt-schema warnings

- Add a generic compatible to EEPROM so that it matches OF table

- Add USB controller nodes to Pro5 SoC

- Fix clock and reset of SPI nodes

* tag 'uniphier-dt-v5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier:
  ARM: dts: uniphier: Set SCSSI clock and reset IDs for each channel
  ARM: dts: uniphier: Add USB3 controller nodes for Pro5
  ARM: dts: uniphier: Add one more generic compatible string for I2C EEPROM
  ARM: dts: uniphier: rename cache controller nodes to follow json-schema
  ARM: dts: uniphier: rename NAND node names to follow json-schema
  ARM: dts: uniphier: rename aidet node names to follow json-schema
  ARM: dts: uniphier: change SD/eMMC node names to follow json-schema

Link: https://lore.kernel.org/r/CAK7LNAQ-AOTyqpV1E_S-hksjqexHfVauwGV9rrfDvjRVnu8-UQ@mail.gmail.comSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 80e7f21d d1876a0b
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arch/arm/boot/dts/uniphier-ld4.dtsi
View file @ c354f77b
......@@ -51,7 +51,7 @@ soc {
ranges;
interrupt-parent = <&intc>;
l2: l2-cache@500c0000 {
l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
......@@ -245,7 +245,7 @@ dmac: dma-controller@5a000000 {
#dma-cells = <1>;
};
sd: sdhc@5a400000 {
sd: mmc@5a400000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a400000 0x200>;
......@@ -265,7 +265,7 @@ sd: sdhc@5a400000 {
sd-uhs-sdr50;
};
emmc: sdhc@5a500000 {
emmc: mmc@5a500000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a500000 0x200>;
......@@ -375,7 +375,7 @@ intc: interrupt-controller@60001000 {
interrupt-controller;
};
aidet: aidet@61830000 {
aidet: interrupt-controller@61830000 {
compatible = "socionext,uniphier-ld4-aidet";
reg = <0x61830000 0x200>;
interrupt-controller;
......@@ -398,7 +398,7 @@ sys_rst: reset {
};
};
nand: nand@68000000 {
nand: nand-controller@68000000 {
compatible = "socionext,uniphier-denali-nand-v5a";
status = "disabled";
reg-names = "nand_data", "denali_reg";
......
arch/arm/boot/dts/uniphier-pro4.dtsi
View file @ c354f77b
......@@ -59,7 +59,7 @@ soc {
ranges;
interrupt-parent = <&intc>;
l2: l2-cache@500c0000 {
l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
......@@ -279,7 +279,7 @@ dmac: dma-controller@5a000000 {
#dma-cells = <1>;
};
sd: sdhc@5a400000 {
sd: mmc@5a400000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a400000 0x200>;
......@@ -299,7 +299,7 @@ sd: sdhc@5a400000 {
sd-uhs-sdr50;
};
emmc: sdhc@5a500000 {
emmc: mmc@5a500000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a500000 0x200>;
......@@ -317,7 +317,7 @@ emmc: sdhc@5a500000 {
non-removable;
};
sd1: sdhc@5a600000 {
sd1: mmc@5a600000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a600000 0x200>;
......@@ -426,7 +426,7 @@ efuse@200 {
};
};
aidet: aidet@5fc20000 {
aidet: interrupt-controller@5fc20000 {
compatible = "socionext,uniphier-pro4-aidet";
reg = <0x5fc20000 0x200>;
interrupt-controller;
......@@ -588,7 +588,7 @@ usb1_rst: reset@40 {
};
};
nand: nand@68000000 {
nand: nand-controller@68000000 {
compatible = "socionext,uniphier-denali-nand-v5a";
status = "disabled";
reg-names = "nand_data", "denali_reg";
......
arch/arm/boot/dts/uniphier-pro5.dtsi
View file @ c354f77b
......@@ -131,7 +131,7 @@ soc {
ranges;
interrupt-parent = <&intc>;
l2: l2-cache@500c0000 {
l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
<0x506c0000 0x400>;
......@@ -144,7 +144,7 @@ l2: l2-cache@500c0000 {
next-level-cache = <&l3>;
};
l3: l3-cache@500c8000 {
l3: cache-controller@500c8000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
<0x506c8000 0x400>;
......@@ -174,8 +174,8 @@ spi1: spi@54006100 {
interrupts = <0 216 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
clocks = <&peri_clk 11>;
resets = <&peri_rst 11>;
clocks = <&peri_clk 11>; /* common with spi0 */
resets = <&peri_rst 12>;
};
serial0: serial@54006800 {
......@@ -408,7 +408,7 @@ efuse@400 {
};
};
aidet: aidet@5fc20000 {
aidet: interrupt-controller@5fc20000 {
compatible = "socionext,uniphier-pro5-aidet";
reg = <0x5fc20000 0x200>;
interrupt-controller;
......@@ -453,7 +453,155 @@ sys_rst: reset {
};
};
nand: nand@68000000 {
usb0: usb@65a00000 {
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
status = "disabled";
reg = <0x65a00000 0xcd00>;
interrupt-names = "host";
interrupts = <0 134 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clock-names = "ref", "bus_early", "suspend";
clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
resets = <&usb0_rst 15>;
phys = <&usb0_hsphy0>, <&usb0_ssphy0>;
dr_mode = "host";
};
usb-glue@65b00000 {
compatible = "socionext,uniphier-pro5-dwc3-glue",
"simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65b00000 0x400>;
usb0_rst: reset@0 {
compatible = "socionext,uniphier-pro5-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 14>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 14>;
};
usb0_vbus0: regulator@100 {
compatible = "socionext,uniphier-pro5-usb3-regulator";
reg = <0x100 0x10>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 14>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 14>;
};
usb0_hsphy0: hs-phy@280 {
compatible = "socionext,uniphier-pro5-usb3-hsphy";
reg = <0x280 0x10>;
#phy-cells = <0>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 14>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 14>;
vbus-supply = <&usb0_vbus0>;
};
usb0_ssphy0: ss-phy@380 {
compatible = "socionext,uniphier-pro5-usb3-ssphy";
reg = <0x380 0x10>;
#phy-cells = <0>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 14>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 14>;
vbus-supply = <&usb0_vbus0>;
};
};
usb1: usb@65c00000 {
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
status = "disabled";
reg = <0x65c00000 0xcd00>;
interrupt-names = "host";
interrupts = <0 137 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
clock-names = "ref", "bus_early", "suspend";
clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
resets = <&usb1_rst 15>;
phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>;
dr_mode = "host";
};
usb-glue@65d00000 {
compatible = "socionext,uniphier-pro5-dwc3-glue",
"simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65d00000 0x400>;
usb1_rst: reset@0 {
compatible = "socionext,uniphier-pro5-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 15>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 15>;
};
usb1_vbus0: regulator@100 {
compatible = "socionext,uniphier-pro5-usb3-regulator";
reg = <0x100 0x10>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 15>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 15>;
};
usb1_vbus1: regulator@110 {
compatible = "socionext,uniphier-pro5-usb3-regulator";
reg = <0x110 0x10>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 15>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 15>;
};
usb1_hsphy0: hs-phy@280 {
compatible = "socionext,uniphier-pro5-usb3-hsphy";
reg = <0x280 0x10>;
#phy-cells = <0>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 15>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 15>;
vbus-supply = <&usb1_vbus0>;
};
usb1_hsphy1: hs-phy@290 {
compatible = "socionext,uniphier-pro5-usb3-hsphy";
reg = <0x290 0x10>;
#phy-cells = <0>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 15>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 15>;
vbus-supply = <&usb1_vbus1>;
};
usb1_ssphy0: ss-phy@380 {
compatible = "socionext,uniphier-pro5-usb3-ssphy";
reg = <0x380 0x10>;
#phy-cells = <0>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 15>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 15>;
vbus-supply = <&usb1_vbus0>;
};
};
nand: nand-controller@68000000 {
compatible = "socionext,uniphier-denali-nand-v5b";
status = "disabled";
reg-names = "nand_data", "denali_reg";
......@@ -469,7 +617,7 @@ nand: nand@68000000 {
resets = <&sys_rst 2>, <&sys_rst 2>;
};
emmc: sdhc@68400000 {
emmc: mmc@68400000 {
compatible = "socionext,uniphier-sd-v3.1";
status = "disabled";
reg = <0x68400000 0x800>;
......@@ -485,7 +633,7 @@ emmc: sdhc@68400000 {
non-removable;
};
sd: sdhc@68800000 {
sd: mmc@68800000 {
compatible = "socionext,uniphier-sd-v3.1";
status = "disabled";
reg = <0x68800000 0x800>;
......
arch/arm/boot/dts/uniphier-pxs2.dtsi
View file @ c354f77b
......@@ -157,7 +157,7 @@ soc {
ranges;
interrupt-parent = <&intc>;
l2: l2-cache@500c0000 {
l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
<0x506c0000 0x400>;
......@@ -187,8 +187,8 @@ spi1: spi@54006100 {
interrupts = <0 216 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
clocks = <&peri_clk 11>;
resets = <&peri_rst 11>;
clocks = <&peri_clk 12>;
resets = <&peri_rst 12>;
};
serial0: serial@54006800 {
......@@ -446,7 +446,7 @@ peri_rst: reset {
};
};
emmc: sdhc@5a000000 {
emmc: mmc@5a000000 {
compatible = "socionext,uniphier-sd-v3.1.1";
status = "disabled";
reg = <0x5a000000 0x800>;
......@@ -462,7 +462,7 @@ emmc: sdhc@5a000000 {
non-removable;
};
sd: sdhc@5a400000 {
sd: mmc@5a400000 {
compatible = "socionext,uniphier-sd-v3.1.1";
status = "disabled";
reg = <0x5a400000 0x800>;
......@@ -508,7 +508,7 @@ efuse@200 {
};
};
aidet: aidet@5fc20000 {
aidet: interrupt-controller@5fc20000 {
compatible = "socionext,uniphier-pxs2-aidet";
reg = <0x5fc20000 0x200>;
interrupt-controller;
......@@ -761,7 +761,7 @@ usb1_ssphy0: ss-phy@300 {
};
};
nand: nand@68000000 {
nand: nand-controller@68000000 {
compatible = "socionext,uniphier-denali-nand-v5b";
status = "disabled";
reg-names = "nand_data", "denali_reg";
......
arch/arm/boot/dts/uniphier-ref-daughter.dtsi
View file @ c354f77b
......@@ -7,7 +7,7 @@
&i2c0 {
eeprom@50 {
compatible = "microchip,24lc128";
compatible = "microchip,24lc128", "atmel,24c128";
reg = <0x50>;
pagesize = <64>;
};
......
arch/arm/boot/dts/uniphier-sld8.dtsi
View file @ c354f77b
......@@ -51,7 +51,7 @@ soc {
ranges;
interrupt-parent = <&intc>;
l2: l2-cache@500c0000 {
l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
......@@ -249,7 +249,7 @@ dmac: dma-controller@5a000000 {
#dma-cells = <1>;
};
sd: sdhc@5a400000 {
sd: mmc@5a400000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a400000 0x200>;
......@@ -269,7 +269,7 @@ sd: sdhc@5a400000 {
sd-uhs-sdr50;
};
emmc: sdhc@5a500000 {
emmc: mmc@5a500000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a500000 0x200>;
......@@ -379,7 +379,7 @@ intc: interrupt-controller@60001000 {
interrupt-controller;
};
aidet: aidet@61830000 {
aidet: interrupt-controller@61830000 {
compatible = "socionext,uniphier-sld8-aidet";
reg = <0x61830000 0x200>;
interrupt-controller;
......@@ -402,7 +402,7 @@ sys_rst: reset {
};
};
nand: nand@68000000 {
nand: nand-controller@68000000 {
compatible = "socionext,uniphier-denali-nand-v5a";
status = "disabled";
reg-names = "nand_data", "denali_reg";
......
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