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Commit c5fc2498 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC cleanups from Olof Johansson:
 "A large cleanup branch this release, with a healthy 10k negative line
  delta.

  Most of this is removal of legacy (non-DT) support of shmobile
  platforms.  There is also removal of two non-DT platforms on OMAP, and
  the plat-samsung directory is cleaned out by moving most of the
  previously shared-location-but-not-actually-shared files from there to
  the appropriate mach directories instead.

  There are other sets of changes in here as well:

   - Rob Herring removed use of set_irq_flags under all platforms and
     moved to genirq alternatives

   - a series of timer API conversions to set-state interface

   - ep93xx, nomadik and ux500 cleanups from Linus Walleij

   - __init annotation fixes from Nicolas Pitre

   + a bunch of other changes that all add up to a nice set of cleanups"

* tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (108 commits)
  ARM/fb: ep93xx: switch framebuffer to use modedb only
  ARM: gemini: Setup timer3 as free running timer
  ARM: gemini: Use timer1 for clockevent
  ARM: gemini: Add missing register definitions for gemini timer
  ARM: ep93xx/timer: Migrate to new 'set-state' interface
  ARM: nomadik: push accelerometer down to boards
  ARM: nomadik: move l2x0 setup to device tree
  ARM: nomadik: selectively enable UART0 on boards
  ARM: nomadik: move hog code to use DT hogs
  ARM: shmobile: Fix mismerges
  ARM: ux500: simplify secondary CPU boot
  ARM: SAMSUNG: remove keypad-core header in plat-samsung
  ARM: SAMSUNG: local watchdog-reset header in mach-s3c64xx
  ARM: SAMSUNG: local onenand-core header in mach-s3c64xx
  ARM: SAMSUNG: local irq-uart header in mach-s3c64xx
  ARM: SAMSUNG: local backlight header in mach-s3c64xx
  ARM: SAMSUNG: local ata-core header in mach-s3c64xx
  ARM: SAMSUNG: local regs-usb-hsotg-phy header in mach-s3c64xx
  ARM: SAMSUNG: local spi-core header in mach-s3c24xx
  ARM: SAMSUNG: local nand-core header in mach-s3c24xx
  ...
parents 00e3fcc2 97a2482d
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Showing with 1281 additions and 10483 deletions
Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.txt
View file @ c5fc2498
......@@ -8,10 +8,10 @@ Required properties:
- interrupts : The interrupt from the HDA controller.
- clocks : Must contain an entry for each required entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names : Must include the following entries: hda, hdacodec_2x, hda2hdmi
- clock-names : Must include the following entries: hda, hda2hdmi, hda2codec_2x
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names : Must include the following entries: hda, hdacodec_2x, hda2hdmi
- reset-names : Must include the following entries: hda, hda2hdmi, hda2codec_2x
Example:
......@@ -24,7 +24,7 @@ hda@0,70030000 {
<&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
clock-names = "hda", "hda2hdmi", "hda2codec_2x";
resets = <&tegra_car 125>, /* hda */
<&tegra_car 128>; /* hda2hdmi */
<&tegra_car 111>, /* hda2codec_2x */
<&tegra_car 128>, /* hda2hdmi */
<&tegra_car 111>; /* hda2codec_2x */
reset-names = "hda", "hda2hdmi", "hda2codec_2x";
};
MAINTAINERS
View file @ c5fc2498
......@@ -1471,9 +1471,7 @@ F: arch/arm/boot/dts/emev2*
F: arch/arm/boot/dts/r7s*
F: arch/arm/boot/dts/r8a*
F: arch/arm/boot/dts/sh*
F: arch/arm/configs/armadillo800eva_defconfig
F: arch/arm/configs/bockw_defconfig
F: arch/arm/configs/kzm9g_defconfig
F: arch/arm/configs/marzen_defconfig
F: arch/arm/configs/shmobile_defconfig
F: arch/arm/include/debug/renesas-scif.S
......
arch/arm/Kconfig
View file @ c5fc2498
......@@ -268,7 +268,6 @@ config PHYS_OFFSET
depends on !ARM_PATCH_PHYS_VIRT
default DRAM_BASE if !MMU
default 0x00000000 if ARCH_EBSA110 || \
EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
ARCH_FOOTBRIDGE || \
ARCH_INTEGRATOR || \
ARCH_IOP13XX || \
......@@ -277,10 +276,7 @@ config PHYS_OFFSET
default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
default 0x20000000 if ARCH_S5PV210
default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
default 0xc0000000 if ARCH_SA1100
help
Please provide the physical address corresponding to the
location of main memory in your system.
......@@ -418,11 +414,14 @@ config ARCH_EP93XX
bool "EP93xx-based"
select ARCH_HAS_HOLES_MEMORYMODEL
select ARCH_REQUIRE_GPIOLIB
select ARCH_USES_GETTIMEOFFSET
select ARM_AMBA
select ARM_PATCH_PHYS_VIRT
select ARM_VIC
select AUTO_ZRELADDR
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select CPU_ARM920T
select GENERIC_CLOCKEVENTS
help
This enables support for the Cirrus EP93xx series of CPUs.
......
arch/arm/boot/compressed/Makefile
View file @ c5fc2498
......@@ -51,10 +51,6 @@ else
endif
endif
ifeq ($(CONFIG_ARCH_SHMOBILE_LEGACY),y)
OBJS += head-shmobile.o
endif
#
# We now have a PIC decompressor implementation. Decompressors running
# from RAM should not define ZTEXTADDR. Decompressors running directly
......
arch/arm/boot/compressed/head-shmobile.S deleted 100644 → 0
View file @ 00e3fcc2
/*
* The head-file for SH-Mobile ARM platforms
*
* Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
* Simon Horman <horms@verge.net.au>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifdef CONFIG_ZBOOT_ROM
.section ".start", "ax"
/* load board-specific initialization code */
#include <mach/zboot.h>
adr r0, dtb_info
ldmia r0, {r1, r3, r4, r5, r7}
sub r0, r0, r1 @ calculate the delta offset
add r5, r5, r0 @ _edata
ldr lr, [r5, #0] @ check if valid DTB is present
cmp lr, r3
bne 0f
add r9, r7, #31 @ rounded up to a multiple
bic r9, r9, #31 @ ... of 32 bytes
add r6, r9, r5 @ copy from _edata
add r9, r9, r4 @ to MEMORY_START
1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
cmp r6, r5
stmdb r9!, {r0 - r3, r10 - r12, lr}
bhi 1b
/* Success: Zero board ID, pointer to start of memory for atag/dtb */
mov r7, #0
mov r8, r4
b 2f
.align 2
dtb_info:
.word dtb_info
#ifndef __ARMEB__
.word 0xedfe0dd0 @ sig is 0xd00dfeed big endian
#else
.word 0xd00dfeed
#endif
.word MEMORY_START
.word _edata
.word 0x4000 @ maximum DTB size
0:
/* Failure: Zero board ID, NULL atag/dtb */
mov r7, #0
mov r8, #0 @ pass null pointer as atag
2 :
#endif /* CONFIG_ZBOOT_ROM */
arch/arm/boot/dts/Makefile
View file @ c5fc2498
......@@ -501,11 +501,8 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
s5pv210-smdkv210.dtb \
s5pv210-torbreck.dtb
dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \
r8a7740-armadillo800eva.dtb \
r8a7778-bockw.dtb \
r8a7778-bockw-reference.dtb \
r8a7779-marzen.dtb \
sh73a0-kzm9g.dtb
r8a7778-bockw-reference.dtb
dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
emev2-kzm9d.dtb \
r7s72100-genmai.dtb \
......
arch/arm/boot/dts/ste-nomadik-nhk15.dts
View file @ c5fc2498
......@@ -17,12 +17,22 @@ chosen {
};
aliases {
serial0 = &uart0;
serial1 = &uart1;
stmpe-i2c0 = &stmpe0;
stmpe-i2c1 = &stmpe1;
};
pinctrl {
uart0 {
uart0_nhk_mode: uart0_mux {
u0_default_mux {
function = "u0";
groups = "u0txrx_a_1", "u0ctsrts_a_1";
};
};
};
stmpe2401_1 {
stmpe2401_1_nhk_mode: stmpe2401_1_nhk {
nhk_cfg1 {
......@@ -73,6 +83,11 @@ ethernet@300 {
};
i2c0 {
lis3lv02dl@1d {
/* Accelerometer */
compatible = "st,lis3lv02dl-accel";
reg = <0x1d>;
};
stmpe0: stmpe2401@43 {
compatible = "st,stmpe2401";
reg = <0x43>;
......@@ -131,22 +146,30 @@ stmpe_gpio44: stmpe_gpio {
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
/*
* This will turn off SATA so that MMC/SD
* can thrive
*/
mmcsd-gpio {
gpio-hog;
gpios = <2 0x0>;
output-low;
line-name = "SATA EN";
};
};
};
};
amba {
/* Activate RX/TX and CTS/RTS on UART 0 */
uart0: uart@101fd000 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_nhk_mode>;
status = "okay";
};
mmcsd: sdi@101f6000 {
cd-gpios = <&stmpe_gpio44 7 GPIO_ACTIVE_LOW>;
wp-gpios = <&stmpe_gpio44 18 GPIO_ACTIVE_HIGH>;
};
};
/* Custom board node with GPIO pins to active etc */
usb-s8815 {
/* This will turn off SATA so that MMC/SD can thrive */
mmcsd-gpio {
gpios = <&stmpe_gpio44 2 0x1>;
};
};
};
arch/arm/boot/dts/ste-nomadik-s8815.dts
View file @ c5fc2498
......@@ -16,9 +16,20 @@ chosen {
};
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
gpio3: gpio@101e7000 {
/* This hog will bias the MMC/SD card detect line */
mmcsd-gpio {
gpio-hog;
gpios = <16 0x0>;
output-low;
line-name = "card detect bias";
};
};
src@101e0000 {
/* These chrystal drivers are not used on this board */
disable-sxtalo;
......@@ -30,6 +41,15 @@ pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&cd_default_mode>;
uart0 {
/* Only use RX/TX pins */
uart0_s8815_mode: uart0_mux {
u0_default_mux {
function = "u0";
groups = "u0txrx_a_1";
};
};
};
mmcsd-cd {
cd_default_mode: cd_default {
cd_default_cfg1 {
......@@ -85,6 +105,14 @@ ethernet@300 {
};
};
i2c1 {
lis3lv02dl@1d {
/* Accelerometer */
compatible = "st,lis3lv02dl-accel";
reg = <0x1d>;
};
};
/* GPIO I2C connected to the USB portions of the STw4811 only */
gpio-i2c {
compatible = "i2c-gpio";
......@@ -102,21 +130,19 @@ stw4811@2d {
};
/* Configure card detect for the uSD slot */
amba {
/* Activate RXTX on UART 0 */
uart0: uart@101fd000 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_s8815_mode>;
status = "okay";
};
/* Configure card detect for the uSD slot */
mmcsd: sdi@101f6000 {
cd-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
};
};
/* Custom board node with GPIO pins to active etc */
usb-s8815 {
/* This will bias the MMC/SD card detect line */
mmcsd-gpio {
gpios = <&gpio3 16 0x1>;
};
};
/* The user LED on the board is set up to be used for heartbeat */
leds {
compatible = "gpio-leds";
......
arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
View file @ c5fc2498
......@@ -21,6 +21,13 @@ L2: l2-cache {
interrupts = <30>;
cache-unified;
cache-level = <2>;
cache-size = <131072>;
cache-sets = <512>;
cache-line-size = <32>;
/* At full speed latency must be >=2 */
arm,tag-latency = <2>;
arm,data-latency = <2 2>;
arm,dirty-latency = <2>;
};
mtu0: mtu@101e2000 {
......@@ -97,14 +104,6 @@ gpio3: gpio@101e7000 {
pinctrl {
compatible = "stericsson,stn8815-pinctrl";
/* Pin configurations */
uart0 {
uart0_default_mux: uart0_mux {
u0_default_mux {
function = "u0";
groups = "u0_a_1";
};
};
};
uart1 {
uart1_default_mux: uart1_mux {
u1_default_mux {
......@@ -721,11 +720,6 @@ stw5095@1a {
compatible = "st,stw5095";
reg = <0x1a>;
};
lis3lv02dl@1d {
/* Accelerometer */
compatible = "st,lis3lv02dl-accel";
reg = <0x1d>;
};
};
amba {
......@@ -755,8 +749,6 @@ uart0: uart@101fd000 {
interrupts = <12>;
clocks = <&uart0clk>, <&pclkuart0>;
clock-names = "uartclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart0_default_mux>;
status = "disabled";
};
......
arch/arm/common/it8152.c
View file @ c5fc2498
......@@ -91,7 +91,7 @@ void it8152_init_irq(void)
for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) {
irq_set_chip_and_handler(irq, &it8152_irq_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
}
}
......
arch/arm/common/locomo.c
View file @ c5fc2498
......@@ -138,9 +138,9 @@ static struct locomo_dev_info locomo_devices[] = {
},
};
static void locomo_handler(unsigned int irq, struct irq_desc *desc)
static void locomo_handler(unsigned int __irq, struct irq_desc *desc)
{
struct locomo *lchip = irq_get_chip_data(irq);
struct locomo *lchip = irq_desc_get_chip_data(desc);
int req, i;
/* Acknowledge the parent IRQ */
......@@ -150,6 +150,8 @@ static void locomo_handler(unsigned int irq, struct irq_desc *desc)
req = locomo_readl(lchip->base + LOCOMO_ICR) & 0x0f00;
if (req) {
unsigned int irq;
/* generate the next interrupt(s) */
irq = lchip->irq_base;
for (i = 0; i <= 3; i++, irq++) {
......@@ -205,7 +207,7 @@ static void locomo_setup_irq(struct locomo *lchip)
for ( ; irq <= lchip->irq_base + 3; irq++) {
irq_set_chip_and_handler(irq, &locomo_chip, handle_level_irq);
irq_set_chip_data(irq, lchip);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
}
}
......@@ -475,8 +477,7 @@ static void __locomo_remove(struct locomo *lchip)
device_for_each_child(lchip->dev, NULL, locomo_remove_child);
if (lchip->irq != NO_IRQ) {
irq_set_chained_handler(lchip->irq, NULL);
irq_set_handler_data(lchip->irq, NULL);
irq_set_chained_handler_and_data(lchip->irq, NULL, NULL);
}
iounmap(lchip->base);
......
arch/arm/common/sa1111.c
View file @ c5fc2498
......@@ -197,10 +197,11 @@ static struct sa1111_dev_info sa1111_devices[] = {
* will call us again if there are more interrupts to process.
*/
static void
sa1111_irq_handler(unsigned int irq, struct irq_desc *desc)
sa1111_irq_handler(unsigned int __irq, struct irq_desc *desc)
{
unsigned int irq = irq_desc_get_irq(desc);
unsigned int stat0, stat1, i;
struct sa1111 *sachip = irq_get_handler_data(irq);
struct sa1111 *sachip = irq_desc_get_handler_data(desc);
void __iomem *mapbase = sachip->base + SA1111_INTC;
stat0 = sa1111_readl(mapbase + SA1111_INTSTATCLR0);
......@@ -486,7 +487,7 @@ static int sa1111_setup_irq(struct sa1111 *sachip, unsigned irq_base)
irq_set_chip_and_handler(irq, &sa1111_low_chip,
handle_edge_irq);
irq_set_chip_data(irq, sachip);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
}
for (i = AUDXMTDMADONEA; i <= IRQ_S1_BVD1_STSCHG; i++) {
......@@ -494,7 +495,7 @@ static int sa1111_setup_irq(struct sa1111 *sachip, unsigned irq_base)
irq_set_chip_and_handler(irq, &sa1111_high_chip,
handle_edge_irq);
irq_set_chip_data(irq, sachip);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
}
/*
......
arch/arm/configs/armadillo800eva_defconfig deleted 100644 → 0
View file @ 00e3fcc2
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=16
# CONFIG_UTS_NS is not set
# CONFIG_IPC_NS is not set
# CONFIG_PID_NS is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_PERF_EVENTS=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_SHMOBILE_LEGACY=y
CONFIG_ARCH_R8A7740=y
CONFIG_MACH_ARMADILLO800EVA=y
# CONFIG_SH_TIMER_TMU is not set
CONFIG_ARM_THUMB=y
CONFIG_CACHE_L2X0=y
CONFIG_ARM_ERRATA_430973=y
CONFIG_ARM_ERRATA_458693=y
CONFIG_ARM_ERRATA_460075=y
CONFIG_PL310_ERRATA_588369=y
CONFIG_ARM_ERRATA_720789=y
CONFIG_PL310_ERRATA_727915=y
CONFIG_ARM_ERRATA_743622=y
CONFIG_ARM_ERRATA_751472=y
CONFIG_PL310_ERRATA_753970=y
CONFIG_ARM_ERRATA_754322=y
CONFIG_PL310_ERRATA_769419=y
CONFIG_ARM_ERRATA_775420=y
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_FORCE_MAX_ZONEORDER=13
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_KEXEC=y
CONFIG_VFP=y
CONFIG_NEON=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_PM=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_MD=y
CONFIG_BLK_DEV_DM=y
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_CIRRUS is not set
# CONFIG_NET_VENDOR_FARADAY is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
CONFIG_SH_ETH=y
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_WLAN is not set
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ST1232=y
# CONFIG_SERIO is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_SH_SCI=y
CONFIG_SERIAL_SH_SCI_NR_UARTS=9
CONFIG_SERIAL_SH_SCI_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_GPIO=y
CONFIG_I2C_SH_MOBILE=y
# CONFIG_HWMON is not set
CONFIG_REGULATOR=y
CONFIG_REGULATOR_GPIO=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_VIDEO_DEV=y
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_SOC_CAMERA=y
CONFIG_SOC_CAMERA_MT9T112=y
CONFIG_VIDEO_SH_MOBILE_CEU=y
CONFIG_FB=y
CONFIG_FB_SH_MOBILE_LCDC=y
CONFIG_FB_SH_MOBILE_HDMI=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_BACKLIGHT_PWM=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_SND_SUPPORT_OLD_API is not set
# CONFIG_SND_VERBOSE_PROCFS is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_ARM is not set
CONFIG_SND_SOC_SH4_FSI=y
# CONFIG_HID_SUPPORT is not set
CONFIG_USB=y
CONFIG_USB_RENESAS_USBHS=y
CONFIG_USB_GADGET=y
CONFIG_USB_RENESAS_USBHS_UDC=y
CONFIG_USB_ETH=m
CONFIG_MMC=y
CONFIG_MMC_SDHI=y
CONFIG_MMC_SH_MMCIF=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_S35390A=y
CONFIG_DMADEVICES=y
CONFIG_SH_DMAE=y
CONFIG_UIO=y
CONFIG_UIO_PDRV_GENIRQ=y
CONFIG_PWM=y
CONFIG_PWM_RENESAS_TPU=y
# CONFIG_DNOTIFY is not set
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_NFS_V4_1=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
# CONFIG_ARM_UNWIND is not set
CONFIG_CRYPTO=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_XZ_DEC=y
arch/arm/configs/kzm9g_defconfig deleted 100644 → 0
View file @ 00e3fcc2
# CONFIG_ARM_PATCH_PHYS_VIRT is not set
CONFIG_EXPERIMENTAL=y
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=16
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_IPC_NS is not set
# CONFIG_USER_NS is not set
# CONFIG_PID_NS is not set
# CONFIG_NET_NS is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_SHMOBILE_LEGACY=y
CONFIG_ARCH_SH73A0=y
CONFIG_MACH_KZM9G=y
CONFIG_MEMORY_START=0x41000000
CONFIG_MEMORY_SIZE=0x1f000000
CONFIG_ARM_ERRATA_743622=y
CONFIG_ARM_ERRATA_754322=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_SMP=y
CONFIG_SCHED_MC=y
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_HIGHMEM=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_KEXEC=y
CONFIG_VFP=y
CONFIG_NEON=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_PM=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_IRDA=y
CONFIG_SH_IRDA=y
# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
CONFIG_SMSC911X=y
# CONFIG_WLAN is not set
CONFIG_INPUT_SPARSEKMAP=y
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ST1232=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_ADXL34X=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_SH_SCI=y
CONFIG_SERIAL_SH_SCI_NR_UARTS=9
CONFIG_SERIAL_SH_SCI_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_SH_MOBILE=y
CONFIG_GPIO_PCF857X=y
# CONFIG_HWMON is not set
CONFIG_MFD_AS3711=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_AS3711=y
CONFIG_FB=y
CONFIG_FB_SH_MOBILE_LCDC=y
CONFIG_BACKLIGHT_AS3711=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
CONFIG_FB_SH_MOBILE_MERAM=y
CONFIG_SOUND=y
CONFIG_SND=y
# CONFIG_SND_SUPPORT_OLD_API is not set
# CONFIG_SND_VERBOSE_PROCFS is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_ARM is not set
# CONFIG_SND_USB is not set
CONFIG_SND_SOC=y
CONFIG_SND_SOC_SH4_FSI=y
# CONFIG_HID_SUPPORT is not set
CONFIG_USB=y
CONFIG_USB_R8A66597_HCD=y
CONFIG_USB_RENESAS_USBHS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_RENESAS_USBHS_UDC=y
CONFIG_USB_ETH=m
CONFIG_USB_MASS_STORAGE=m
CONFIG_MMC=y
# CONFIG_MMC_BLOCK_BOUNCE is not set
CONFIG_MMC_SDHI=y
CONFIG_MMC_SH_MMCIF=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_RS5C372=y
CONFIG_DMADEVICES=y
CONFIG_SH_DMAE=y
CONFIG_ASYNC_TX_DMA=y
CONFIG_STAGING=y
CONFIG_IIO=y
CONFIG_AK8975=y
# CONFIG_DNOTIFY is not set
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_NFS_V4_1=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_FTRACE is not set
# CONFIG_ARM_UNWIND is not set
CONFIG_CRYPTO=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_DES=y
CONFIG_CRC16=y
arch/arm/kernel/irq.c
View file @ c5fc2498
......@@ -140,7 +140,7 @@ int __init arch_probe_nr_irqs(void)
static bool migrate_one_irq(struct irq_desc *desc)
{
struct irq_data *d = irq_desc_get_irq_data(desc);
const struct cpumask *affinity = d->affinity;
const struct cpumask *affinity = irq_data_get_affinity_mask(d);
struct irq_chip *c;
bool ret = false;
......@@ -160,7 +160,7 @@ static bool migrate_one_irq(struct irq_desc *desc)
if (!c->irq_set_affinity)
pr_debug("IRQ%u: unable to set affinity\n", d->irq);
else if (c->irq_set_affinity(d, affinity, false) == IRQ_SET_MASK_OK && ret)
cpumask_copy(d->affinity, affinity);
cpumask_copy(irq_data_get_affinity_mask(d), affinity);
return ret;
}
......
arch/arm/kernel/psci.c
View file @ c5fc2498
......@@ -278,7 +278,7 @@ static int psci_0_1_init(struct device_node *np)
return err;
}
static const struct of_device_id psci_of_match[] __initconst = {
static const struct of_device_id const psci_of_match[] __initconst = {
{ .compatible = "arm,psci", .data = psci_0_1_init},
{ .compatible = "arm,psci-0.2", .data = psci_0_2_init},
{},
......
arch/arm/kernel/smp_twd.c
View file @ c5fc2498
......@@ -36,29 +36,30 @@ static DEFINE_PER_CPU(bool, percpu_setup_called);
static struct clock_event_device __percpu *twd_evt;
static int twd_ppi;
static void twd_set_mode(enum clock_event_mode mode,
struct clock_event_device *clk)
static int twd_shutdown(struct clock_event_device *clk)
{
unsigned long ctrl;
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE
| TWD_TIMER_CONTROL_PERIODIC;
writel_relaxed(DIV_ROUND_CLOSEST(twd_timer_rate, HZ),
twd_base + TWD_TIMER_LOAD);
break;
case CLOCK_EVT_MODE_ONESHOT:
/* period set, and timer enabled in 'next_event' hook */
ctrl = TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT;
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
default:
ctrl = 0;
}
writel_relaxed(0, twd_base + TWD_TIMER_CONTROL);
return 0;
}
static int twd_set_oneshot(struct clock_event_device *clk)
{
/* period set, and timer enabled in 'next_event' hook */
writel_relaxed(TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT,
twd_base + TWD_TIMER_CONTROL);
return 0;
}
static int twd_set_periodic(struct clock_event_device *clk)
{
unsigned long ctrl = TWD_TIMER_CONTROL_ENABLE |
TWD_TIMER_CONTROL_IT_ENABLE |
TWD_TIMER_CONTROL_PERIODIC;
writel_relaxed(DIV_ROUND_CLOSEST(twd_timer_rate, HZ),
twd_base + TWD_TIMER_LOAD);
writel_relaxed(ctrl, twd_base + TWD_TIMER_CONTROL);
return 0;
}
static int twd_set_next_event(unsigned long evt,
......@@ -94,7 +95,7 @@ static void twd_timer_stop(void)
{
struct clock_event_device *clk = raw_cpu_ptr(twd_evt);
twd_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
twd_shutdown(clk);
disable_percpu_irq(clk->irq);
}
......@@ -296,7 +297,10 @@ static void twd_timer_setup(void)
clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
CLOCK_EVT_FEAT_C3STOP;
clk->rating = 350;
clk->set_mode = twd_set_mode;
clk->set_state_shutdown = twd_shutdown;
clk->set_state_periodic = twd_set_periodic;
clk->set_state_oneshot = twd_set_oneshot;
clk->tick_resume = twd_shutdown;
clk->set_next_event = twd_set_next_event;
clk->irq = twd_ppi;
clk->cpumask = cpumask_of(cpu);
......
arch/arm/mach-at91/at91rm9200.c
View file @ c5fc2498
......@@ -37,7 +37,7 @@ static void __init at91rm9200_dt_device_init(void)
at91rm9200_pm_init();
}
static const char *at91rm9200_dt_board_compat[] __initconst = {
static const char *const at91rm9200_dt_board_compat[] __initconst = {
"atmel,at91rm9200",
NULL
};
......
arch/arm/mach-at91/at91sam9.c
View file @ c5fc2498
......@@ -72,7 +72,7 @@ static void __init at91sam9_dt_device_init(void)
at91sam9260_pm_init();
}
static const char *at91_dt_board_compat[] __initconst = {
static const char *const at91_dt_board_compat[] __initconst = {
"atmel,at91sam9",
NULL
};
......@@ -89,7 +89,7 @@ static void __init at91sam9g45_dt_device_init(void)
at91sam9g45_pm_init();
}
static const char *at91sam9g45_board_compat[] __initconst = {
static const char *const at91sam9g45_board_compat[] __initconst = {
"atmel,at91sam9g45",
NULL
};
......@@ -106,7 +106,7 @@ static void __init at91sam9x5_dt_device_init(void)
at91sam9x5_pm_init();
}
static const char *at91sam9x5_board_compat[] __initconst = {
static const char *const at91sam9x5_board_compat[] __initconst = {
"atmel,at91sam9x5",
"atmel,at91sam9n12",
NULL
......
arch/arm/mach-at91/pm.c
View file @ c5fc2498
......@@ -311,7 +311,7 @@ static void at91sam9_sdram_standby(void)
at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
}
static const struct of_device_id ramc_ids[] __initconst = {
static const struct of_device_id const ramc_ids[] __initconst = {
{ .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
{ .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
......
arch/arm/mach-at91/sama5.c
View file @ c5fc2498
......@@ -52,7 +52,7 @@ static void __init sama5_dt_device_init(void)
at91sam9x5_pm_init();
}
static const char *sama5_dt_board_compat[] __initconst = {
static const char *const sama5_dt_board_compat[] __initconst = {
"atmel,sama5",
NULL
};
......@@ -63,7 +63,7 @@ DT_MACHINE_START(sama5_dt, "Atmel SAMA5")
.dt_compat = sama5_dt_board_compat,
MACHINE_END
static const char *sama5_alt_dt_board_compat[] __initconst = {
static const char *const sama5_alt_dt_board_compat[] __initconst = {
"atmel,sama5d4",
NULL
};
......
arch/arm/mach-bcm/Makefile
View file @ c5fc2498
......@@ -39,10 +39,8 @@ obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o
# BCM63XXx
ifeq ($(CONFIG_ARCH_BCM_63XX),y)
CFLAGS_bcm63xx_headsmp.o += -march=armv7-a
obj-y += bcm63xx.o
obj-$(CONFIG_SMP) += bcm63xx_smp.o bcm63xx_headsmp.o \
bcm63xx_pmb.o
obj-$(CONFIG_SMP) += bcm63xx_smp.o bcm63xx_pmb.o
endif
ifeq ($(CONFIG_ARCH_BRCMSTB),y)
......
arch/arm/mach-bcm/bcm63xx_headsmp.S deleted 100644 → 0
View file @ 00e3fcc2
/*
* Copyright (C) 2015, Broadcom Corporation
* All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
ENTRY(bcm63138_secondary_startup)
ARM_BE8(setend be)
/*
* L1 cache does have unpredictable contents at power-up clean its
* contents without flushing
*/
bl v7_invalidate_l1
nop
b secondary_startup
ENDPROC(bcm63138_secondary_startup)
arch/arm/mach-bcm/bcm63xx_smp.c
View file @ c5fc2498
......@@ -127,7 +127,7 @@ static int bcm63138_smp_boot_secondary(unsigned int cpu,
}
/* Locate the secondary CPU node */
dn = of_get_cpu_node(cpu_logical_map(cpu), NULL);
dn = of_get_cpu_node(cpu, NULL);
if (!dn) {
pr_err("SMP: failed to locate secondary CPU%d node\n", cpu);
ret = -ENODEV;
......@@ -135,7 +135,7 @@ static int bcm63138_smp_boot_secondary(unsigned int cpu,
}
/* Write the secondary init routine to the BootLUT reset vector */
val = virt_to_phys(bcm63138_secondary_startup);
val = virt_to_phys(secondary_startup);
writel_relaxed(val, bootlut_base + BOOTLUT_RESET_VECT);
/* Power up the core, will jump straight to its reset vector when we
......
arch/arm/mach-bcm/bcm63xx_smp.h
View file @ c5fc2498
......@@ -3,7 +3,6 @@
struct device_node;
extern void bcm63138_secondary_startup(void);
extern int bcm63xx_pmb_power_on_cpu(struct device_node *dn);
#endif /* __BCM63XX_SMP_H */
arch/arm/mach-bcm/bcm_5301x.c
View file @ c5fc2498
......@@ -44,7 +44,7 @@ static void __init bcm5301x_init_early(void)
"imprecise external abort");
}
static const char __initconst *bcm5301x_dt_compat[] = {
static const char *const bcm5301x_dt_compat[] __initconst = {
"brcm,bcm4708",
NULL,
};
......
arch/arm/mach-bcm/bcm_kona_smc.c
View file @ c5fc2498
......@@ -33,7 +33,7 @@ struct bcm_kona_smc_data {
unsigned result;
};
static const struct of_device_id bcm_kona_smc_ids[] __initconst = {
static const struct of_device_id const bcm_kona_smc_ids[] __initconst = {
{.compatible = "brcm,kona-smc"},
{.compatible = "bcm,kona-smc"}, /* deprecated name */
{},
......
arch/arm/mach-clps711x/board-autcpu12.c
View file @ c5fc2498
......@@ -160,7 +160,7 @@ static struct platform_device autcpu12_mmgpio_pdev __initdata = {
},
};
static const struct gpio autcpu12_gpios[] __initconst = {
static const struct gpio const autcpu12_gpios[] __initconst = {
{ AUTCPU12_DPOT_CS, GPIOF_OUT_INIT_HIGH, "DPOT CS" },
{ AUTCPU12_DPOT_CLK, GPIOF_OUT_INIT_LOW, "DPOT CLK" },
{ AUTCPU12_DPOT_UD, GPIOF_OUT_INIT_LOW, "DPOT UD" },
......
arch/arm/mach-cns3xxx/core.c
View file @ c5fc2498
......@@ -113,30 +113,33 @@ void cns3xxx_power_off(void)
*/
static void __iomem *cns3xxx_tmr1;
static void cns3xxx_timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *clk)
static int cns3xxx_shutdown(struct clock_event_device *clk)
{
writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
return 0;
}
static int cns3xxx_set_oneshot(struct clock_event_device *clk)
{
unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
/* period set, and timer enabled in 'next_event' hook */
ctrl |= (1 << 2) | (1 << 9);
writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
return 0;
}
static int cns3xxx_set_periodic(struct clock_event_device *clk)
{
unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
int pclk = cns3xxx_cpu_clock() / 8;
int reload;
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
reload = pclk * 20 / (3 * HZ) * 0x25000;
writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
ctrl |= (1 << 0) | (1 << 2) | (1 << 9);
break;
case CLOCK_EVT_MODE_ONESHOT:
/* period set, and timer enabled in 'next_event' hook */
ctrl |= (1 << 2) | (1 << 9);
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
default:
ctrl = 0;
}
reload = pclk * 20 / (3 * HZ) * 0x25000;
writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
ctrl |= (1 << 0) | (1 << 2) | (1 << 9);
writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
return 0;
}
static int cns3xxx_timer_set_next_event(unsigned long evt,
......@@ -151,12 +154,16 @@ static int cns3xxx_timer_set_next_event(unsigned long evt,
}
static struct clock_event_device cns3xxx_tmr1_clockevent = {
.name = "cns3xxx timer1",
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.set_mode = cns3xxx_timer_set_mode,
.set_next_event = cns3xxx_timer_set_next_event,
.rating = 350,
.cpumask = cpu_all_mask,
.name = "cns3xxx timer1",
.features = CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_ONESHOT,
.set_state_shutdown = cns3xxx_shutdown,
.set_state_periodic = cns3xxx_set_periodic,
.set_state_oneshot = cns3xxx_set_oneshot,
.tick_resume = cns3xxx_shutdown,
.set_next_event = cns3xxx_timer_set_next_event,
.rating = 350,
.cpumask = cpu_all_mask,
};
static void __init cns3xxx_clockevents_init(unsigned int timer_irq)
......@@ -339,7 +346,7 @@ static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
.power_off = csn3xxx_usb_power_off,
};
static struct of_dev_auxdata cns3xxx_auxdata[] __initconst = {
static const struct of_dev_auxdata const cns3xxx_auxdata[] __initconst = {
{ "intel,usb-ehci", CNS3XXX_USB_BASE, "ehci-platform", &cns3xxx_usb_ehci_pdata },
{ "intel,usb-ohci", CNS3XXX_USB_OHCI_BASE, "ohci-platform", &cns3xxx_usb_ohci_pdata },
{ "cavium,cns3420-ahci", CNS3XXX_SATA2_BASE, "ahci", NULL },
......@@ -392,7 +399,7 @@ static void __init cns3xxx_init(void)
cns3xxx_auxdata, NULL);
}
static const char *cns3xxx_dt_compat[] __initdata = {
static const char *const cns3xxx_dt_compat[] __initconst = {
"cavium,cns3410",
"cavium,cns3420",
NULL,
......
arch/arm/mach-davinci/cp_intc.c
View file @ c5fc2498
......@@ -112,7 +112,7 @@ static int cp_intc_host_map(struct irq_domain *h, unsigned int virq,
pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw);
irq_set_chip(virq, &cp_intc_irq_chip);
set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
irq_set_probe(virq);
irq_set_handler(virq, handle_edge_irq);
return 0;
}
......
arch/arm/mach-davinci/da850.c
View file @ c5fc2498
......@@ -715,7 +715,7 @@ const short da850_lcdcntl_pins[] __initconst = {
-1
};
const short da850_vpif_capture_pins[] __initdata = {
const short da850_vpif_capture_pins[] __initconst = {
DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3,
DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7,
DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11,
......@@ -725,7 +725,7 @@ const short da850_vpif_capture_pins[] __initdata = {
-1
};
const short da850_vpif_display_pins[] __initdata = {
const short da850_vpif_display_pins[] __initconst = {
DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3,
DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7,
DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10,
......
arch/arm/mach-davinci/da8xx-dt.c
View file @ c5fc2498
......@@ -20,7 +20,7 @@
#define DA8XX_NUM_UARTS 3
static const struct of_device_id da8xx_irq_match[] __initconst = {
static const struct of_device_id const da8xx_irq_match[] __initconst = {
{ .compatible = "ti,cp-intc", .data = cp_intc_of_init, },
{ }
};
......@@ -59,7 +59,7 @@ static void __init da850_init_machine(void)
}
static const char *da850_boards_compat[] __initdata = {
static const char *const da850_boards_compat[] __initconst = {
"enbw,cmc",
"ti,da850-evm",
"ti,da850",
......
arch/arm/mach-davinci/time.c
View file @ c5fc2498
......@@ -303,36 +303,42 @@ static int davinci_set_next_event(unsigned long cycles,
return 0;
}
static void davinci_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
static int davinci_shutdown(struct clock_event_device *evt)
{
struct timer_s *t = &timers[TID_CLOCKEVENT];
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
t->period = davinci_clock_tick_rate / (HZ);
t->opts &= ~TIMER_OPTS_STATE_MASK;
t->opts |= TIMER_OPTS_PERIODIC;
timer32_config(t);
break;
case CLOCK_EVT_MODE_ONESHOT:
t->opts &= ~TIMER_OPTS_STATE_MASK;
t->opts |= TIMER_OPTS_ONESHOT;
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
t->opts &= ~TIMER_OPTS_STATE_MASK;
t->opts |= TIMER_OPTS_DISABLED;
break;
case CLOCK_EVT_MODE_RESUME:
break;
}
t->opts &= ~TIMER_OPTS_STATE_MASK;
t->opts |= TIMER_OPTS_DISABLED;
return 0;
}
static int davinci_set_oneshot(struct clock_event_device *evt)
{
struct timer_s *t = &timers[TID_CLOCKEVENT];
t->opts &= ~TIMER_OPTS_STATE_MASK;
t->opts |= TIMER_OPTS_ONESHOT;
return 0;
}
static int davinci_set_periodic(struct clock_event_device *evt)
{
struct timer_s *t = &timers[TID_CLOCKEVENT];
t->period = davinci_clock_tick_rate / (HZ);
t->opts &= ~TIMER_OPTS_STATE_MASK;
t->opts |= TIMER_OPTS_PERIODIC;
timer32_config(t);
return 0;
}
static struct clock_event_device clockevent_davinci = {
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.set_next_event = davinci_set_next_event,
.set_mode = davinci_set_mode,
.features = CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_ONESHOT,
.set_next_event = davinci_set_next_event,
.set_state_shutdown = davinci_shutdown,
.set_state_periodic = davinci_set_periodic,
.set_state_oneshot = davinci_set_oneshot,
};
......
arch/arm/mach-digicolor/digicolor.c
View file @ c5fc2498
......@@ -8,7 +8,7 @@
#include <asm/mach/arch.h>
static const char *digicolor_dt_compat[] __initconst = {
static const char *const digicolor_dt_compat[] __initconst = {
"cnxt,cx92755",
NULL,
};
......
arch/arm/mach-dove/irq.c
View file @ c5fc2498
......@@ -69,8 +69,9 @@ static struct irq_chip pmu_irq_chip = {
.irq_ack = pmu_irq_ack,
};
static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc)
static void pmu_irq_handler(unsigned int __irq, struct irq_desc *desc)
{
unsigned int irq = irq_desc_get_irq(desc);
unsigned long cause = readl(PMU_INTERRUPT_CAUSE);
cause &= readl(PMU_INTERRUPT_MASK);
......@@ -172,7 +173,7 @@ void __init dove_init_irq(void)
for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq);
irq_set_status_flags(i, IRQ_LEVEL);
set_irq_flags(i, IRQF_VALID);
irq_clear_status_flags(i, IRQ_NOREQUEST);
}
irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
}
arch/arm/mach-ebsa110/core.c
View file @ c5fc2498
......@@ -65,7 +65,7 @@ static void __init ebsa110_init_irq(void)
for (irq = 0; irq < NR_IRQS; irq++) {
irq_set_chip_and_handler(irq, &ebsa110_irq_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
}
}
......
arch/arm/mach-ep93xx/Kconfig
View file @ c5fc2498
......@@ -15,45 +15,8 @@ config CRUNCH
comment "EP93xx Platforms"
choice
prompt "EP93xx first SDRAM bank selection"
default EP93XX_SDCE3_SYNC_PHYS_OFFSET
config EP93XX_SDCE3_SYNC_PHYS_OFFSET
bool "0x00000000 - SDCE3/SyncBoot"
help
Select this option if you want support for EP93xx boards with the
first SDRAM bank at 0x00000000.
config EP93XX_SDCE0_PHYS_OFFSET
bool "0xc0000000 - SDCEO"
help
Select this option if you want support for EP93xx boards with the
first SDRAM bank at 0xc0000000.
config EP93XX_SDCE1_PHYS_OFFSET
bool "0xd0000000 - SDCE1"
help
Select this option if you want support for EP93xx boards with the
first SDRAM bank at 0xd0000000.
config EP93XX_SDCE2_PHYS_OFFSET
bool "0xe0000000 - SDCE2"
help
Select this option if you want support for EP93xx boards with the
first SDRAM bank at 0xe0000000.
config EP93XX_SDCE3_ASYNC_PHYS_OFFSET
bool "0xf0000000 - SDCE3/AsyncBoot"
help
Select this option if you want support for EP93xx boards with the
first SDRAM bank at 0xf0000000.
endchoice
config MACH_ADSSPHERE
bool "Support ADS Sphere"
depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET
help
Say 'Y' here if you want your kernel to support the ADS
Sphere board.
......@@ -63,7 +26,6 @@ config MACH_EDB93XX
config MACH_EDB9301
bool "Support Cirrus Logic EDB9301"
depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET
select MACH_EDB93XX
help
Say 'Y' here if you want your kernel to support the Cirrus
......@@ -71,7 +33,6 @@ config MACH_EDB9301
config MACH_EDB9302
bool "Support Cirrus Logic EDB9302"
depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET
select MACH_EDB93XX
help
Say 'Y' here if you want your kernel to support the Cirrus
......@@ -79,7 +40,6 @@ config MACH_EDB9302
config MACH_EDB9302A
bool "Support Cirrus Logic EDB9302A"
depends on EP93XX_SDCE0_PHYS_OFFSET
select MACH_EDB93XX
help
Say 'Y' here if you want your kernel to support the Cirrus
......@@ -87,7 +47,6 @@ config MACH_EDB9302A
config MACH_EDB9307
bool "Support Cirrus Logic EDB9307"
depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET
select MACH_EDB93XX
help
Say 'Y' here if you want your kernel to support the Cirrus
......@@ -95,7 +54,6 @@ config MACH_EDB9307
config MACH_EDB9307A
bool "Support Cirrus Logic EDB9307A"
depends on EP93XX_SDCE0_PHYS_OFFSET
select MACH_EDB93XX
help
Say 'Y' here if you want your kernel to support the Cirrus
......@@ -103,7 +61,6 @@ config MACH_EDB9307A
config MACH_EDB9312
bool "Support Cirrus Logic EDB9312"
depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET
select MACH_EDB93XX
help
Say 'Y' here if you want your kernel to support the Cirrus
......@@ -111,7 +68,6 @@ config MACH_EDB9312
config MACH_EDB9315
bool "Support Cirrus Logic EDB9315"
depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET
select MACH_EDB93XX
help
Say 'Y' here if you want your kernel to support the Cirrus
......@@ -119,14 +75,12 @@ config MACH_EDB9315
config MACH_EDB9315A
bool "Support Cirrus Logic EDB9315A"
depends on EP93XX_SDCE0_PHYS_OFFSET
select MACH_EDB93XX
help
Say 'Y' here if you want your kernel to support the Cirrus
Logic EDB9315A Evaluation Board.
config MACH_GESBC9312
depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET
bool "Support Glomation GESBC-9312-sx"
help
Say 'Y' here if you want your kernel to support the Glomation
......@@ -137,7 +91,6 @@ config MACH_MICRO9
config MACH_MICRO9H
bool "Support Contec Micro9-High"
depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET
select MACH_MICRO9
help
Say 'Y' here if you want your kernel to support the
......@@ -145,7 +98,6 @@ config MACH_MICRO9H
config MACH_MICRO9M
bool "Support Contec Micro9-Mid"
depends on EP93XX_SDCE3_ASYNC_PHYS_OFFSET
select MACH_MICRO9
help
Say 'Y' here if you want your kernel to support the
......@@ -153,7 +105,6 @@ config MACH_MICRO9M
config MACH_MICRO9L
bool "Support Contec Micro9-Lite"
depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET
select MACH_MICRO9
help
Say 'Y' here if you want your kernel to support the
......@@ -161,7 +112,6 @@ config MACH_MICRO9L
config MACH_MICRO9S
bool "Support Contec Micro9-Slim"
depends on EP93XX_SDCE3_ASYNC_PHYS_OFFSET
select MACH_MICRO9
help
Say 'Y' here if you want your kernel to support the
......@@ -169,28 +119,24 @@ config MACH_MICRO9S
config MACH_SIM_ONE
bool "Support Simplemachines Sim.One board"
depends on EP93XX_SDCE0_PHYS_OFFSET
help
Say 'Y' here if you want your kernel to support the
Simplemachines Sim.One board.
config MACH_SNAPPER_CL15
bool "Support Bluewater Systems Snapper CL15 Module"
depends on EP93XX_SDCE0_PHYS_OFFSET
help
Say 'Y' here if you want your kernel to support the Bluewater
Systems Snapper CL15 Module.
config MACH_TS72XX
bool "Support Technologic Systems TS-72xx SBC"
depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET
help
Say 'Y' here if you want your kernel to support the
Technologic Systems TS-72xx board.
config MACH_VISION_EP9307
bool "Support Vision Engraving Systems EP9307 SoM"
depends on EP93XX_SDCE0_PHYS_OFFSET
help
Say 'Y' here if you want your kernel to support the
Vision Engraving Systems EP9307 SoM.
......
arch/arm/mach-ep93xx/Makefile
View file @ c5fc2498
#
# Makefile for the linux kernel.
#
obj-y := core.o clock.o
obj-y := core.o clock.o timer-ep93xx.o
obj-$(CONFIG_EP93XX_DMA) += dma.o
......
arch/arm/mach-ep93xx/Makefile.boot
View file @ c5fc2498
zreladdr-$(CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET) += 0x00008000
params_phys-$(CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET) := 0x00000100
zreladdr-$(CONFIG_EP93XX_SDCE0_PHYS_OFFSET) += 0xc0008000
params_phys-$(CONFIG_EP93XX_SDCE0_PHYS_OFFSET) := 0xc0000100
zreladdr-$(CONFIG_EP93XX_SDCE1_PHYS_OFFSET) += 0xd0008000
params_phys-$(CONFIG_EP93XX_SDCE1_PHYS_OFFSET) := 0xd0000100
zreladdr-$(CONFIG_EP93XX_SDCE2_PHYS_OFFSET) += 0xe0008000
params_phys-$(CONFIG_EP93XX_SDCE2_PHYS_OFFSET) := 0xe0000100
zreladdr-$(CONFIG_EP93XX_SDCE3_ASYNC_PHYS_OFFSET) += 0xf0008000
params_phys-$(CONFIG_EP93XX_SDCE3_ASYNC_PHYS_OFFSET) := 0xf0000100
# Empty file waiting for deletion once Makefile.boot isn't needed any more.
arch/arm/mach-ep93xx/core.c
View file @ c5fc2498
......@@ -22,7 +22,6 @@
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/sys_soc.h>
#include <linux/timex.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/gpio.h>
......@@ -38,6 +37,7 @@
#include <linux/irqchip/arm-vic.h>
#include <linux/reboot.h>
#include <linux/usb/ohci_pdriver.h>
#include <linux/random.h>
#include <mach/hardware.h>
#include <linux/platform_data/video-ep93xx.h>
......@@ -47,7 +47,6 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include "soc.h"
......@@ -73,113 +72,6 @@ void __init ep93xx_map_io(void)
iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
}
/*************************************************************************
* Timer handling for EP93xx
*************************************************************************
* The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
* 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
* an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
* is free-running, and can't generate interrupts.
*
* The 508 kHz timers are ideal for use for the timer interrupt, as the
* most common values of HZ divide 508 kHz nicely. We pick one of the 16
* bit timers (timer 1) since we don't need more than 16 bits of reload
* value as long as HZ >= 8.
*
* The higher clock rate of timer 4 makes it a better choice than the
* other timers for use in gettimeoffset(), while the fact that it can't
* generate interrupts means we don't have to worry about not being able
* to use this timer for something else. We also use timer 4 for keeping
* track of lost jiffies.
*/
#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x))
#define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00)
#define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04)
#define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08)
#define EP93XX_TIMER123_CONTROL_ENABLE (1 << 7)
#define EP93XX_TIMER123_CONTROL_MODE (1 << 6)
#define EP93XX_TIMER123_CONTROL_CLKSEL (1 << 3)
#define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c)
#define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20)
#define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24)
#define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28)
#define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c)
#define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60)
#define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64)
#define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8)
#define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80)
#define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84)
#define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88)
#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c)
#define EP93XX_TIMER123_CLOCK 508469
#define EP93XX_TIMER4_CLOCK 983040
#define TIMER1_RELOAD ((EP93XX_TIMER123_CLOCK / HZ) - 1)
#define TIMER4_TICKS_PER_JIFFY DIV_ROUND_CLOSEST(EP93XX_TIMER4_CLOCK, HZ)
static unsigned int last_jiffy_time;
static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
{
/* Writing any value clears the timer interrupt */
__raw_writel(1, EP93XX_TIMER1_CLEAR);
/* Recover lost jiffies */
while ((signed long)
(__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
>= TIMER4_TICKS_PER_JIFFY) {
last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
timer_tick();
}
return IRQ_HANDLED;
}
static struct irqaction ep93xx_timer_irq = {
.name = "ep93xx timer",
.flags = IRQF_TIMER | IRQF_IRQPOLL,
.handler = ep93xx_timer_interrupt,
};
static u32 ep93xx_gettimeoffset(void)
{
int offset;
offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
/*
* Timer 4 is based on a 983.04 kHz reference clock,
* so dividing by 983040 gives the fraction of a second,
* so dividing by 0.983040 converts to uS.
* Refactor the calculation to avoid overflow.
* Finally, multiply by 1000 to give nS.
*/
return (offset + (53 * offset / 3072)) * 1000;
}
void __init ep93xx_timer_init(void)
{
u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
EP93XX_TIMER123_CONTROL_CLKSEL;
arch_gettimeoffset = ep93xx_gettimeoffset;
/* Enable periodic HZ timer. */
__raw_writel(tmode, EP93XX_TIMER1_CONTROL);
__raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD);
__raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
EP93XX_TIMER1_CONTROL);
/* Enable lost jiffy timer. */
__raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
EP93XX_TIMER4_VALUE_HIGH);
setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
}
/*************************************************************************
* EP93xx IRQ handling
*************************************************************************/
......@@ -971,6 +863,12 @@ static const char __init *ep93xx_get_soc_id(void)
if (id != id2)
return "invalid";
/* Toss the unique ID into the entropy pool */
add_device_randomness(&id2, 4);
add_device_randomness(&id3, 4);
add_device_randomness(&id4, 4);
add_device_randomness(&id5, 4);
snprintf(ep93xx_soc_id, sizeof(ep93xx_soc_id),
"%08x%08x%08x%08x", id2, id3, id4, id5);
......
arch/arm/mach-ep93xx/edb93xx.c
View file @ c5fc2498
......@@ -205,8 +205,6 @@ static void __init edb93xx_register_pwm(void)
* EDB93xx framebuffer
*************************************************************************/
static struct ep93xxfb_mach_info __initdata edb93xxfb_info = {
.num_modes = EP93XXFB_USE_MODEDB,
.bpp = 16,
.flags = 0,
};
......
arch/arm/mach-ep93xx/simone.c
View file @ c5fc2498
......@@ -40,8 +40,6 @@ static struct ep93xx_eth_data __initdata simone_eth_data = {
};
static struct ep93xxfb_mach_info __initdata simone_fb_info = {
.num_modes = EP93XXFB_USE_MODEDB,
.bpp = 16,
.flags = EP93XXFB_USE_SDCSN0 | EP93XXFB_PCLK_FALLING,
};
......@@ -169,6 +167,7 @@ static struct spi_board_info simone_spi_devices[] __initdata = {
static struct ep93xx_spi_info simone_spi_info __initdata = {
.num_chipselect = ARRAY_SIZE(simone_spi_devices),
.use_dma = 1,
};
static struct i2c_gpio_platform_data __initdata simone_i2c_gpio_data = {
......
arch/arm/mach-ep93xx/snappercl15.c
View file @ c5fc2498
......@@ -144,8 +144,6 @@ static struct i2c_board_info __initdata snappercl15_i2c_data[] = {
};
static struct ep93xxfb_mach_info __initdata snappercl15_fb_info = {
.num_modes = EP93XXFB_USE_MODEDB,
.bpp = 16,
};
static struct platform_device snappercl15_audio_device = {
......
arch/arm/mach-ep93xx/timer-ep93xx.c 0 → 100644
View file @ c5fc2498
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/sched_clock.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/mach/time.h>
#include "soc.h"
/*************************************************************************
* Timer handling for EP93xx
*************************************************************************
* The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
* 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
* an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
* is free-running, and can't generate interrupts.
*
* The 508 kHz timers are ideal for use for the timer interrupt, as the
* most common values of HZ divide 508 kHz nicely. We pick the 32 bit
* timer (timer 3) to get as long sleep intervals as possible when using
* CONFIG_NO_HZ.
*
* The higher clock rate of timer 4 makes it a better choice than the
* other timers for use as clock source and for sched_clock(), providing
* a stable 40 bit time base.
*************************************************************************
*/
#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x))
#define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00)
#define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04)
#define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08)
#define EP93XX_TIMER123_CONTROL_ENABLE (1 << 7)
#define EP93XX_TIMER123_CONTROL_MODE (1 << 6)
#define EP93XX_TIMER123_CONTROL_CLKSEL (1 << 3)
#define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c)
#define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20)
#define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24)
#define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28)
#define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c)
#define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60)
#define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64)
#define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8)
#define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80)
#define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84)
#define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88)
#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c)
#define EP93XX_TIMER123_RATE 508469
#define EP93XX_TIMER4_RATE 983040
static u64 notrace ep93xx_read_sched_clock(void)
{
u64 ret;
ret = readl(EP93XX_TIMER4_VALUE_LOW);
ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32);
return ret;
}
cycle_t ep93xx_clocksource_read(struct clocksource *c)
{
u64 ret;
ret = readl(EP93XX_TIMER4_VALUE_LOW);
ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32);
return (cycle_t) ret;
}
static int ep93xx_clkevt_set_next_event(unsigned long next,
struct clock_event_device *evt)
{
/* Default mode: periodic, off, 508 kHz */
u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
EP93XX_TIMER123_CONTROL_CLKSEL;
/* Clear timer */
writel(tmode, EP93XX_TIMER3_CONTROL);
/* Set next event */
writel(next, EP93XX_TIMER3_LOAD);
writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
EP93XX_TIMER3_CONTROL);
return 0;
}
static int ep93xx_clkevt_shutdown(struct clock_event_device *evt)
{
/* Disable timer */
writel(0, EP93XX_TIMER3_CONTROL);
return 0;
}
static struct clock_event_device ep93xx_clockevent = {
.name = "timer1",
.features = CLOCK_EVT_FEAT_ONESHOT,
.set_state_shutdown = ep93xx_clkevt_shutdown,
.set_state_oneshot = ep93xx_clkevt_shutdown,
.tick_resume = ep93xx_clkevt_shutdown,
.set_next_event = ep93xx_clkevt_set_next_event,
.rating = 300,
};
static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = dev_id;
/* Writing any value clears the timer interrupt */
writel(1, EP93XX_TIMER3_CLEAR);
evt->event_handler(evt);
return IRQ_HANDLED;
}
static struct irqaction ep93xx_timer_irq = {
.name = "ep93xx timer",
.flags = IRQF_TIMER | IRQF_IRQPOLL,
.handler = ep93xx_timer_interrupt,
.dev_id = &ep93xx_clockevent,
};
void __init ep93xx_timer_init(void)
{
/* Enable and register clocksource and sched_clock on timer 4 */
writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
EP93XX_TIMER4_VALUE_HIGH);
clocksource_mmio_init(NULL, "timer4",
EP93XX_TIMER4_RATE, 200, 40,
ep93xx_clocksource_read);
sched_clock_register(ep93xx_read_sched_clock, 40,
EP93XX_TIMER4_RATE);
/* Set up clockevent on timer 3 */
setup_irq(IRQ_EP93XX_TIMER3, &ep93xx_timer_irq);
clockevents_config_and_register(&ep93xx_clockevent,
EP93XX_TIMER123_RATE,
1,
0xffffffffU);
}
arch/arm/mach-ep93xx/vision_ep9307.c
View file @ c5fc2498
......@@ -29,6 +29,8 @@
#include <linux/spi/mmc_spi.h>
#include <linux/mmc/host.h>
#include <sound/cs4271.h>
#include <mach/hardware.h>
#include <linux/platform_data/video-ep93xx.h>
#include <linux/platform_data/spi-ep93xx.h>
......@@ -104,8 +106,6 @@ static void vision_lcd_blank(int blank_mode, struct fb_info *info)
}
static struct ep93xxfb_mach_info ep93xxfb_info __initdata = {
.num_modes = EP93XXFB_USE_MODEDB,
.bpp = 16,
.flags = EP93XXFB_USE_SDCSN0 | EP93XXFB_PCLK_FALLING,
.setup = vision_lcd_setup,
.teardown = vision_lcd_teardown,
......@@ -168,6 +168,35 @@ static struct i2c_board_info vision_i2c_info[] __initdata = {
},
};
/*************************************************************************
* SPI CS4271 Audio Codec
*************************************************************************/
static struct cs4271_platform_data vision_cs4271_data = {
.gpio_nreset = EP93XX_GPIO_LINE_H(2),
};
static int vision_cs4271_hw_setup(struct spi_device *spi)
{
return gpio_request_one(EP93XX_GPIO_LINE_EGPIO6,
GPIOF_OUT_INIT_HIGH, spi->modalias);
}
static void vision_cs4271_hw_cleanup(struct spi_device *spi)
{
gpio_free(EP93XX_GPIO_LINE_EGPIO6);
}
static void vision_cs4271_hw_cs_control(struct spi_device *spi, int value)
{
gpio_set_value(EP93XX_GPIO_LINE_EGPIO6, value);
}
static struct ep93xx_spi_chip_ops vision_cs4271_hw = {
.setup = vision_cs4271_hw_setup,
.cleanup = vision_cs4271_hw_cleanup,
.cs_control = vision_cs4271_hw_cs_control,
};
/*************************************************************************
* SPI Flash
*************************************************************************/
......@@ -262,12 +291,20 @@ static struct ep93xx_spi_chip_ops vision_spi_mmc_hw = {
*************************************************************************/
static struct spi_board_info vision_spi_board_info[] __initdata = {
{
.modalias = "cs4271",
.platform_data = &vision_cs4271_data,
.controller_data = &vision_cs4271_hw,
.max_speed_hz = 6000000,
.bus_num = 0,
.chip_select = 0,
.mode = SPI_MODE_3,
}, {
.modalias = "sst25l",
.platform_data = &vision_spi_flash_data,
.controller_data = &vision_spi_flash_hw,
.max_speed_hz = 20000000,
.bus_num = 0,
.chip_select = 0,
.chip_select = 1,
.mode = SPI_MODE_3,
}, {
.modalias = "mmc_spi",
......@@ -275,15 +312,30 @@ static struct spi_board_info vision_spi_board_info[] __initdata = {
.controller_data = &vision_spi_mmc_hw,
.max_speed_hz = 20000000,
.bus_num = 0,
.chip_select = 1,
.chip_select = 2,
.mode = SPI_MODE_3,
},
};
static struct ep93xx_spi_info vision_spi_master __initdata = {
.num_chipselect = ARRAY_SIZE(vision_spi_board_info),
.num_chipselect = ARRAY_SIZE(vision_spi_board_info),
.use_dma = 1,
};
/*************************************************************************
* I2S Audio
*************************************************************************/
static struct platform_device vision_audio_device = {
.name = "edb93xx-audio",
.id = -1,
};
static void __init vision_register_i2s(void)
{
ep93xx_register_i2s();
platform_device_register(&vision_audio_device);
}
/*************************************************************************
* Machine Initialization
*************************************************************************/
......@@ -309,6 +361,7 @@ static void __init vision_init_machine(void)
ARRAY_SIZE(vision_i2c_info));
ep93xx_register_spi(&vision_spi_master, vision_spi_board_info,
ARRAY_SIZE(vision_spi_board_info));
vision_register_i2s();
}
MACHINE_START(VISION_EP9307, "Vision Engraving Systems EP9307")
......
arch/arm/mach-exynos/Kconfig
View file @ c5fc2498
......@@ -30,6 +30,11 @@ menuconfig ARCH_EXYNOS
if ARCH_EXYNOS
config S5P_DEV_MFC
bool
help
Compile in setup memory (init) code for MFC
config ARCH_EXYNOS3
bool "SAMSUNG EXYNOS3"
select ARM_CPU_SUSPEND if PM
......
arch/arm/mach-exynos/Makefile
View file @ c5fc2498
......@@ -23,3 +23,5 @@ AFLAGS_sleep.o :=-Wa,-march=armv7-a$(plus_sec)
obj-$(CONFIG_EXYNOS5420_MCPM) += mcpm-exynos.o
CFLAGS_mcpm-exynos.o += -march=armv7-a
obj-$(CONFIG_S5P_DEV_MFC) += s5p-dev-mfc.o
arch/arm/mach-exynos/common.h
View file @ c5fc2498
......@@ -128,6 +128,12 @@ void exynos_firmware_init(void);
/* CPU BOOT mode flag for Exynos3250 SoC bootloader */
#define C2_STATE (1 << 3)
/*
* Magic values for bootloader indicating chosen low power mode.
* See also Documentation/arm/Samsung/Bootloader-interface.txt
*/
#define EXYNOS_SLEEP_MAGIC 0x00000bad
#define EXYNOS_AFTR_MAGIC 0xfcba0d10
void exynos_set_boot_flag(unsigned int cpu, unsigned int mode);
void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode);
......
arch/arm/mach-exynos/firmware.c
View file @ c5fc2498
......@@ -25,8 +25,6 @@
#include "common.h"
#include "smc.h"
#define EXYNOS_SLEEP_MAGIC 0x00000bad
#define EXYNOS_AFTR_MAGIC 0xfcba0d10
#define EXYNOS_BOOT_ADDR 0x8
#define EXYNOS_BOOT_FLAG 0xc
......
arch/arm/mach-exynos/pmu.c
View file @ c5fc2498
......@@ -698,7 +698,7 @@ static void exynos_power_off(void)
;
}
void exynos5420_powerdown_conf(enum sys_powerdown mode)
static void exynos5420_powerdown_conf(enum sys_powerdown mode)
{
u32 this_cluster;
......@@ -991,7 +991,6 @@ static int exynos_pmu_probe(struct platform_device *pdev)
static struct platform_driver exynos_pmu_driver = {
.driver = {
.name = "exynos-pmu",
.owner = THIS_MODULE,
.of_match_table = exynos_pmu_of_device_ids,
},
.probe = exynos_pmu_probe,
......
arch/arm/plat-samsung/include/plat/regs-srom.h → arch/arm/mach-exynos/regs-srom.h
View file @ c5fc2498
/* linux/arch/arm/plat-samsung/include/plat/regs-srom.h
*
/*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
......
arch/arm/mach-exynos/suspend.c
View file @ c5fc2498
......@@ -32,13 +32,11 @@
#include <asm/suspend.h>
#include <plat/pm-common.h>
#include <plat/regs-srom.h>
#include "common.h"
#include "regs-pmu.h"
#include "exynos-pmu.h"
#define S5P_CHECK_SLEEP 0x00000BAD
#include "regs-pmu.h"
#include "regs-srom.h"
#define REG_TABLE_END (-1U)
......@@ -331,7 +329,7 @@ static void exynos_pm_enter_sleep_mode(void)
{
/* Set value of power down register for sleep mode */
exynos_sys_powerdown_conf(SYS_SLEEP);
pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
pmu_raw_writel(EXYNOS_SLEEP_MAGIC, S5P_INFORM1);
}
static void exynos_pm_prepare(void)
......
arch/arm/mach-footbridge/common.c
View file @ c5fc2498
......@@ -106,7 +106,7 @@ static void __init __fb_init_irq(void)
for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) {
irq_set_chip_and_handler(irq, &fb_chip, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
}
}
......
arch/arm/mach-footbridge/dc21285-timer.c
View file @ c5fc2498
......@@ -57,34 +57,32 @@ static int ckevt_dc21285_set_next_event(unsigned long delta,
return 0;
}
static void ckevt_dc21285_set_mode(enum clock_event_mode mode,
struct clock_event_device *c)
static int ckevt_dc21285_shutdown(struct clock_event_device *c)
{
switch (mode) {
case CLOCK_EVT_MODE_RESUME:
case CLOCK_EVT_MODE_PERIODIC:
*CSR_TIMER1_CLR = 0;
*CSR_TIMER1_LOAD = (mem_fclk_21285 + 8 * HZ) / (16 * HZ);
*CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD |
TIMER_CNTL_DIV16;
break;
case CLOCK_EVT_MODE_ONESHOT:
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
*CSR_TIMER1_CNTL = 0;
break;
}
*CSR_TIMER1_CNTL = 0;
return 0;
}
static int ckevt_dc21285_set_periodic(struct clock_event_device *c)
{
*CSR_TIMER1_CLR = 0;
*CSR_TIMER1_LOAD = (mem_fclk_21285 + 8 * HZ) / (16 * HZ);
*CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD |
TIMER_CNTL_DIV16;
return 0;
}
static struct clock_event_device ckevt_dc21285 = {
.name = "dc21285_timer1",
.features = CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_ONESHOT,
.rating = 200,
.irq = IRQ_TIMER1,
.set_next_event = ckevt_dc21285_set_next_event,
.set_mode = ckevt_dc21285_set_mode,
.name = "dc21285_timer1",
.features = CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_ONESHOT,
.rating = 200,
.irq = IRQ_TIMER1,
.set_next_event = ckevt_dc21285_set_next_event,
.set_state_shutdown = ckevt_dc21285_shutdown,
.set_state_periodic = ckevt_dc21285_set_periodic,
.set_state_oneshot = ckevt_dc21285_shutdown,
.tick_resume = ckevt_dc21285_set_periodic,
};
static irqreturn_t timer1_interrupt(int irq, void *dev_id)
......@@ -94,7 +92,7 @@ static irqreturn_t timer1_interrupt(int irq, void *dev_id)
*CSR_TIMER1_CLR = 0;
/* Stop the timer if in one-shot mode */
if (ce->mode == CLOCK_EVT_MODE_ONESHOT)
if (clockevent_state_oneshot(ce))
*CSR_TIMER1_CNTL = 0;
ce->event_handler(ce);
......
arch/arm/mach-footbridge/isa-irq.c
View file @ c5fc2498
......@@ -153,13 +153,13 @@ void __init isa_init_irq(unsigned int host_irq)
for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) {
irq_set_chip_and_handler(irq, &isa_lo_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
}
for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) {
irq_set_chip_and_handler(irq, &isa_hi_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
}
request_resource(&ioport_resource, &pic1_resource);
......@@ -175,8 +175,8 @@ void __init isa_init_irq(unsigned int host_irq)
* resistor on this line.
*/
if (machine_is_netwinder())
set_irq_flags(_ISA_IRQ(11), IRQF_VALID |
IRQF_PROBE | IRQF_NOAUTOEN);
irq_modify_status(_ISA_IRQ(11),
IRQ_NOREQUEST | IRQ_NOPROBE, IRQ_NOAUTOEN);
}
}
......
arch/arm/mach-gemini/gpio.c
View file @ c5fc2498
......@@ -220,7 +220,7 @@ void __init gemini_gpio_init(void)
j < GPIO_IRQ_BASE + (i + 1) * 32; j++) {
irq_set_chip_and_handler(j, &gpio_irq_chip,
handle_edge_irq);
set_irq_flags(j, IRQF_VALID);
irq_clear_status_flags(j, IRQ_NOREQUEST);
}
irq_set_chained_handler_and_data(IRQ_GPIO(i), gpio_irq_handler,
......
arch/arm/mach-gemini/include/mach/hardware.h
View file @ c5fc2498
......@@ -57,9 +57,6 @@
#define GEMINI_USB1_BASE 0x69000000
#define GEMINI_BIG_ENDIAN_BASE 0x80000000
#define GEMINI_TIMER1_BASE GEMINI_TIMER_BASE
#define GEMINI_TIMER2_BASE (GEMINI_TIMER_BASE + 0x10)
#define GEMINI_TIMER3_BASE (GEMINI_TIMER_BASE + 0x20)
/*
* UART Clock when System clk is 150MHz
......
arch/arm/mach-gemini/irq.c
View file @ c5fc2498
......@@ -92,7 +92,7 @@ void __init gemini_init_irq(void)
} else {
irq_set_handler(i, handle_level_irq);
}
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
}
/* Disable all interrupts */
......
arch/arm/mach-gemini/time.c
View file @ c5fc2498
......@@ -15,93 +15,147 @@
#include <asm/mach/time.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/sched_clock.h>
/*
* Register definitions for the timers
*/
#define TIMER_COUNT(BASE_ADDR) (BASE_ADDR + 0x00)
#define TIMER_LOAD(BASE_ADDR) (BASE_ADDR + 0x04)
#define TIMER_MATCH1(BASE_ADDR) (BASE_ADDR + 0x08)
#define TIMER_MATCH2(BASE_ADDR) (BASE_ADDR + 0x0C)
#define TIMER_CR(BASE_ADDR) (BASE_ADDR + 0x30)
#define TIMER_1_CR_ENABLE (1 << 0)
#define TIMER_1_CR_CLOCK (1 << 1)
#define TIMER_1_CR_INT (1 << 2)
#define TIMER_2_CR_ENABLE (1 << 3)
#define TIMER_2_CR_CLOCK (1 << 4)
#define TIMER_2_CR_INT (1 << 5)
#define TIMER_3_CR_ENABLE (1 << 6)
#define TIMER_3_CR_CLOCK (1 << 7)
#define TIMER_3_CR_INT (1 << 8)
#define TIMER1_BASE GEMINI_TIMER_BASE
#define TIMER2_BASE (GEMINI_TIMER_BASE + 0x10)
#define TIMER3_BASE (GEMINI_TIMER_BASE + 0x20)
#define TIMER_COUNT(BASE) (IO_ADDRESS(BASE) + 0x00)
#define TIMER_LOAD(BASE) (IO_ADDRESS(BASE) + 0x04)
#define TIMER_MATCH1(BASE) (IO_ADDRESS(BASE) + 0x08)
#define TIMER_MATCH2(BASE) (IO_ADDRESS(BASE) + 0x0C)
#define TIMER_CR (IO_ADDRESS(GEMINI_TIMER_BASE) + 0x30)
#define TIMER_INTR_STATE (IO_ADDRESS(GEMINI_TIMER_BASE) + 0x34)
#define TIMER_INTR_MASK (IO_ADDRESS(GEMINI_TIMER_BASE) + 0x38)
#define TIMER_1_CR_ENABLE (1 << 0)
#define TIMER_1_CR_CLOCK (1 << 1)
#define TIMER_1_CR_INT (1 << 2)
#define TIMER_2_CR_ENABLE (1 << 3)
#define TIMER_2_CR_CLOCK (1 << 4)
#define TIMER_2_CR_INT (1 << 5)
#define TIMER_3_CR_ENABLE (1 << 6)
#define TIMER_3_CR_CLOCK (1 << 7)
#define TIMER_3_CR_INT (1 << 8)
#define TIMER_1_CR_UPDOWN (1 << 9)
#define TIMER_2_CR_UPDOWN (1 << 10)
#define TIMER_3_CR_UPDOWN (1 << 11)
#define TIMER_DEFAULT_FLAGS (TIMER_1_CR_UPDOWN | \
TIMER_3_CR_ENABLE | \
TIMER_3_CR_UPDOWN)
#define TIMER_1_INT_MATCH1 (1 << 0)
#define TIMER_1_INT_MATCH2 (1 << 1)
#define TIMER_1_INT_OVERFLOW (1 << 2)
#define TIMER_2_INT_MATCH1 (1 << 3)
#define TIMER_2_INT_MATCH2 (1 << 4)
#define TIMER_2_INT_OVERFLOW (1 << 5)
#define TIMER_3_INT_MATCH1 (1 << 6)
#define TIMER_3_INT_MATCH2 (1 << 7)
#define TIMER_3_INT_OVERFLOW (1 << 8)
#define TIMER_INT_ALL_MASK 0x1ff
static unsigned int tick_rate;
static u64 notrace gemini_read_sched_clock(void)
{
return readl(TIMER_COUNT(TIMER3_BASE));
}
static int gemini_timer_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
u32 cr;
cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
/* Setup the match register */
cr = readl(TIMER_COUNT(TIMER1_BASE));
writel(cr + cycles, TIMER_MATCH1(TIMER1_BASE));
if (readl(TIMER_COUNT(TIMER1_BASE)) - cr > cycles)
return -ETIME;
/* This may be overdoing it, feel free to test without this */
cr &= ~TIMER_2_CR_ENABLE;
cr &= ~TIMER_2_CR_INT;
writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
return 0;
}
/* Set next event */
writel(cycles, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE)));
writel(cycles, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE)));
cr |= TIMER_2_CR_ENABLE;
cr |= TIMER_2_CR_INT;
writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
static int gemini_timer_shutdown(struct clock_event_device *evt)
{
u32 cr;
/*
* Disable also for oneshot: the set_next() call will arm the timer
* instead.
*/
/* Stop timer and interrupt. */
cr = readl(TIMER_CR);
cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT);
writel(cr, TIMER_CR);
/* Setup counter start from 0 */
writel(0, TIMER_COUNT(TIMER1_BASE));
writel(0, TIMER_LOAD(TIMER1_BASE));
/* enable interrupt */
cr = readl(TIMER_INTR_MASK);
cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2);
cr |= TIMER_1_INT_MATCH1;
writel(cr, TIMER_INTR_MASK);
/* start the timer */
cr = readl(TIMER_CR);
cr |= TIMER_1_CR_ENABLE;
writel(cr, TIMER_CR);
return 0;
}
static void gemini_timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
static int gemini_timer_set_periodic(struct clock_event_device *evt)
{
u32 period = DIV_ROUND_CLOSEST(tick_rate, HZ);
u32 cr;
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
/* Start the timer */
writel(period,
TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE)));
writel(period,
TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE)));
cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
cr |= TIMER_2_CR_ENABLE;
cr |= TIMER_2_CR_INT;
writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
break;
case CLOCK_EVT_MODE_ONESHOT:
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
case CLOCK_EVT_MODE_RESUME:
/*
* Disable also for oneshot: the set_next() call will
* arm the timer instead.
*/
cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
cr &= ~TIMER_2_CR_ENABLE;
cr &= ~TIMER_2_CR_INT;
writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
break;
default:
break;
}
/* Stop timer and interrupt */
cr = readl(TIMER_CR);
cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT);
writel(cr, TIMER_CR);
/* Setup timer to fire at 1/HT intervals. */
cr = 0xffffffff - (period - 1);
writel(cr, TIMER_COUNT(TIMER1_BASE));
writel(cr, TIMER_LOAD(TIMER1_BASE));
/* enable interrupt on overflow */
cr = readl(TIMER_INTR_MASK);
cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2);
cr |= TIMER_1_INT_OVERFLOW;
writel(cr, TIMER_INTR_MASK);
/* Start the timer */
cr = readl(TIMER_CR);
cr |= TIMER_1_CR_ENABLE;
cr |= TIMER_1_CR_INT;
writel(cr, TIMER_CR);
return 0;
}
/* Use TIMER2 as clock event */
/* Use TIMER1 as clock event */
static struct clock_event_device gemini_clockevent = {
.name = "TIMER2",
.rating = 300, /* Reasonably fast and accurate clock event */
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.set_next_event = gemini_timer_set_next_event,
.set_mode = gemini_timer_set_mode,
.name = "TIMER1",
/* Reasonably fast and accurate clock event */
.rating = 300,
.shift = 32,
.features = CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_ONESHOT,
.set_next_event = gemini_timer_set_next_event,
.set_state_shutdown = gemini_timer_shutdown,
.set_state_periodic = gemini_timer_set_periodic,
.set_state_oneshot = gemini_timer_shutdown,
.tick_resume = gemini_timer_shutdown,
};
/*
......@@ -151,20 +205,35 @@ void __init gemini_timer_init(void)
}
/*
* Make irqs happen for the system timer
* Reset the interrupt mask and status
*/
setup_irq(IRQ_TIMER2, &gemini_timer_irq);
/* Enable and use TIMER1 as clock source */
writel(0xffffffff, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE)));
writel(0xffffffff, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER1_BASE)));
writel(TIMER_1_CR_ENABLE, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
if (clocksource_mmio_init(TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE)),
"TIMER1", tick_rate, 300, 32,
clocksource_mmio_readl_up))
pr_err("timer: failed to initialize gemini clock source\n");
/* Configure and register the clockevent */
writel(TIMER_INT_ALL_MASK, TIMER_INTR_MASK);
writel(0, TIMER_INTR_STATE);
writel(TIMER_DEFAULT_FLAGS, TIMER_CR);
/*
* Setup free-running clocksource timer (interrupts
* disabled.)
*/
writel(0, TIMER_COUNT(TIMER3_BASE));
writel(0, TIMER_LOAD(TIMER3_BASE));
writel(0, TIMER_MATCH1(TIMER3_BASE));
writel(0, TIMER_MATCH2(TIMER3_BASE));
clocksource_mmio_init(TIMER_COUNT(TIMER3_BASE),
"gemini_clocksource", tick_rate,
300, 32, clocksource_mmio_readl_up);
sched_clock_register(gemini_read_sched_clock, 32, tick_rate);
/*
* Setup clockevent timer (interrupt-driven.)
*/
writel(0, TIMER_COUNT(TIMER1_BASE));
writel(0, TIMER_LOAD(TIMER1_BASE));
writel(0, TIMER_MATCH1(TIMER1_BASE));
writel(0, TIMER_MATCH2(TIMER1_BASE));
setup_irq(IRQ_TIMER1, &gemini_timer_irq);
gemini_clockevent.cpumask = cpumask_of(0);
clockevents_config_and_register(&gemini_clockevent, tick_rate,
1, 0xffffffff);
}
arch/arm/mach-imx/3ds_debugboard.c
View file @ c5fc2498
......@@ -195,7 +195,7 @@ int __init mxc_expio_init(u32 base, u32 intr_gpio)
for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) {
irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
irq_clear_status_flags(i, IRQ_NOREQUEST);
}
irq_set_irq_type(p_irq, IRQF_TRIGGER_LOW);
irq_set_chained_handler(p_irq, mxc_expio_irq_handler);
......
arch/arm/mach-imx/epit.c
View file @ c5fc2498
......@@ -57,7 +57,6 @@
#include "hardware.h"
static struct clock_event_device clockevent_epit;
static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
static void __iomem *timer_base;
......@@ -106,8 +105,8 @@ static int epit_set_next_event(unsigned long evt,
return 0;
}
static void epit_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
/* Left event sources disabled, no more interrupts appear */
static int epit_shutdown(struct clock_event_device *evt)
{
unsigned long flags;
......@@ -120,39 +119,41 @@ static void epit_set_mode(enum clock_event_mode mode,
/* Disable interrupt in GPT module */
epit_irq_disable();
if (mode != clockevent_mode) {
/* Set event time into far-far future */
/* Clear pending interrupt */
epit_irq_acknowledge();
}
/* Clear pending interrupt */
epit_irq_acknowledge();
/* Remember timer mode */
clockevent_mode = mode;
local_irq_restore(flags);
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
printk(KERN_ERR "epit_set_mode: Periodic mode is not "
"supported for i.MX EPIT\n");
break;
case CLOCK_EVT_MODE_ONESHOT:
return 0;
}
static int epit_set_oneshot(struct clock_event_device *evt)
{
unsigned long flags;
/*
* The timer interrupt generation is disabled at least
* for enough time to call epit_set_next_event()
*/
local_irq_save(flags);
/* Disable interrupt in GPT module */
epit_irq_disable();
/* Clear pending interrupt, only while switching mode */
if (!clockevent_state_oneshot(evt))
epit_irq_acknowledge();
/*
* Do not put overhead of interrupt enable/disable into
* epit_set_next_event(), the core has about 4 minutes
* to call epit_set_next_event() or shutdown clock after
* mode switching
*/
local_irq_save(flags);
epit_irq_enable();
local_irq_restore(flags);
break;
case CLOCK_EVT_MODE_SHUTDOWN:
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_RESUME:
/* Left event sources disabled, no more interrupts appear */
break;
}
epit_irq_enable();
local_irq_restore(flags);
return 0;
}
/*
......@@ -176,11 +177,13 @@ static struct irqaction epit_timer_irq = {
};
static struct clock_event_device clockevent_epit = {
.name = "epit",
.features = CLOCK_EVT_FEAT_ONESHOT,
.set_mode = epit_set_mode,
.set_next_event = epit_set_next_event,
.rating = 200,
.name = "epit",
.features = CLOCK_EVT_FEAT_ONESHOT,
.set_state_shutdown = epit_shutdown,
.tick_resume = epit_shutdown,
.set_state_oneshot = epit_set_oneshot,
.set_next_event = epit_set_next_event,
.rating = 200,
};
static int __init epit_clockevent_init(struct clk *timer_clk)
......
arch/arm/mach-imx/mach-imx7d.c
View file @ c5fc2498
......@@ -31,7 +31,7 @@ static void __init imx7d_init_irq(void)
irqchip_init();
}
static const char *imx7d_dt_compat[] __initconst = {
static const char *const imx7d_dt_compat[] __initconst = {
"fsl,imx7d",
NULL,
};
......
arch/arm/mach-imx/mach-mx31ads.c
View file @ c5fc2498
......@@ -238,7 +238,7 @@ static void __init mx31ads_init_expio(void)
for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) {
irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
irq_clear_status_flags(i, IRQ_NOREQUEST);
}
irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_4));
irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
......
arch/arm/mach-iop13xx/irq.c
View file @ c5fc2498
......@@ -233,7 +233,7 @@ void __init iop13xx_init_irq(void)
irq_set_chip(i, &iop13xx_irqchip4);
irq_set_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
}
iop13xx_msi_init();
......
arch/arm/mach-iop32x/irq.c
View file @ c5fc2498
......@@ -69,6 +69,6 @@ void __init iop32x_init_irq(void)
for (i = 0; i < NR_IRQS; i++) {
irq_set_chip_and_handler(i, &ext_chip, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
}
}
arch/arm/mach-iop33x/irq.c
View file @ c5fc2498
......@@ -113,6 +113,6 @@ void __init iop33x_init_irq(void)
irq_set_chip_and_handler(i,
(i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2,
handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
}
}
arch/arm/mach-ixp4xx/common.c
View file @ c5fc2498
......@@ -296,7 +296,7 @@ void __init ixp4xx_init_irq(void)
for(i = 0; i < NR_IRQS; i++) {
irq_set_chip_and_handler(i, &ixp4xx_irq_chip,
handle_level_irq);
set_irq_flags(i, IRQF_VALID);
irq_clear_status_flags(i, IRQ_NOREQUEST);
}
}
......@@ -521,43 +521,55 @@ static int ixp4xx_set_next_event(unsigned long evt,
return 0;
}
static void ixp4xx_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
static int ixp4xx_shutdown(struct clock_event_device *evt)
{
unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
osrt = IXP4XX_LATCH & ~IXP4XX_OST_RELOAD_MASK;
opts = IXP4XX_OST_ENABLE;
break;
case CLOCK_EVT_MODE_ONESHOT:
/* period set by 'set next_event' */
osrt = 0;
opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT;
break;
case CLOCK_EVT_MODE_SHUTDOWN:
opts &= ~IXP4XX_OST_ENABLE;
break;
case CLOCK_EVT_MODE_RESUME:
opts |= IXP4XX_OST_ENABLE;
break;
case CLOCK_EVT_MODE_UNUSED:
default:
osrt = opts = 0;
break;
}
opts &= ~IXP4XX_OST_ENABLE;
*IXP4XX_OSRT1 = osrt | opts;
return 0;
}
static int ixp4xx_set_oneshot(struct clock_event_device *evt)
{
unsigned long opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT;
unsigned long osrt = 0;
/* period set by 'set next_event' */
*IXP4XX_OSRT1 = osrt | opts;
return 0;
}
static int ixp4xx_set_periodic(struct clock_event_device *evt)
{
unsigned long opts = IXP4XX_OST_ENABLE;
unsigned long osrt = IXP4XX_LATCH & ~IXP4XX_OST_RELOAD_MASK;
*IXP4XX_OSRT1 = osrt | opts;
return 0;
}
static int ixp4xx_resume(struct clock_event_device *evt)
{
unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
opts |= IXP4XX_OST_ENABLE;
*IXP4XX_OSRT1 = osrt | opts;
return 0;
}
static struct clock_event_device clockevent_ixp4xx = {
.name = "ixp4xx timer1",
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.rating = 200,
.set_mode = ixp4xx_set_mode,
.set_next_event = ixp4xx_set_next_event,
.name = "ixp4xx timer1",
.features = CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_ONESHOT,
.rating = 200,
.set_state_shutdown = ixp4xx_shutdown,
.set_state_periodic = ixp4xx_set_periodic,
.set_state_oneshot = ixp4xx_set_oneshot,
.tick_resume = ixp4xx_resume,
.set_next_event = ixp4xx_set_next_event,
};
static void __init ixp4xx_clockevent_init(void)
......
arch/arm/mach-ks8695/irq.c
View file @ c5fc2498
......@@ -172,6 +172,6 @@ void __init ks8695_init_irq(void)
handle_edge_irq);
}
set_irq_flags(irq, IRQF_VALID);
irq_clear_status_flags(irq, IRQ_NOREQUEST);
}
}
arch/arm/mach-ks8695/time.c
View file @ c5fc2498
......@@ -54,28 +54,25 @@
/* Timer0 Timeout Counter Register */
#define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */
static void ks8695_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
static int ks8695_set_periodic(struct clock_event_device *evt)
{
u32 rate = DIV_ROUND_CLOSEST(KS8695_CLOCK_RATE, HZ);
u32 half = DIV_ROUND_CLOSEST(rate, 2);
u32 tmcon;
if (mode == CLOCK_EVT_FEAT_PERIODIC) {
u32 rate = DIV_ROUND_CLOSEST(KS8695_CLOCK_RATE, HZ);
u32 half = DIV_ROUND_CLOSEST(rate, 2);
/* Disable timer 1 */
tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
tmcon &= ~TMCON_T1EN;
writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
/* Disable timer 1 */
tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
tmcon &= ~TMCON_T1EN;
writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
/* Both registers need to count down */
writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
/* Both registers need to count down */
writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
/* Re-enable timer1 */
tmcon |= TMCON_T1EN;
writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
}
/* Re-enable timer1 */
tmcon |= TMCON_T1EN;
writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
return 0;
}
static int ks8695_set_next_event(unsigned long cycles,
......@@ -102,11 +99,13 @@ static int ks8695_set_next_event(unsigned long cycles,
}
static struct clock_event_device clockevent_ks8695 = {
.name = "ks8695_t1tc",
.rating = 300, /* Reasonably fast and accurate clock event */
.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
.set_next_event = ks8695_set_next_event,
.set_mode = ks8695_set_mode,
.name = "ks8695_t1tc",
/* Reasonably fast and accurate clock event */
.rating = 300,
.features = CLOCK_EVT_FEAT_ONESHOT |
CLOCK_EVT_FEAT_PERIODIC,
.set_next_event = ks8695_set_next_event,
.set_state_periodic = ks8695_set_periodic,
};
/*
......
arch/arm/mach-lpc32xx/irq.c
View file @ c5fc2498
......@@ -283,25 +283,25 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type)
case IRQ_TYPE_EDGE_RISING:
/* Rising edge sensitive */
__lpc32xx_set_irq_type(d->hwirq, 1, 1);
__irq_set_handler_locked(d->irq, handle_edge_irq);
irq_set_handler_locked(d, handle_edge_irq);
break;
case IRQ_TYPE_EDGE_FALLING:
/* Falling edge sensitive */
__lpc32xx_set_irq_type(d->hwirq, 0, 1);
__irq_set_handler_locked(d->irq, handle_edge_irq);
irq_set_handler_locked(d, handle_edge_irq);
break;
case IRQ_TYPE_LEVEL_LOW:
/* Low level sensitive */
__lpc32xx_set_irq_type(d->hwirq, 0, 0);
__irq_set_handler_locked(d->irq, handle_level_irq);
irq_set_handler_locked(d, handle_level_irq);
break;
case IRQ_TYPE_LEVEL_HIGH:
/* High level sensitive */
__lpc32xx_set_irq_type(d->hwirq, 1, 0);
__irq_set_handler_locked(d->irq, handle_level_irq);
irq_set_handler_locked(d, handle_level_irq);
break;
/* Other modes are not supported */
......@@ -434,7 +434,7 @@ void __init lpc32xx_init_irq(void)
for (i = 0; i < NR_IRQS; i++) {
irq_set_chip_and_handler(i, &lpc32xx_irq_chip,
handle_level_irq);
set_irq_flags(i, IRQF_VALID);
irq_clear_status_flags(i, IRQ_NOREQUEST);
}
/* Set default mappings */
......
arch/arm/mach-lpc32xx/phy3250.c
View file @ c5fc2498
......@@ -212,7 +212,7 @@ static struct lpc32xx_mlc_platform_data lpc32xx_mlc_data = {
.dma_filter = pl08x_filter_id,
};
static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
static const struct of_dev_auxdata const lpc32xx_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", NULL),
OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", NULL),
OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data),
......@@ -248,7 +248,7 @@ static void __init lpc3250_machine_init(void)
lpc32xx_auxdata_lookup, NULL);
}
static char const *lpc32xx_dt_compat[] __initdata = {
static const char *const lpc32xx_dt_compat[] __initconst = {
"nxp,lpc3220",
"nxp,lpc3230",
"nxp,lpc3240",
......
arch/arm/mach-lpc32xx/timer.c
View file @ c5fc2498
......@@ -43,36 +43,24 @@ static int lpc32xx_clkevt_next_event(unsigned long delta,
return 0;
}
static void lpc32xx_clkevt_mode(enum clock_event_mode mode,
struct clock_event_device *dev)
static int lpc32xx_shutdown(struct clock_event_device *evt)
{
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
WARN_ON(1);
break;
case CLOCK_EVT_MODE_ONESHOT:
case CLOCK_EVT_MODE_SHUTDOWN:
/*
* Disable the timer. When using oneshot, we must also
* disable the timer to wait for the first call to
* set_next_event().
*/
__raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_RESUME:
break;
}
/*
* Disable the timer. When using oneshot, we must also
* disable the timer to wait for the first call to
* set_next_event().
*/
__raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
return 0;
}
static struct clock_event_device lpc32xx_clkevt = {
.name = "lpc32xx_clkevt",
.features = CLOCK_EVT_FEAT_ONESHOT,
.rating = 300,
.set_next_event = lpc32xx_clkevt_next_event,
.set_mode = lpc32xx_clkevt_mode,
.name = "lpc32xx_clkevt",
.features = CLOCK_EVT_FEAT_ONESHOT,
.rating = 300,
.set_next_event = lpc32xx_clkevt_next_event,
.set_state_shutdown = lpc32xx_shutdown,
.set_state_oneshot = lpc32xx_shutdown,
};
static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id)
......
arch/arm/mach-mmp/mmp-dt.c
View file @ c5fc2498
......@@ -20,12 +20,12 @@
extern void __init mmp_dt_init_timer(void);
static const char *pxa168_dt_board_compat[] __initdata = {
static const char *const pxa168_dt_board_compat[] __initconst = {
"mrvl,pxa168-aspenite",
NULL,
};
static const char *pxa910_dt_board_compat[] __initdata = {
static const char *const pxa910_dt_board_compat[] __initconst = {
"mrvl,pxa910-dkb",
NULL,
};
......
arch/arm/mach-mmp/mmp2-dt.c
View file @ c5fc2498
......@@ -30,7 +30,7 @@ static void __init mmp_init_time(void)
of_clk_init(NULL);
}
static const char *mmp2_dt_board_compat[] __initdata = {
static const char *const mmp2_dt_board_compat[] __initconst = {
"mrvl,mmp2-brownstone",
NULL,
};
......
arch/arm/mach-mmp/time.c
View file @ c5fc2498
......@@ -124,32 +124,25 @@ static int timer_set_next_event(unsigned long delta,
return 0;
}
static void timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *dev)
static int timer_set_shutdown(struct clock_event_device *evt)
{
unsigned long flags;
local_irq_save(flags);
switch (mode) {
case CLOCK_EVT_MODE_ONESHOT:
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
/* disable the matching interrupt */
__raw_writel(0x00, mmp_timer_base + TMR_IER(0));
break;
case CLOCK_EVT_MODE_RESUME:
case CLOCK_EVT_MODE_PERIODIC:
break;
}
/* disable the matching interrupt */
__raw_writel(0x00, mmp_timer_base + TMR_IER(0));
local_irq_restore(flags);
return 0;
}
static struct clock_event_device ckevt = {
.name = "clockevent",
.features = CLOCK_EVT_FEAT_ONESHOT,
.rating = 200,
.set_next_event = timer_set_next_event,
.set_mode = timer_set_mode,
.name = "clockevent",
.features = CLOCK_EVT_FEAT_ONESHOT,
.rating = 200,
.set_next_event = timer_set_next_event,
.set_state_shutdown = timer_set_shutdown,
.set_state_oneshot = timer_set_shutdown,
};
static cycle_t clksrc_read(struct clocksource *cs)
......
arch/arm/mach-mvebu/pmsu.c
View file @ c5fc2498
......@@ -415,7 +415,7 @@ static __init int armada_38x_cpuidle_init(void)
void __iomem *mpsoc_base;
u32 reg;
pr_warn("CPU idle is currently broken on Armada 38x: disabling");
pr_warn("CPU idle is currently broken on Armada 38x: disabling\n");
return 0;
np = of_find_compatible_node(NULL, NULL,
......@@ -486,7 +486,7 @@ static int __init mvebu_v7_cpu_pm_init(void)
*/
if (of_machine_is_compatible("marvell,armada380")) {
cpu_hotplug_disable();
pr_warn("CPU hotplug support is currently broken on Armada 38x: disabling");
pr_warn("CPU hotplug support is currently broken on Armada 38x: disabling\n");
}
if (of_machine_is_compatible("marvell,armadaxp"))
......
arch/arm/mach-mxs/mach-mxs.c
View file @ c5fc2498
......@@ -282,7 +282,7 @@ static void __init apx4devkit_init(void)
#define TX28_FEC_PHY_RESET MXS_GPIO_NR(4, 13)
#define TX28_FEC_nINT MXS_GPIO_NR(4, 5)
static const struct gpio tx28_gpios[] __initconst = {
static const struct gpio const tx28_gpios[] __initconst = {
{ ENET0_MDC__GPIO_4_0, GPIOF_OUT_INIT_LOW, "GPIO_4_0" },
{ ENET0_MDIO__GPIO_4_1, GPIOF_OUT_INIT_LOW, "GPIO_4_1" },
{ ENET0_RX_EN__GPIO_4_2, GPIOF_OUT_INIT_LOW, "GPIO_4_2" },
......@@ -528,7 +528,7 @@ static void mxs_restart(enum reboot_mode mode, const char *cmd)
soft_restart(0);
}
static const char *mxs_dt_compat[] __initdata = {
static const char *const mxs_dt_compat[] __initconst = {
"fsl,imx28",
"fsl,imx23",
NULL,
......
arch/arm/mach-netx/generic.c
View file @ c5fc2498
......@@ -174,7 +174,7 @@ void __init netx_init_irq(void)
for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
irq_set_chip_and_handler(irq, &netx_hif_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
irq_clear_status_flags(irq, IRQ_NOREQUEST);
}
writel(NETX_DPMAS_INT_EN_GLB_EN, NETX_DPMAS_INT_EN);
......
arch/arm/mach-netx/time.c
View file @ c5fc2498
......@@ -34,40 +34,40 @@
#define TIMER_CLOCKEVENT 0
#define TIMER_CLOCKSOURCE 1
static void netx_set_mode(enum clock_event_mode mode,
struct clock_event_device *clk)
static inline void timer_shutdown(struct clock_event_device *evt)
{
u32 tmode;
/* disable timer */
writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT));
}
static int netx_shutdown(struct clock_event_device *evt)
{
timer_shutdown(evt);
return 0;
}
static int netx_set_oneshot(struct clock_event_device *evt)
{
u32 tmode = NETX_GPIO_COUNTER_CTRL_IRQ_EN | NETX_GPIO_COUNTER_CTRL_RUN;
timer_shutdown(evt);
writel(0, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT));
writel(tmode, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT));
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT));
tmode = NETX_GPIO_COUNTER_CTRL_RST_EN |
NETX_GPIO_COUNTER_CTRL_IRQ_EN |
NETX_GPIO_COUNTER_CTRL_RUN;
break;
case CLOCK_EVT_MODE_ONESHOT:
writel(0, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT));
tmode = NETX_GPIO_COUNTER_CTRL_IRQ_EN |
NETX_GPIO_COUNTER_CTRL_RUN;
break;
default:
WARN(1, "%s: unhandled mode %d\n", __func__, mode);
/* fall through */
case CLOCK_EVT_MODE_SHUTDOWN:
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_RESUME:
tmode = 0;
break;
}
return 0;
}
static int netx_set_periodic(struct clock_event_device *evt)
{
u32 tmode = NETX_GPIO_COUNTER_CTRL_RST_EN |
NETX_GPIO_COUNTER_CTRL_IRQ_EN | NETX_GPIO_COUNTER_CTRL_RUN;
timer_shutdown(evt);
writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT));
writel(tmode, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT));
return 0;
}
static int netx_set_next_event(unsigned long evt,
......@@ -81,7 +81,10 @@ static struct clock_event_device netx_clockevent = {
.name = "netx-timer" __stringify(TIMER_CLOCKEVENT),
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.set_next_event = netx_set_next_event,
.set_mode = netx_set_mode,
.set_state_shutdown = netx_shutdown,
.set_state_periodic = netx_set_periodic,
.set_state_oneshot = netx_set_oneshot,
.tick_resume = netx_shutdown,
};
/*
......
arch/arm/mach-nomadik/cpu-8815.c
View file @ c5fc2498
......@@ -26,10 +26,8 @@
#include <linux/irq.h>
#include <linux/dma-mapping.h>
#include <linux/of_irq.h>
#include <linux/of_gpio.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/gpio.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
......@@ -109,40 +107,6 @@ static void cpu8815_restart(enum reboot_mode mode, const char *cmd)
writel(1, srcbase + 0x18);
}
/*
* This GPIO pin turns on a line that is used to detect card insertion
* on this board.
*/
static int __init cpu8815_mmcsd_init(void)
{
struct device_node *cdbias;
int gpio, err;
cdbias = of_find_node_by_path("/usb-s8815/mmcsd-gpio");
if (!cdbias) {
pr_info("could not find MMC/SD card detect bias node\n");
return 0;
}
gpio = of_get_gpio(cdbias, 0);
if (gpio < 0) {
pr_info("could not obtain MMC/SD card detect bias GPIO\n");
return 0;
}
err = gpio_request(gpio, "card detect bias");
if (err) {
pr_info("failed to request card detect bias GPIO %d\n", gpio);
return -ENODEV;
}
err = gpio_direction_output(gpio, 0);
if (err){
pr_info("failed to set GPIO %d as output, low\n", gpio);
return err;
}
pr_info("enabled USB-S8815 CD bias GPIO %d, low\n", gpio);
return 0;
}
device_initcall(cpu8815_mmcsd_init);
static const char * cpu8815_board_compat[] = {
"st,nomadik-nhk-15",
"calaosystems,usb-s8815",
......@@ -150,9 +114,8 @@ static const char * cpu8815_board_compat[] = {
};
DT_MACHINE_START(NOMADIK_DT, "Nomadik STn8815")
/* At full speed latency must be >=2, so 0x249 in low bits */
.l2c_aux_val = 0x00700249,
.l2c_aux_mask = 0xfe0fefff,
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
.map_io = cpu8815_map_io,
.restart = cpu8815_restart,
.dt_compat = cpu8815_board_compat,
......
arch/arm/mach-omap1/fpga.c
View file @ c5fc2498
......@@ -169,7 +169,7 @@ void omap1510_fpga_init_irq(void)
}
irq_set_handler(i, handle_edge_irq);
set_irq_flags(i, IRQF_VALID);
irq_clear_status_flags(i, IRQ_NOREQUEST);
}
/*
......
arch/arm/mach-omap1/irq.c
View file @ c5fc2498
......@@ -262,7 +262,7 @@ void __init omap1_init_irq(void)
irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
omap_irq_set_cfg(j, 0, 0, irq_trigger);
set_irq_flags(j, IRQF_VALID);
irq_clear_status_flags(j, IRQ_NOREQUEST);
}
omap_alloc_gc(irq_banks[i].va, irq_base + i * 32, 32);
}
......
arch/arm/mach-omap1/time.c
View file @ c5fc2498
......@@ -124,29 +124,26 @@ static int omap_mpu_set_next_event(unsigned long cycles,
return 0;
}
static void omap_mpu_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
static int omap_mpu_set_oneshot(struct clock_event_device *evt)
{
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
omap_mpu_set_autoreset(0);
break;
case CLOCK_EVT_MODE_ONESHOT:
omap_mpu_timer_stop(0);
omap_mpu_remove_autoreset(0);
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
case CLOCK_EVT_MODE_RESUME:
break;
}
omap_mpu_timer_stop(0);
omap_mpu_remove_autoreset(0);
return 0;
}
static int omap_mpu_set_periodic(struct clock_event_device *evt)
{
omap_mpu_set_autoreset(0);
return 0;
}
static struct clock_event_device clockevent_mpu_timer1 = {
.name = "mpu_timer1",
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.set_next_event = omap_mpu_set_next_event,
.set_mode = omap_mpu_set_mode,
.name = "mpu_timer1",
.features = CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_ONESHOT,
.set_next_event = omap_mpu_set_next_event,
.set_state_periodic = omap_mpu_set_periodic,
.set_state_oneshot = omap_mpu_set_oneshot,
};
static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id)
......
arch/arm/mach-omap1/timer32k.c
View file @ c5fc2498
......@@ -114,29 +114,28 @@ static int omap_32k_timer_set_next_event(unsigned long delta,
return 0;
}
static void omap_32k_timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
static int omap_32k_timer_shutdown(struct clock_event_device *evt)
{
omap_32k_timer_stop();
return 0;
}
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
break;
case CLOCK_EVT_MODE_ONESHOT:
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
break;
case CLOCK_EVT_MODE_RESUME:
break;
}
static int omap_32k_timer_set_periodic(struct clock_event_device *evt)
{
omap_32k_timer_stop();
omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
return 0;
}
static struct clock_event_device clockevent_32k_timer = {
.name = "32k-timer",
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.set_next_event = omap_32k_timer_set_next_event,
.set_mode = omap_32k_timer_set_mode,
.name = "32k-timer",
.features = CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_ONESHOT,
.set_next_event = omap_32k_timer_set_next_event,
.set_state_shutdown = omap_32k_timer_shutdown,
.set_state_periodic = omap_32k_timer_set_periodic,
.set_state_oneshot = omap_32k_timer_shutdown,
.tick_resume = omap_32k_timer_shutdown,
};
static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id)
......
arch/arm/mach-omap2/Kconfig
View file @ c5fc2498
......@@ -178,26 +178,6 @@ config MACH_OMAP_LDP
default y
select OMAP_PACKAGE_CBB
config MACH_OMAP3530_LV_SOM
bool "OMAP3 Logic 3530 LV SOM board"
depends on ARCH_OMAP3
default y
select OMAP_PACKAGE_CBB
help
Support for the LogicPD OMAP3530 SOM Development kit
for full description please see the products webpage at
http://www.logicpd.com/products/development-kits/texas-instruments-zoom%E2%84%A2-omap35x-development-kit
config MACH_OMAP3_TORPEDO
bool "OMAP3 Logic 35x Torpedo board"
depends on ARCH_OMAP3
default y
select OMAP_PACKAGE_CBB
help
Support for the LogicPD OMAP35x Torpedo Development kit
for full description please see the products webpage at
http://www.logicpd.com/products/development-kits/zoom-omap35x-torpedo-development-kit
config MACH_OMAP3517EVM
bool "OMAP3517/ AM3517 EVM board"
depends on ARCH_OMAP3
......
arch/arm/mach-omap2/Makefile
View file @ c5fc2498
......@@ -235,9 +235,6 @@ obj-$(CONFIG_SOC_OMAP2420) += msdi.o
# Specific board support
obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o pdata-quirks.o
obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o
obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o
obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o
obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o
obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o
obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o sdram-nokia.o
obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-peripherals.o
......
arch/arm/mach-omap2/board-omap3logic.c deleted 100644 → 0
View file @ 00e3fcc2
/*
* linux/arch/arm/mach-omap2/board-omap3logic.c
*
* Copyright (C) 2010 Li-Pro.Net
* Stephan Linz <linz@li-pro.net>
*
* Copyright (C) 2010-2012 Logic Product Development, Inc.
* Peter Barada <peter.barada@logicpd.com>
* Ashwin BIhari <ashwin.bihari@logicpd.com>
*
* Modified from Beagle, EVM, and RX51
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/i2c/twl.h>
#include <linux/mmc/host.h>
#include <linux/usb/phy.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include "common.h"
#include "mux.h"
#include "hsmmc.h"
#include "control.h"
#include "common-board-devices.h"
#include "gpmc.h"
#include "gpmc-smsc911x.h"
#define OMAP3LOGIC_SMSC911X_CS 1
#define OMAP3530_LV_SOM_MMC_GPIO_CD 110
#define OMAP3530_LV_SOM_MMC_GPIO_WP 126
#define OMAP3530_LV_SOM_SMSC911X_GPIO_IRQ 152
#define OMAP3_TORPEDO_MMC_GPIO_CD 127
#define OMAP3_TORPEDO_SMSC911X_GPIO_IRQ 129
static struct regulator_consumer_supply omap3logic_vmmc1_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
static struct regulator_init_data omap3logic_vmmc1 = {
.constraints = {
.name = "VMMC1",
.min_uV = 1850000,
.max_uV = 3150000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(omap3logic_vmmc1_supply),
.consumer_supplies = omap3logic_vmmc1_supply,
};
static struct twl4030_gpio_platform_data omap3logic_gpio_data = {
.use_leds = true,
.pullups = BIT(1),
.pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8)
| BIT(13) | BIT(15) | BIT(16) | BIT(17),
};
static struct twl4030_usb_data omap3logic_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
static struct twl4030_platform_data omap3logic_twldata = {
/* platform_data for children goes here */
.gpio = &omap3logic_gpio_data,
.vmmc1 = &omap3logic_vmmc1,
.usb = &omap3logic_usb_data,
};
static int __init omap3logic_i2c_init(void)
{
omap3_pmic_init("twl4030", &omap3logic_twldata);
return 0;
}
static struct omap2_hsmmc_info __initdata board_mmc_info[] = {
{
.name = "external",
.mmc = 1,
.caps = MMC_CAP_4_BIT_DATA,
.gpio_cd = -EINVAL,
.gpio_wp = -EINVAL,
},
{} /* Terminator */
};
static void __init board_mmc_init(void)
{
if (machine_is_omap3530_lv_som()) {
/* OMAP3530 LV SOM board */
board_mmc_info[0].gpio_cd = OMAP3530_LV_SOM_MMC_GPIO_CD;
board_mmc_info[0].gpio_wp = OMAP3530_LV_SOM_MMC_GPIO_WP;
omap_mux_init_signal("gpio_110", OMAP_PIN_OUTPUT);
omap_mux_init_signal("gpio_126", OMAP_PIN_OUTPUT);
} else if (machine_is_omap3_torpedo()) {
/* OMAP3 Torpedo board */
board_mmc_info[0].gpio_cd = OMAP3_TORPEDO_MMC_GPIO_CD;
omap_mux_init_signal("gpio_127", OMAP_PIN_OUTPUT);
} else {
/* unsupported board */
printk(KERN_ERR "%s(): unknown machine type\n", __func__);
return;
}
omap_hsmmc_init(board_mmc_info);
}
static struct omap_smsc911x_platform_data __initdata board_smsc911x_data = {
.cs = OMAP3LOGIC_SMSC911X_CS,
.gpio_irq = -EINVAL,
.gpio_reset = -EINVAL,
};
/* TODO/FIXME (comment by Peter Barada, LogicPD):
* Fix the PBIAS voltage for Torpedo MMC1 pins that
* are used for other needs (IRQs, etc). */
static void omap3torpedo_fix_pbias_voltage(void)
{
u16 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
u32 reg;
if (machine_is_omap3_torpedo())
{
/* Set the bias for the pin */
reg = omap_ctrl_readl(control_pbias_offset);
reg &= ~OMAP343X_PBIASLITEPWRDNZ1;
omap_ctrl_writel(reg, control_pbias_offset);
/* 100ms delay required for PBIAS configuration */
msleep(100);
reg |= OMAP343X_PBIASLITEVMODE1;
reg |= OMAP343X_PBIASLITEPWRDNZ1;
omap_ctrl_writel(reg | 0x300, control_pbias_offset);
}
}
static inline void __init board_smsc911x_init(void)
{
if (machine_is_omap3530_lv_som()) {
/* OMAP3530 LV SOM board */
board_smsc911x_data.gpio_irq =
OMAP3530_LV_SOM_SMSC911X_GPIO_IRQ;
omap_mux_init_signal("gpio_152", OMAP_PIN_INPUT);
} else if (machine_is_omap3_torpedo()) {
/* OMAP3 Torpedo board */
board_smsc911x_data.gpio_irq = OMAP3_TORPEDO_SMSC911X_GPIO_IRQ;
omap_mux_init_signal("gpio_129", OMAP_PIN_INPUT);
} else {
/* unsupported board */
printk(KERN_ERR "%s(): unknown machine type\n", __func__);
return;
}
gpmc_smsc911x_init(&board_smsc911x_data);
}
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
/* mUSB */
OMAP3_MUX(HSUSB0_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_STP, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(HSUSB0_DIR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_NXT, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#endif
static struct regulator_consumer_supply dummy_supplies[] = {
REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
};
static void __init omap3logic_init(void)
{
regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap3torpedo_fix_pbias_voltage();
omap3logic_i2c_init();
omap_serial_init();
omap_sdrc_init(NULL, NULL);
board_mmc_init();
board_smsc911x_init();
usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
usb_musb_init(NULL);
/* Ensure SDRC pins are mux'd for self-refresh */
omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
}
MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
.atag_offset = 0x100,
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = omap35xx_init_early,
.init_irq = omap3_init_irq,
.init_machine = omap3logic_init,
.init_late = omap35xx_init_late,
.init_time = omap3_sync32k_timer_init,
.restart = omap3xxx_restart,
MACHINE_END
MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
.atag_offset = 0x100,
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = omap35xx_init_early,
.init_irq = omap3_init_irq,
.init_machine = omap3logic_init,
.init_late = omap35xx_init_late,
.init_time = omap3_sync32k_timer_init,
.restart = omap3xxx_restart,
MACHINE_END
arch/arm/mach-omap2/board-omap3pandora.c deleted 100644 → 0
View file @ 00e3fcc2
This diff is collapsed.
arch/arm/mach-omap2/prm_common.c
View file @ c5fc2498
......@@ -705,7 +705,7 @@ static struct omap_prcm_init_data scrm_data __initdata = {
};
#endif
static const struct of_device_id omap_prcm_dt_match_table[] __initconst = {
static const struct of_device_id const omap_prcm_dt_match_table[] __initconst = {
#ifdef CONFIG_SOC_AM33XX
{ .compatible = "ti,am3-prcm", .data = &am3_prm_data },
#endif
......
arch/arm/mach-omap2/timer.c
View file @ c5fc2498
......@@ -102,38 +102,38 @@ static int omap2_gp_timer_set_next_event(unsigned long cycles,
return 0;
}
static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
static int omap2_gp_timer_shutdown(struct clock_event_device *evt)
{
__omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
return 0;
}
static int omap2_gp_timer_set_periodic(struct clock_event_device *evt)
{
u32 period;
__omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
period = clkev.rate / HZ;
period -= 1;
/* Looks like we need to first set the load value separately */
__omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
0xffffffff - period, OMAP_TIMER_POSTED);
__omap_dm_timer_load_start(&clkev,
OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
0xffffffff - period, OMAP_TIMER_POSTED);
break;
case CLOCK_EVT_MODE_ONESHOT:
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
case CLOCK_EVT_MODE_RESUME:
break;
}
period = clkev.rate / HZ;
period -= 1;
/* Looks like we need to first set the load value separately */
__omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 0xffffffff - period,
OMAP_TIMER_POSTED);
__omap_dm_timer_load_start(&clkev,
OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
0xffffffff - period, OMAP_TIMER_POSTED);
return 0;
}
static struct clock_event_device clockevent_gpt = {
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.rating = 300,
.set_next_event = omap2_gp_timer_set_next_event,
.set_mode = omap2_gp_timer_set_mode,
.features = CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_ONESHOT,
.rating = 300,
.set_next_event = omap2_gp_timer_set_next_event,
.set_state_shutdown = omap2_gp_timer_shutdown,
.set_state_periodic = omap2_gp_timer_set_periodic,
.set_state_oneshot = omap2_gp_timer_shutdown,
.tick_resume = omap2_gp_timer_shutdown,
};
static struct property device_disabled = {
......
arch/arm/mach-omap2/vc.c
View file @ c5fc2498
......@@ -563,7 +563,7 @@ struct i2c_init_data {
u8 hsscll_12;
};
static const __initdata struct i2c_init_data omap4_i2c_timing_data[] = {
static const struct i2c_init_data const omap4_i2c_timing_data[] __initconst = {
{
.load = 50,
.loadbits = 0x3,
......
arch/arm/mach-omap2/voltagedomains3xxx_data.c
View file @ c5fc2498
......@@ -95,7 +95,7 @@ static struct voltagedomain *voltagedomains_am35xx[] __initdata = {
};
static const char *sys_clk_name __initdata = "sys_ck";
static const char *const sys_clk_name __initconst = "sys_ck";
void __init omap3xxx_voltagedomains_init(void)
{
......
arch/arm/mach-omap2/voltagedomains44xx_data.c
View file @ c5fc2498
......@@ -92,7 +92,7 @@ static struct voltagedomain *voltagedomains_omap4[] __initdata = {
NULL,
};
static const char *sys_clk_name __initdata = "sys_clkin_ck";
static const char *const sys_clk_name __initconst = "sys_clkin_ck";
void __init omap44xx_voltagedomains_init(void)
{
......
arch/arm/mach-omap2/voltagedomains54xx_data.c
View file @ c5fc2498
......@@ -78,7 +78,7 @@ static struct voltagedomain *voltagedomains_omap5[] __initdata = {
NULL,
};
static const char *sys_clk_name __initdata = "sys_clkin";
static const char *const sys_clk_name __initconst = "sys_clkin";
void __init omap54xx_voltagedomains_init(void)
{
......
arch/arm/mach-orion5x/dns323-setup.c
View file @ c5fc2498
......@@ -236,9 +236,7 @@ static int __init dns323_read_mac_addr(void)
}
iounmap(mac_page);
printk("DNS-323: Found ethernet MAC address: ");
for (i = 0; i < 6; i++)
printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n");
printk("DNS-323: Found ethernet MAC address: %pM\n", addr);
memcpy(dns323_eth_data.mac_addr, addr, 6);
......
arch/arm/mach-orion5x/tsx09-common.c
View file @ c5fc2498
......@@ -101,9 +101,7 @@ static int __init qnap_tsx09_check_mac_addr(const char *addr_str)
addr[i] = byte;
}
printk(KERN_INFO "tsx09: found ethernet mac address ");
for (i = 0; i < 6; i++)
printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n");
printk(KERN_INFO "tsx09: found ethernet mac address %pM\n", addr);
memcpy(qnap_tsx09_eth_data.mac_addr, addr, 6);
......
arch/arm/mach-pxa/balloon3.c
View file @ c5fc2498
......@@ -496,18 +496,18 @@ static struct irq_chip balloon3_irq_chip = {
.irq_unmask = balloon3_unmask_irq,
};
static void balloon3_irq_handler(unsigned int irq, struct irq_desc *desc)
static void balloon3_irq_handler(unsigned int __irq, struct irq_desc *desc)
{
unsigned long pending = __raw_readl(BALLOON3_INT_CONTROL_REG) &
balloon3_irq_enabled;
do {
/* clear useless edge notification */
if (desc->irq_data.chip->irq_ack) {
struct irq_data *d;
struct irq_data *d = irq_desc_get_irq_data(desc);
struct irq_chip *chip = irq_data_get_chip(d);
unsigned int irq;
d = irq_get_irq_data(BALLOON3_AUX_NIRQ);
desc->irq_data.chip->irq_ack(d);
}
/* clear useless edge notification */
if (chip->irq_ack)
chip->irq_ack(d);
while (pending) {
irq = BALLOON3_IRQ(0) + __ffs(pending);
......@@ -528,7 +528,7 @@ static void __init balloon3_init_irq(void)
for (irq = BALLOON3_IRQ(0); irq <= BALLOON3_IRQ(7); irq++) {
irq_set_chip_and_handler(irq, &balloon3_irq_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
}
irq_set_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler);
......
arch/arm/mach-pxa/cm-x2xx-pci.c
View file @ c5fc2498
......@@ -29,8 +29,9 @@
void __iomem *it8152_base_address;
static int cmx2xx_it8152_irq_gpio;
static void cmx2xx_it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
static void cmx2xx_it8152_irq_demux(unsigned int __irq, struct irq_desc *desc)
{
unsigned int irq = irq_desc_get_irq(desc);
/* clear our parent irq */
desc->irq_data.chip->irq_ack(&desc->irq_data);
......
arch/arm/mach-pxa/irq.c
View file @ c5fc2498
......@@ -133,7 +133,6 @@ static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
irq_set_chip_and_handler(virq, &pxa_internal_irq_chip,
handle_level_irq);
irq_set_chip_data(virq, base);
set_irq_flags(virq, IRQF_VALID);
return 0;
}
......
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