[PATCH] sn: Added call to pcireg_intr_status_get

From: Pat Gefre <pfg@sgi.com>

Added call to pcireg_intr_status_get

arch/ia64/sn/io/sn2/pcibr/pcibr_reg.c

@@ -6,7 +6,6 @@
  * Copyright (C) 2003 Silicon Graphics, Inc. All rights reserved.
  */
 
-
 #include <linux/types.h>
 #include <asm/sn/sgi.h>
 #include <asm/sn/iograph.h>
@@ -24,51 +23,70 @@
 uint64_t
 pcireg_control_get(void *ptr)
 {
-	uint64_t    ret = 0;
-	pic_t       *bridge;
+	uint64_t ret = 0;
+	pic_t *bridge;
+
+	if (IS_IOADDR(ptr))
+		bridge = (pic_t *) ptr;
+	else
+		bridge = (pic_t *) ((pcibr_soft_t) (ptr))->bs_base;
+
+	ret = ((pic_t *) bridge)->p_wid_control;
+	return ret;
+}
+
+/*
+ * Interrupt Status Register Access -- Read Only                    0000_0100
+ */
+uint64_t
+pcireg_intr_status_get(void *ptr)
+{
+	short bridge_type;
+	pic_t *bridge;
+	uint64_t ret = 0;
 
-	if ( IS_IOADDR(ptr) )
-		bridge = (pic_t *)ptr;
+	if (IS_IOADDR(ptr))
+		bridge = (pic_t *) ptr;
 	else
-		bridge = (pic_t *)((pcibr_soft_t)(ptr))->bs_base;
+		bridge = (pic_t *) ((pcibr_soft_t) (ptr))->bs_base;
 
-	ret = ((pic_t *)bridge)->p_wid_control;
+	ret = ((pic_t *) bridge)->p_int_status;
 	return ret;
 }
 
 void
 pcireg_intr_enable_bit_clr(void *ptr, uint64_t bits)
 {
-	pic_t       *bridge;
+	pic_t *bridge;
 
-	if ( IS_IOADDR(ptr) )
-		bridge = (pic_t *)ptr;
+	if (IS_IOADDR(ptr))
+		bridge = (pic_t *) ptr;
 	else
-		bridge = (pic_t *)((pcibr_soft_t)(ptr))->bs_base;
+		bridge = (pic_t *) ((pcibr_soft_t) (ptr))->bs_base;
 	bridge->p_int_enable &= ~bits;
 }
 
 void
 pcireg_intr_enable_bit_set(void *ptr, uint64_t bits)
 {
-	pic_t       *bridge;
+	pic_t *bridge;
 
-	if ( IS_IOADDR(ptr) )
-		bridge = (pic_t *)ptr;
+	if (IS_IOADDR(ptr))
+		bridge = (pic_t *) ptr;
 	else
-		bridge = (pic_t *)((pcibr_soft_t)(ptr))->bs_base;
+		bridge = (pic_t *) ((pcibr_soft_t) (ptr))->bs_base;
 	bridge->p_int_enable |= bits;
 }
 
 void
 pcireg_intr_addr_addr_set(void *ptr, int int_n, uint64_t addr)
 {
-	pic_t       *bridge;
+	pic_t *bridge;
 
-	if ( IS_IOADDR(ptr) )
-		bridge = (pic_t *)ptr;
+	if (IS_IOADDR(ptr))
+		bridge = (pic_t *) ptr;
 	else
-		bridge = (pic_t *)((pcibr_soft_t)(ptr))->bs_base;
+		bridge = (pic_t *) ((pcibr_soft_t) (ptr))->bs_base;
 	bridge->p_int_addr[int_n] &= ~(0x0000FFFFFFFFFFFF);
 	bridge->p_int_addr[int_n] |= (addr & 0x0000FFFFFFFFFFFF);
 }
@@ -79,11 +97,11 @@ pcireg_intr_addr_addr_set(void *ptr, int int_n, uint64_t addr)
 void
 pcireg_force_intr_set(void *ptr, int int_n)
 {
-	pic_t       *bridge;
+	pic_t *bridge;
 
-	if ( IS_IOADDR(ptr) )
-		bridge = (pic_t *)ptr;
+	if (IS_IOADDR(ptr))
+		bridge = (pic_t *) ptr;
 	else
-		bridge = (pic_t *)((pcibr_soft_t)(ptr))->bs_base;
-        bridge->p_force_pin[int_n] = 1;
+		bridge = (pic_t *) ((pcibr_soft_t) (ptr))->bs_base;
+	bridge->p_force_pin[int_n] = 1;
 }

arch/ia64/sn/kernel/irq.c

@@ -262,7 +262,7 @@ sn_check_intr(int irq, pcibr_intr_t intr) {
 	unsigned long irr_reg;
 
 
-	regval = intr->bi_soft->bs_base->p_int_status_64;
+	regval = pcireg_intr_status_get(intr->bi_soft->bs_base);
 	irr_reg_num = irq_to_vector(irq) / 64;
 	irr_bit = irq_to_vector(irq) % 64;
 	switch (irr_reg_num) {