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Commit cc0c832f authored by Tony Lindgren's avatar Tony Lindgren Committed by Russell King
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[ARM PATCH] 2164/1: OMAP update 3/8: Include files 

Patch from Tony Lindgren

This patch syncs the mainline kernel with the linux-omap tree.
The highlights of the patch are:
- Collapse OMAP 1610, 6912 and 1710 into one processor group 16xx
- USB updates by David Brownell
- Pin multiplexing updates by David Brownell
- Board specific low level serial port init

Signed-off-by: Tony Lindgren
parent 8109a6d4
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Showing with 212 additions and 195 deletions
include/asm-arm/arch-omap/board-h2.h
View file @ cc0c832f
......@@ -36,10 +36,14 @@
#define OMAP1610_ETHR_SIZE SZ_4K
#define OMAP1610_ETHR_START 0x04000000
/* Intel STRATA NOR flash at CS3 */
#define OMAP1610_NOR_FLASH_BASE 0xD8000000
#define OMAP1610_NOR_FLASH_SIZE SZ_32M
#define OMAP1610_NOR_FLASH_START 0x0C000000
/* Intel STRATA NOR flash at CS3 or CS2B(NAND Boot) */
#define OMAP_NOR_FLASH_SIZE SZ_32M
#define OMAP_NOR_FLASH_START1 0x0C000000 /* CS3 */
#define OMAP_NOR_FLASH_START2 0x0A000000 /* CS2B */
/* Samsung NAND flash at CS2B or CS3(NAND Boot) */
#define OMAP_NAND_FLASH_START1 0x0A000000 /* CS2B */
#define OMAP_NAND_FLASH_START2 0x0C000000 /* CS3 */
#endif /* __ASM_ARCH_OMAP_H2_H */
include/asm-arm/arch-omap/board-h3.h
View file @ cc0c832f
......@@ -32,10 +32,14 @@
#define OMAP1710_ETHR_SIZE SZ_4K
#define OMAP1710_ETHR_START 0x04000000
/* Intel STRATA NOR flash at CS3 */
#define OMAP_NOR_FLASH_BASE 0xD8000000
#define OMAP_NOR_FLASH_SIZE SZ_32M
#define OMAP_NOR_FLASH_START 0x00000000
/* Intel STRATA NOR flash at CS3 or CS2B(NAND Boot) */
#define OMAP_NOR_FLASH_SIZE SZ_32M
#define OMAP_NOR_FLASH_START1 0x0C000000 /* CS3 */
#define OMAP_NOR_FLASH_START2 0x0A000000 /* CS2B */
/* Samsung NAND flash at CS2B or CS3(NAND Boot) */
#define OMAP_NAND_FLASH_START1 0x0A000000 /* CS2B */
#define OMAP_NAND_FLASH_START2 0x0C000000 /* CS3 */
#define MAXIRQNUM (IH_BOARD_BASE)
#define MAXFIQNUM MAXIRQNUM
......@@ -43,65 +47,5 @@
#define NR_IRQS (MAXIRQNUM + 1)
#define OMAP_MCBSP1_BASE OMAP1610_MCBSP1_BASE
#define AUDIO_DRR2 (OMAP_MCBSP1_BASE + 0x00)
#define AUDIO_DRR1 (OMAP_MCBSP1_BASE + 0x02)
#define AUDIO_DXR2 (OMAP_MCBSP1_BASE + 0x04)
#define AUDIO_DXR1 (OMAP_MCBSP1_BASE + 0x06)
#define AUDIO_SPCR2 (OMAP_MCBSP1_BASE + 0x08)
#define AUDIO_SPCR1 (OMAP_MCBSP1_BASE + 0x0a)
#define AUDIO_RCR2 (OMAP_MCBSP1_BASE + 0x0c)
#define AUDIO_RCR1 (OMAP_MCBSP1_BASE + 0x0e)
#define AUDIO_XCR2 (OMAP_MCBSP1_BASE + 0x10)
#define AUDIO_XCR1 (OMAP_MCBSP1_BASE + 0x12)
#define AUDIO_SRGR2 (OMAP_MCBSP1_BASE + 0x14)
#define AUDIO_SRGR1 (OMAP_MCBSP1_BASE + 0x16)
#define AUDIO_MCR2 (OMAP_MCBSP1_BASE + 0x18)
#define AUDIO_MCR1 (OMAP_MCBSP1_BASE + 0x1a)
#define AUDIO_RCERA (OMAP_MCBSP1_BASE + 0x1c)
#define AUDIO_RCERB (OMAP_MCBSP1_BASE + 0x1e)
#define AUDIO_XCERA (OMAP_MCBSP1_BASE + 0x20)
#define AUDIO_XCERB (OMAP_MCBSP1_BASE + 0x22)
#define AUDIO_PCR0 (OMAP_MCBSP1_BASE + 0x24)
/* UART3 Registers Maping through MPU bus */
#define OMAP_MPU_UART3_BASE 0xFFFB9800 /* UART3 through MPU bus */
#define UART3_RHR (OMAP_MPU_UART3_BASE + 0)
#define UART3_THR (OMAP_MPU_UART3_BASE + 0)
#define UART3_DLL (OMAP_MPU_UART3_BASE + 0)
#define UART3_IER (OMAP_MPU_UART3_BASE + 4)
#define UART3_DLH (OMAP_MPU_UART3_BASE + 4)
#define UART3_IIR (OMAP_MPU_UART3_BASE + 8)
#define UART3_FCR (OMAP_MPU_UART3_BASE + 8)
#define UART3_EFR (OMAP_MPU_UART3_BASE + 8)
#define UART3_LCR (OMAP_MPU_UART3_BASE + 0x0C)
#define UART3_MCR (OMAP_MPU_UART3_BASE + 0x10)
#define UART3_XON1_ADDR1 (OMAP_MPU_UART3_BASE + 0x10)
#define UART3_XON2_ADDR2 (OMAP_MPU_UART3_BASE + 0x14)
#define UART3_LSR (OMAP_MPU_UART3_BASE + 0x14)
#define UART3_TCR (OMAP_MPU_UART3_BASE + 0x18)
#define UART3_MSR (OMAP_MPU_UART3_BASE + 0x18)
#define UART3_XOFF1 (OMAP_MPU_UART3_BASE + 0x18)
#define UART3_XOFF2 (OMAP_MPU_UART3_BASE + 0x1C)
#define UART3_SPR (OMAP_MPU_UART3_BASE + 0x1C)
#define UART3_TLR (OMAP_MPU_UART3_BASE + 0x1C)
#define UART3_MDR1 (OMAP_MPU_UART3_BASE + 0x20)
#define UART3_MDR2 (OMAP_MPU_UART3_BASE + 0x24)
#define UART3_SFLSR (OMAP_MPU_UART3_BASE + 0x28)
#define UART3_TXFLL (OMAP_MPU_UART3_BASE + 0x28)
#define UART3_RESUME (OMAP_MPU_UART3_BASE + 0x2C)
#define UART3_TXFLH (OMAP_MPU_UART3_BASE + 0x2C)
#define UART3_SFREGL (OMAP_MPU_UART3_BASE + 0x30)
#define UART3_RXFLL (OMAP_MPU_UART3_BASE + 0x30)
#define UART3_SFREGH (OMAP_MPU_UART3_BASE + 0x34)
#define UART3_RXFLH (OMAP_MPU_UART3_BASE + 0x34)
#define UART3_BLR (OMAP_MPU_UART3_BASE + 0x38)
#define UART3_ACREG (OMAP_MPU_UART3_BASE + 0x3C)
#define UART3_DIV16 (OMAP_MPU_UART3_BASE + 0x3C)
#define UART3_SCR (OMAP_MPU_UART3_BASE + 0x40)
#define UART3_SSR (OMAP_MPU_UART3_BASE + 0x44)
#define UART3_EBLR (OMAP_MPU_UART3_BASE + 0x48)
#define UART3_OSC_12M_SEL (OMAP_MPU_UART3_BASE + 0x4C)
#define UART3_MVR (OMAP_MPU_UART3_BASE + 0x50)
#endif /* __ASM_ARCH_OMAP_H3_H */
include/asm-arm/arch-omap/board-innovator.h
View file @ cc0c832f
......@@ -71,17 +71,11 @@ unsigned char fpga_read(int reg);
#endif /* CONFIG_ARCH_OMAP1510 */
#if defined (CONFIG_ARCH_OMAP1610)
#if defined (CONFIG_ARCH_OMAP16XX)
/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
#define OMAP1610_ETHR_BASE 0xE8000000
#define OMAP1610_ETHR_SIZE SZ_4K
#define OMAP1610_ETHR_START 0x04000000
/* Intel STRATA NOR flash at CS3 */
#define OMAP1610_NOR_FLASH_BASE 0xD8000000
#define OMAP1610_NOR_FLASH_SIZE SZ_32M
#define OMAP1610_NOR_FLASH_START 0x0C000000
#define INNOVATOR1610_ETHR_START 0x04000000
#define INNOVATOR1610_ETHR_SIZE SZ_4K
#endif /* CONFIG_ARCH_OMAP1610 */
#endif /* __ASM_ARCH_OMAP_INNOVATOR_H */
include/asm-arm/arch-omap/board.h
View file @ cc0c832f
......@@ -17,7 +17,12 @@
#define OMAP_TAG_CLOCK 0x4f01
#define OMAP_TAG_MMC 0x4f02
#define OMAP_TAG_UART 0x4f03
#define OMAP_TAG_USB 0x4f04
#define OMAP_TAG_USB 0x4f04
#define OMAP_TAG_LCD 0x4f05
#define OMAP_TAG_GPIO_SWITCH 0x4f06
#define OMAP_TAG_BOOT_REASON 0x4f80
#define OMAP_TAG_FLASH_PART 0x4f81
struct omap_clock_config {
/* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
......@@ -26,8 +31,8 @@ struct omap_clock_config {
struct omap_mmc_config {
u8 mmc_blocks;
s8 mmc1_power_pin, mmc2_power_pin;
s8 mmc1_switch_pin, mmc2_switch_pin;
s16 mmc1_power_pin, mmc2_power_pin;
s16 mmc1_switch_pin, mmc2_switch_pin;
};
struct omap_uart_config {
......@@ -63,6 +68,38 @@ struct omap_usb_config {
u8 pins[3];
};
struct omap_lcd_config {
char panel_name[16];
char ctrl_name[16];
};
/* Cover:
* high -> closed
* low -> open
* Connection:
* high -> connected
* low -> disconnected
*/
#define OMAP_GPIO_SWITCH_TYPE_COVER 0x0000
#define OMAP_GPIO_SWITCH_TYPE_CONNECTION 0x0001
#define OMAP_GPIO_SWITCH_FLAG_INVERTED 0x0001
struct omap_gpio_switch_config {
char name[12];
u16 gpio;
int flags:4;
int type:4;
int key_code:24; /* Linux key code */
};
struct omap_flash_part_config {
char part_table[0];
};
struct omap_boot_reason_config {
char reason_str[12];
};
struct omap_board_config_entry {
u16 tag;
u16 len;
......@@ -74,10 +111,14 @@ struct omap_board_config_kernel {
const void *data;
};
extern const void *__omap_get_config(u16 tag, size_t len);
extern const void *__omap_get_config(u16 tag, size_t len, int nr);
#define omap_get_config(tag, type) \
((const type *) __omap_get_config((tag), sizeof(type)))
((const type *) __omap_get_config((tag), sizeof(type), 0))
#define omap_get_nr_config(tag, type, nr) \
((const type *) __omap_get_config((tag), sizeof(type), (nr)))
extern const void *omap_get_var_config(u16 tag, size_t *len);
extern struct omap_board_config_kernel *omap_board_config;
extern int omap_board_config_size;
......
include/asm-arm/arch-omap/hardware.h
View file @ cc0c832f
......@@ -40,6 +40,7 @@
#include <linux/config.h>
#ifndef __ASSEMBLER__
#include <asm/types.h>
#include <asm/arch/cpu.h>
#endif
#include <asm/arch/io.h>
......@@ -64,6 +65,7 @@
#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
#define CK_RATEF 1
#define CK_IDLEF 2
......@@ -140,12 +142,12 @@
#define MPUTIM_AR (1<<1)
#define MPUTIM_ST (1<<0)
/* Watchdog */
#define OMAP_WATCHDOG_BASE (0xfffec800)
#define OMAP_WDT_TIMER (OMAP_WATCHDOG_BASE + 0x0)
#define OMAP_WDT_LOAD_TIM (OMAP_WATCHDOG_BASE + 0x4)
#define OMAP_WDT_READ_TIM (OMAP_WATCHDOG_BASE + 0x4)
#define OMAP_WDT_TIMER_MODE (OMAP_WATCHDOG_BASE + 0x8)
/* Watchdog timer within the OMAP3.2 gigacell */
#define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)
/*
* ---------------------------------------------------------------------------
......@@ -186,22 +188,22 @@
* ---------------------------------------------------------------------------
*/
#define TCMIF_BASE 0xfffecc00
#define IMIF_PRIO_REG __REG32(TCMIF_BASE + 0x00)
#define EMIFS_PRIO_REG __REG32(TCMIF_BASE + 0x04)
#define EMIFF_PRIO_REG __REG32(TCMIF_BASE + 0x08)
#define EMIFS_CONFIG_REG __REG32(TCMIF_BASE + 0x0c)
#define EMIFS_CS0_CONFIG_REG __REG32(TCMIF_BASE + 0x10)
#define EMIFS_CS1_CONFIG_REG __REG32(TCMIF_BASE + 0x14)
#define EMIFS_CS2_CONFIG_REG __REG32(TCMIF_BASE + 0x18)
#define EMIFS_CS3_CONFIG_REG __REG32(TCMIF_BASE + 0x1c)
#define EMIFF_SDRAM_CONFIG_REG __REG32(TCMIF_BASE + 0x20)
#define EMIFF_MRS_REG __REG32(TCMIF_BASE + 0x24)
#define TC_TIMEOUT1_REG __REG32(TCMIF_BASE + 0x28)
#define TC_TIMEOUT2_REG __REG32(TCMIF_BASE + 0x2c)
#define TC_TIMEOUT3_REG __REG32(TCMIF_BASE + 0x30)
#define TC_ENDIANISM_REG __REG32(TCMIF_BASE + 0x34)
#define EMIFF_SDRAM_CONFIG_2_REG __REG32(TCMIF_BASE + 0x3c)
#define EMIF_CFG_DYNAMIC_WS_REG __REG32(TCMIF_BASE + 0x40)
#define IMIF_PRIO (TCMIF_BASE + 0x00)
#define EMIFS_PRIO (TCMIF_BASE + 0x04)
#define EMIFF_PRIO (TCMIF_BASE + 0x08)
#define EMIFS_CONFIG (TCMIF_BASE + 0x0c)
#define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10)
#define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14)
#define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18)
#define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c)
#define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20)
#define EMIFF_MRS (TCMIF_BASE + 0x24)
#define TC_TIMEOUT1 (TCMIF_BASE + 0x28)
#define TC_TIMEOUT2 (TCMIF_BASE + 0x2c)
#define TC_TIMEOUT3 (TCMIF_BASE + 0x30)
#define TC_ENDIANISM (TCMIF_BASE + 0x34)
#define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c)
#define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40)
/*
* ----------------------------------------------------------------------------
......@@ -235,6 +237,7 @@
#define PULL_DWN_CTRL_1 0xfffe1044
#define PULL_DWN_CTRL_2 0xfffe1048
#define PULL_DWN_CTRL_3 0xfffe104c
#define PULL_DWN_CTRL_4 0xfffe10ac
/* OMAP-1610 specific multiplexing registers */
#define FUNC_MUX_CTRL_E 0xfffe1090
......@@ -248,6 +251,9 @@
#define PU_PD_SEL_3 0xfffe10c0
#define PU_PD_SEL_4 0xfffe10c4
/* Timer32K for 1610 and 1710*/
#define OMAP_TIMER32K_BASE 0xFFFBC400
/*
* ---------------------------------------------------------------------------
* TIPB bus interface
......@@ -277,62 +283,24 @@
/*
* ---------------------------------------------------------------------------
* Processor differentiation
* Processor specific defines
* ---------------------------------------------------------------------------
*/
#define OMAP_ID_BASE (0xfffed400)
#define OMAP_ID_REG __REG32(OMAP_ID_BASE + 0x04)
#define ID_SHIFT 12
#define ID_MASK 0x7fff
/* See also uncompress.h */
#define OMAP_ID_730 0x355F
#define OMAP_ID_1510 0x3470
#define OMAP_ID_1610 0x3576
#define OMAP_ID_1710 0x35F7
#define OMAP_ID_5912 0x358C
#define OMAP_ID_1611 0x358C
#ifdef CONFIG_ARCH_OMAP730
#include "omap730.h"
#define cpu_is_omap730() (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_730)
#else
#define cpu_is_omap730() 0
#endif
#ifdef CONFIG_ARCH_OMAP1510
#include "omap1510.h"
#define cpu_is_omap1510() (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_1510)
#else
#define cpu_is_omap1510() 0
#endif
#ifdef CONFIG_ARCH_OMAP1610
#include "omap1610.h"
#define cpu_is_omap1610() (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_1610) || \
(((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_1611)
#else
#define cpu_is_omap1610() 0
#endif
#ifdef CONFIG_ARCH_OMAP1710
#include "omap1610.h"
#define cpu_is_omap1710() (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_1710)
#else
#define cpu_is_omap1710() 0
#endif
#ifdef CONFIG_ARCH_OMAP5912
#include "omap5912.h"
#define cpu_is_omap5912() (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_5912)
#else
#define cpu_is_omap5912() 0
#ifdef CONFIG_ARCH_OMAP16XX
#include "omap16xx.h"
#endif
/*
* ---------------------------------------------------------------------------
* Board differentiation
* Board specific defines
* ---------------------------------------------------------------------------
*/
......
include/asm-arm/arch-omap/irqs.h
View file @ cc0c832f
......@@ -192,8 +192,6 @@
#define INT_730_TIMER32K (22 + IH2_BASE)
#define INT_730_MMC_SDIO (23 + IH2_BASE)
#define INT_730_UPLD (24 + IH2_BASE)
#define INT_730_RTC_TIMER (25 + IH2_BASE)
#define INT_730_RTC_ALARM (26 + IH2_BASE)
#define INT_730_USB_HHC_1 (27 + IH2_BASE)
#define INT_730_USB_HHC_2 (28 + IH2_BASE)
#define INT_730_USB_GENI (29 + IH2_BASE)
......@@ -224,24 +222,6 @@
#define INT_730_DMA_CH15 (62 + IH2_BASE)
#define INT_730_NAND (63 + IH2_BASE)
/* OMAP-730 differences */
#ifdef CONFIG_ARCH_OMAP730
#undef INT_IH2_IRQ
#define INT_IH2_IRQ INT_730_IH2_IRQ
#undef INT_KEYBOARD
#define INT_KEYBOARD INT_730_MPUIO_KEYPAD
#undef INT_UART1
#define INT_UART1 INT_730_UART_MODEM_1
#undef INT_UART2
#define INT_UART2 INT_730_UART_MODEM_IRDA_2
#undef INT_MPUIO
#define INT_MPUIO INT_730_MPUIO
#undef INT_RTC_TIMER
#define INT_RTC_TIMER INT_730_RTC_TIMER
#undef INT_RTC_ALARM
#define INT_RTC_ALARM INT_730_RTC_ALARM
#endif
/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and
* 16 MPUIO lines */
#define OMAP_MAX_GPIO_LINES 192
......@@ -260,7 +240,7 @@ extern void omap_init_irq(void);
#include <asm/arch/hardware.h>
#ifndef NR_IRQS
#define NR_IRQS 256
#define NR_IRQS IH_BOARD_BASE
#endif
#endif
include/asm-arm/arch-omap/memory.h
View file @ cc0c832f
......@@ -59,12 +59,14 @@
* OMAP-1510 bus address is translated into a Local Bus address if the
* OMAP bus type is lbus. We do the address translation based on the
* device overriding the defaults used in the dma-mapping API.
* Note that the is_lbus_device() test is not very efficient on 1510
* because of the strncmp().
*/
#ifdef CONFIG_ARCH_OMAP1510
#define virt_to_lbus(x) ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET)
#define lbus_to_virt(x) ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
#define is_lbus_device(dev) (cpu_is_omap1510() && dev && dev->coherent_dma_mask == 0x0fffffff)
#define is_lbus_device(dev) (cpu_is_omap1510() && dev && (strncmp(dev->bus_id, "ohci", 4) == 0))
#define __arch_page_to_dma(dev, page) ({is_lbus_device(dev) ? \
(dma_addr_t)virt_to_lbus(page_address(page)) : \
......
include/asm-arm/arch-omap/mux.h
View file @ cc0c832f
......@@ -43,9 +43,7 @@
#define PU_PD_SEL_NA 0 /* No pu_pd reg available */
#define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */
#define DEBUG_MUX
#ifdef DEBUG_MUX
#ifdef CONFIG_OMAP_MUX_DEBUG
#define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
.mux_reg = FUNC_MUX_CTRL_##reg, \
.mask_offset = mode_offset, \
......@@ -73,7 +71,7 @@
#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
.pu_pd_val = status,
#endif // DEBUG_MUX
#endif /* CONFIG_OMAP_MUX_DEBUG */
#define MUX_CFG(desc, mux_reg, mode_offset, mode, \
pull_reg, pull_bit, pull_status, \
......@@ -134,6 +132,7 @@ typedef enum {
UART3_RTS,
UART3_CLKREQ,
UART3_BCLK, /* 12MHz clock out */
Y15_1610_UART3_RTS,
/* PWT & PWL */
PWT,
......@@ -174,8 +173,13 @@ typedef enum {
R19_1510_GPIO1,
M14_1510_GPIO2,
/* OMAP1610 GPIO */
Y15_1610_GPIO17,
/* OMAP-1710 GPIO */
R18_1710_GPIO0,
V2_1710_GPIO10,
N21_1710_GPIO14,
W15_1710_GPIO40,
/* MPUIO */
......@@ -244,6 +248,10 @@ typedef enum {
P15_1610_UWIRE_CS0,
N15_1610_UWIRE_CS1,
/* OMAP-1610 Flash */
L3_1610_FLASH_CS2B_OE,
M8_1610_FLASH_CS2B_WE,
/* First MMC */
MMC_CMD,
MMC_DAT1,
......@@ -310,7 +318,8 @@ typedef enum {
* Table of various FUNC_MUX and PULL_DWN combinations for each device.
* See also reg_cfg_t above for the lookup table.
*/
static reg_cfg_set reg_cfg_table[] = {
static reg_cfg_set __initdata_or_module
reg_cfg_table[] = {
/*
* description mux mode mux pull pull pull pu_pd pu dbg
* reg offset mode reg bit ena reg
......@@ -331,6 +340,7 @@ MUX_CFG("UART3_CTS", 5, 12, 2, 0, 24, 0, NA, 0, 0)
MUX_CFG("UART3_RTS", 5, 15, 2, 0, 25, 0, NA, 0, 0)
MUX_CFG("UART3_CLKREQ", 9, 27, 0, 2, 5, 0, NA, 0, 0)
MUX_CFG("UART3_BCLK", A, 0, 0, 2, 6, 0, NA, 0, 0)
MUX_CFG("Y15_1610_UART3_RTS", A, 0, 1, 2, 6, 0, NA, 0, 0)
/* PWT & PWL, conflicts with UART3 */
MUX_CFG("PWT", 6, 0, 2, 0, 30, 0, NA, 0, 0)
......@@ -371,9 +381,14 @@ MUX_CFG("R18_1510_GPIO0", 7, 9, 0, 1, 11, 1, 0, 0, 1)
MUX_CFG("R19_1510_GPIO1", 7, 6, 0, 1, 10, 1, 0, 0, 1)
MUX_CFG("M14_1510_GPIO2", 7, 3, 0, 1, 9, 1, 0, 0, 1)
/* OMAP1610 GPIO */
MUX_CFG("Y15_1610_GPIO17", A, 0, 7, 2, 6, 0, NA, 0, 1)
/* OMAP-1710 GPIO */
MUX_CFG("R18_1710_GPIO0", 7, 9, 0, 1, 11, 1, 1, 1, 1)
MUX_CFG("W15_1710_GPIO40", 9, 27, 7, 2, 5, 1, 2, 1, 1)
MUX_CFG("R18_1710_GPIO0", 7, 9, 0, 1, 11, 1, 1, 1, 1)
MUX_CFG("V2_1710_GPIO10", F, 27, 1, 4, 3, 1, 4, 1, 1)
MUX_CFG("N21_1710_GPIO14", 6, 9, 0, 1, 1, 1, 1, 1, 1)
MUX_CFG("W15_1710_GPIO40", 9, 27, 7, 2, 5, 1, 2, 1, 1)
/* MPUIO */
MUX_CFG("MPUIO2", 7, 18, 0, 1, 1, 1, NA, 0, 1)
......@@ -442,6 +457,10 @@ MUX_CFG("N14_1610_UWIRE_CS0", 8, 9, 1, 1, 21, 0, 1, 1, 1)
MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1)
MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 1, 14, 0, NA, 0, 1)
/* OMAP-1610 Flash */
MUX_CFG("L3_1610_FLASH_CS2B_OE",10, 6, 1, NA, 0, 0, NA, 0, 1)
MUX_CFG("M8_1610_FLASH_CS2B_WE",10, 3, 1, NA, 0, 0, NA, 0, 1)
/* First MMC interface, same on 1510, 1610 and 1710 */
MUX_CFG("MMC_CMD", A, 27, 0, 2, 15, 1, 2, 1, 1)
MUX_CFG("MMC_DAT1", A, 24, 0, 2, 14, 1, 2, 1, 1)
......@@ -501,6 +520,12 @@ MUX_CFG("T20_1610_LOW_PWR", 7, 12, 1, NA, 0, 0, NA, 0, 0)
#endif /* __MUX_C__ */
#ifdef CONFIG_OMAP_MUX
/* setup pin muxing in Linux */
extern int omap_cfg_reg(reg_cfg_t reg_cfg);
#else
/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
static inline int omap_cfg_reg(reg_cfg_t reg_cfg) { return 0; }
#endif
#endif
include/asm-arm/arch-omap/serial.h
View file @ cc0c832f
......@@ -12,6 +12,8 @@
#define OMAP_UART1_BASE (unsigned char *)0xfffb0000
#define OMAP_UART2_BASE (unsigned char *)0xfffb0800
#define OMAP_UART3_BASE (unsigned char *)0xfffb9800
#define OMAP_MAX_NR_PORTS 3
#define PORT_OMAP 16 /* Temporary */
#ifndef __ASSEMBLY__
......@@ -19,7 +21,9 @@
#include <asm/irq.h>
#define OMAP1510_BASE_BAUD (12000000/16)
#define OMAP1610_BASE_BAUD (48000000/16)
#define OMAP16XX_BASE_BAUD (48000000/16)
#define UART_SYSC 0x15
/* OMAP FCR trigger redefinitions */
#define UART_FCR_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 8 */
......
include/asm-arm/arch-omap/tc.h 0 → 100644
View file @ cc0c832f
/*
* linux/include/asm-arm/arch-omap/tc.h
*
* OMAP Traffic Controller
*
* Copyright (C) 2004 Nokia Corporation
* Author: Imre Deak <imre.deak@nokia.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef __ASM_ARCH_TC_H
#define __ASM_ARCH_TC_H
#define OMAP_TC_OCPT1_PRIOR 0xFFFECC00
#define OMAP_TC_EMIFS_PRIOR 0xFFFECC04
#define OMAP_TC_EMIFF_PRIOR 0xFFFECC08
#define OMAP_TC_OCPT2_PRIOR 0xFFFECCD0
/* EMIF Slow Interface Configuration Register */
#define OMAP_EMIFS_CONFIG_REG __REG32(EMIFS_CONFIG)
#define OMAP_EMIFS_CONFIG_FR (1 << 4)
#define OMAP_EMIFS_CONFIG_PDE (1 << 3)
#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2)
#define OMAP_EMIFS_CONFIG_BM (1 << 1)
#define OMAP_EMIFS_CONFIG_WP (1 << 0)
/* external EMIFS chipselect regions */
#define OMAP_CS1_PHYS 0x04000000
#define OMAP_CS1_SIZE SZ_64M
#define OMAP_CS1A_PHYS OMAP_CS1_PHYS
#define OMAP_CS1A_SIZE SZ_32M
#define OMAP_CS1B_PHYS (OMAP_CS1A_PHYS + OMAP_CS1A_SIZE)
#define OMAP_CS1B_SIZE SZ_32M
#define OMAP_CS2_PHYS 0x08000000
#define OMAP_CS2_SIZE SZ_64M
#define OMAP_CS2A_PHYS OMAP_CS2_PHYS
#define OMAP_CS2A_SIZE SZ_32M
#define OMAP_CS2B_PHYS (OMAP_CS2A_PHYS + OMAP_CS2A_SIZE)
#define OMAP_CS2B_SIZE SZ_32M
#define OMAP_CS3_PHYS 0x0c000000
#define OMAP_CS3_SIZE SZ_64M
#endif /* __ASM_ARCH_TC_H */
include/asm-arm/arch-omap/timex.h
View file @ cc0c832f
......@@ -28,8 +28,6 @@
#if !defined(__ASM_ARCH_OMAP_TIMEX_H)
#define __ASM_ARCH_OMAP_TIMEX_H
#include <asm/arch/clocks.h>
/* TC clock */
#define CLOCK_TICK_RATE ((OMAP_CK_MAX_RATE*1000000)/2)
#define CLOCK_TICK_RATE (HZ * 100000UL)
#endif /* __ASM_ARCH_OMAP_TIMEX_H */
include/asm-arm/arch-omap/uncompress.h
View file @ cc0c832f
......@@ -20,10 +20,13 @@
#include <linux/config.h>
#include <linux/types.h>
#include <linux/serial_reg.h>
#include <asm/hardware.h>
#include <asm/arch/serial.h>
unsigned int system_rev;
#define UART_OMAP_MDR1 0x08 /* mode definition register */
#define OMAP_ID_730 0x355F
#define ID_MASK 0x7fff
#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK
......@@ -31,7 +34,7 @@ static void
putstr(const char *s)
{
volatile u8 * uart = 0;
int shift = 0;
int shift;
#ifdef CONFIG_OMAP_LL_DEBUG_UART3
uart = (volatile u8 *)(OMAP_UART3_BASE);
......@@ -46,21 +49,11 @@ putstr(const char *s)
/* MMU is not on, so cpu_is_omapXXXX() won't work here */
unsigned int omap_id = omap_get_id();
if (omap_id == OMAP_ID_1510 || omap_id == OMAP_ID_1610 ||
omap_id == OMAP_ID_1710 || omap_id == OMAP_ID_5912) {
shift = 2;
} else if (omap_id == OMAP_ID_730) {
if (omap_id == OMAP_ID_730)
shift = 0;
} else {
/* Assume nothing for unknown OMAP processors.
* Add an entry for your OMAP type to select
* the default serial console here. If the
* serial port is enabled, we'll use it to
* display status messages. Else we'll be
* quiet.
*/
return;
}
else
shift = 2;
if (check_port(uart, shift))
break;
/* Silent boot if no serial ports are enabled. */
......
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