Commit cc2d1de0 authored by Rafał Miłecki's avatar Rafał Miłecki Committed by Kalle Valo

bcma: define ChipCommon B MII registers

We don't have access to datasheets to document all the bits but we can
name these registers at least.
Signed-off-by: default avatarRafał Miłecki <zajec5@gmail.com>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
parent cf8c581a
...@@ -33,11 +33,12 @@ static bool bcma_wait_reg(struct bcma_bus *bus, void __iomem *addr, u32 mask, ...@@ -33,11 +33,12 @@ static bool bcma_wait_reg(struct bcma_bus *bus, void __iomem *addr, u32 mask,
void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value) void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value)
{ {
struct bcma_bus *bus = ccb->core->bus; struct bcma_bus *bus = ccb->core->bus;
void __iomem *mii = ccb->mii;
writel(offset, ccb->mii + 0x00); writel(offset, mii + BCMA_CCB_MII_MNG_CTL);
bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100); bcma_wait_reg(bus, mii + BCMA_CCB_MII_MNG_CTL, 0x0100, 0x0000, 100);
writel(value, ccb->mii + 0x04); writel(value, mii + BCMA_CCB_MII_MNG_CMD_DATA);
bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100); bcma_wait_reg(bus, mii + BCMA_CCB_MII_MNG_CTL, 0x0100, 0x0000, 100);
} }
EXPORT_SYMBOL_GPL(bcma_chipco_b_mii_write); EXPORT_SYMBOL_GPL(bcma_chipco_b_mii_write);
......
...@@ -504,6 +504,9 @@ ...@@ -504,6 +504,9 @@
#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000 #define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20 #define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
#define BCMA_CCB_MII_MNG_CTL 0x0000
#define BCMA_CCB_MII_MNG_CMD_DATA 0x0004
/* BCM4331 ChipControl numbers. */ /* BCM4331 ChipControl numbers. */
#define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */ #define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
#define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */ #define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */
......
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