Commit cc3e06a5 authored by Dave Airlie's avatar Dave Airlie

Merge branch 'drm-fixes-3.10-sun' of git://people.freedesktop.org/~agd5f/linux into drm-next

This is the pull request for AMD Sun/Hainan support.  I've
split it out separately from my regular fixes stream.  Hainan
is a new SI asic with no UVD or DCE hardware.  The patches are
minimally invasive; basically just pci ids and skipping UVD and
DCE init for this family.  Most of the changes to si.c are just
the golden register tables for the family.

* 'drm-fixes-3.10-sun' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon: add Hainan pci ids
  drm/radeon: add golden register settings for Hainan (v2)
  drm/radeon: sun/hainan chips do not have UVD (v2)
  drm/radeon: track which asics have UVD
  drm/radeon: radeon-asic updates for Hainan
  drm/radeon: fill in ucode loading support for Hainan
  drm/radeon: don't touch DCE or VGA regs on Hainan (v3)
  drm/radeon: fill in GPU init for Hainan (v2)
  drm/radeon: add chip family for Hainan
parents a3f69026 2a0f9055
...@@ -2343,11 +2343,13 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav ...@@ -2343,11 +2343,13 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
u32 crtc_enabled, tmp, frame_count, blackout; u32 crtc_enabled, tmp, frame_count, blackout;
int i, j; int i, j;
save->vga_render_control = RREG32(VGA_RENDER_CONTROL); if (!ASIC_IS_NODCE(rdev)) {
save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
/* disable VGA render */ /* disable VGA render */
WREG32(VGA_RENDER_CONTROL, 0); WREG32(VGA_RENDER_CONTROL, 0);
}
/* blank the display controllers */ /* blank the display controllers */
for (i = 0; i < rdev->num_crtc; i++) { for (i = 0; i < rdev->num_crtc; i++) {
crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN; crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
...@@ -2438,8 +2440,11 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s ...@@ -2438,8 +2440,11 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
(u32)rdev->mc.vram_start); (u32)rdev->mc.vram_start);
} }
WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); if (!ASIC_IS_NODCE(rdev)) {
WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
}
/* unlock regs and wait for update */ /* unlock regs and wait for update */
for (i = 0; i < rdev->num_crtc; i++) { for (i = 0; i < rdev->num_crtc; i++) {
...@@ -2499,10 +2504,12 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s ...@@ -2499,10 +2504,12 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
} }
} }
} }
/* Unlock vga access */ if (!ASIC_IS_NODCE(rdev)) {
WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); /* Unlock vga access */
mdelay(1); WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
WREG32(VGA_RENDER_CONTROL, save->vga_render_control); mdelay(1);
WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
}
} }
void evergreen_mc_program(struct radeon_device *rdev) void evergreen_mc_program(struct radeon_device *rdev)
......
...@@ -1694,6 +1694,7 @@ struct radeon_device { ...@@ -1694,6 +1694,7 @@ struct radeon_device {
int num_crtc; /* number of crtcs */ int num_crtc; /* number of crtcs */
struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
bool audio_enabled; bool audio_enabled;
bool has_uvd;
struct r600_audio audio_status; /* audio stuff */ struct r600_audio audio_status; /* audio stuff */
struct notifier_block acpi_nb; struct notifier_block acpi_nb;
/* only one userspace can use Hyperz features or CMASK at a time */ /* only one userspace can use Hyperz features or CMASK at a time */
...@@ -1838,6 +1839,7 @@ void r100_pll_errata_after_index(struct radeon_device *rdev); ...@@ -1838,6 +1839,7 @@ void r100_pll_errata_after_index(struct radeon_device *rdev);
#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
(rdev->flags & RADEON_IS_IGP)) (rdev->flags & RADEON_IS_IGP))
#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
/* /*
* BIOS helpers. * BIOS helpers.
......
...@@ -1935,6 +1935,8 @@ int radeon_asic_init(struct radeon_device *rdev) ...@@ -1935,6 +1935,8 @@ int radeon_asic_init(struct radeon_device *rdev)
else else
rdev->num_crtc = 2; rdev->num_crtc = 2;
rdev->has_uvd = false;
switch (rdev->family) { switch (rdev->family) {
case CHIP_R100: case CHIP_R100:
case CHIP_RV100: case CHIP_RV100:
...@@ -1999,16 +2001,22 @@ int radeon_asic_init(struct radeon_device *rdev) ...@@ -1999,16 +2001,22 @@ int radeon_asic_init(struct radeon_device *rdev)
case CHIP_RV635: case CHIP_RV635:
case CHIP_RV670: case CHIP_RV670:
rdev->asic = &r600_asic; rdev->asic = &r600_asic;
if (rdev->family == CHIP_R600)
rdev->has_uvd = false;
else
rdev->has_uvd = true;
break; break;
case CHIP_RS780: case CHIP_RS780:
case CHIP_RS880: case CHIP_RS880:
rdev->asic = &rs780_asic; rdev->asic = &rs780_asic;
rdev->has_uvd = true;
break; break;
case CHIP_RV770: case CHIP_RV770:
case CHIP_RV730: case CHIP_RV730:
case CHIP_RV710: case CHIP_RV710:
case CHIP_RV740: case CHIP_RV740:
rdev->asic = &rv770_asic; rdev->asic = &rv770_asic;
rdev->has_uvd = true;
break; break;
case CHIP_CEDAR: case CHIP_CEDAR:
case CHIP_REDWOOD: case CHIP_REDWOOD:
...@@ -2021,11 +2029,13 @@ int radeon_asic_init(struct radeon_device *rdev) ...@@ -2021,11 +2029,13 @@ int radeon_asic_init(struct radeon_device *rdev)
else else
rdev->num_crtc = 6; rdev->num_crtc = 6;
rdev->asic = &evergreen_asic; rdev->asic = &evergreen_asic;
rdev->has_uvd = true;
break; break;
case CHIP_PALM: case CHIP_PALM:
case CHIP_SUMO: case CHIP_SUMO:
case CHIP_SUMO2: case CHIP_SUMO2:
rdev->asic = &sumo_asic; rdev->asic = &sumo_asic;
rdev->has_uvd = true;
break; break;
case CHIP_BARTS: case CHIP_BARTS:
case CHIP_TURKS: case CHIP_TURKS:
...@@ -2036,27 +2046,37 @@ int radeon_asic_init(struct radeon_device *rdev) ...@@ -2036,27 +2046,37 @@ int radeon_asic_init(struct radeon_device *rdev)
else else
rdev->num_crtc = 6; rdev->num_crtc = 6;
rdev->asic = &btc_asic; rdev->asic = &btc_asic;
rdev->has_uvd = true;
break; break;
case CHIP_CAYMAN: case CHIP_CAYMAN:
rdev->asic = &cayman_asic; rdev->asic = &cayman_asic;
/* set num crtcs */ /* set num crtcs */
rdev->num_crtc = 6; rdev->num_crtc = 6;
rdev->has_uvd = true;
break; break;
case CHIP_ARUBA: case CHIP_ARUBA:
rdev->asic = &trinity_asic; rdev->asic = &trinity_asic;
/* set num crtcs */ /* set num crtcs */
rdev->num_crtc = 4; rdev->num_crtc = 4;
rdev->has_uvd = true;
break; break;
case CHIP_TAHITI: case CHIP_TAHITI:
case CHIP_PITCAIRN: case CHIP_PITCAIRN:
case CHIP_VERDE: case CHIP_VERDE:
case CHIP_OLAND: case CHIP_OLAND:
case CHIP_HAINAN:
rdev->asic = &si_asic; rdev->asic = &si_asic;
/* set num crtcs */ /* set num crtcs */
if (rdev->family == CHIP_OLAND) if (rdev->family == CHIP_HAINAN)
rdev->num_crtc = 0;
else if (rdev->family == CHIP_OLAND)
rdev->num_crtc = 2; rdev->num_crtc = 2;
else else
rdev->num_crtc = 6; rdev->num_crtc = 6;
if (rdev->family == CHIP_HAINAN)
rdev->has_uvd = false;
else
rdev->has_uvd = true;
break; break;
default: default:
/* FIXME: not supported yet */ /* FIXME: not supported yet */
......
...@@ -221,24 +221,28 @@ static bool ni_read_disabled_bios(struct radeon_device *rdev) ...@@ -221,24 +221,28 @@ static bool ni_read_disabled_bios(struct radeon_device *rdev)
/* enable the rom */ /* enable the rom */
WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
/* Disable VGA mode */ if (!ASIC_IS_NODCE(rdev)) {
WREG32(AVIVO_D1VGA_CONTROL, /* Disable VGA mode */
(d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | WREG32(AVIVO_D1VGA_CONTROL,
AVIVO_DVGA_CONTROL_TIMING_SELECT))); (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
WREG32(AVIVO_D2VGA_CONTROL, AVIVO_DVGA_CONTROL_TIMING_SELECT)));
(d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | WREG32(AVIVO_D2VGA_CONTROL,
AVIVO_DVGA_CONTROL_TIMING_SELECT))); (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
WREG32(AVIVO_VGA_RENDER_CONTROL, AVIVO_DVGA_CONTROL_TIMING_SELECT)));
(vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); WREG32(AVIVO_VGA_RENDER_CONTROL,
(vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
}
WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
r = radeon_read_bios(rdev); r = radeon_read_bios(rdev);
/* restore regs */ /* restore regs */
WREG32(R600_BUS_CNTL, bus_cntl); WREG32(R600_BUS_CNTL, bus_cntl);
WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); if (!ASIC_IS_NODCE(rdev)) {
WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
}
WREG32(R600_ROM_CNTL, rom_cntl); WREG32(R600_ROM_CNTL, rom_cntl);
return r; return r;
} }
......
...@@ -94,6 +94,7 @@ static const char radeon_family_name[][16] = { ...@@ -94,6 +94,7 @@ static const char radeon_family_name[][16] = {
"PITCAIRN", "PITCAIRN",
"VERDE", "VERDE",
"OLAND", "OLAND",
"HAINAN",
"LAST", "LAST",
}; };
......
...@@ -92,6 +92,7 @@ enum radeon_family { ...@@ -92,6 +92,7 @@ enum radeon_family {
CHIP_PITCAIRN, CHIP_PITCAIRN,
CHIP_VERDE, CHIP_VERDE,
CHIP_OLAND, CHIP_OLAND,
CHIP_HAINAN,
CHIP_LAST, CHIP_LAST,
}; };
......
This diff is collapsed.
...@@ -28,6 +28,7 @@ ...@@ -28,6 +28,7 @@
#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
#define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001
/* discrete uvd clocks */ /* discrete uvd clocks */
#define CG_UPLL_FUNC_CNTL 0x634 #define CG_UPLL_FUNC_CNTL 0x634
......
...@@ -152,6 +152,12 @@ ...@@ -152,6 +152,12 @@
{0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \ {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6700, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \ {0x1002, 0x6700, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \ {0x1002, 0x6701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \ {0x1002, 0x6702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
......
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