Commit cd1c9c1a authored by Alex Deucher's avatar Alex Deucher

drm/radeon: re-enable selective GPUVM flushing

Now that the PFP and ME synchronization is fixed, we
can enable this again reliably.
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Tested-by: default avatarMichel Dänzer <michel.daenzer@amd.com>
parent 86302eea
...@@ -238,9 +238,7 @@ void radeon_vm_flush(struct radeon_device *rdev, ...@@ -238,9 +238,7 @@ void radeon_vm_flush(struct radeon_device *rdev,
uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory); uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory);
/* if we can't remember our last VM flush then flush now! */ /* if we can't remember our last VM flush then flush now! */
/* XXX figure out why we have to flush all the time before CIK */ if (!vm->last_flush || pd_addr != vm->pd_gpu_addr) {
if (rdev->family < CHIP_BONAIRE ||
!vm->last_flush || pd_addr != vm->pd_gpu_addr) {
trace_radeon_vm_flush(pd_addr, ring, vm->id); trace_radeon_vm_flush(pd_addr, ring, vm->id);
vm->pd_gpu_addr = pd_addr; vm->pd_gpu_addr = pd_addr;
radeon_ring_vm_flush(rdev, ring, vm); radeon_ring_vm_flush(rdev, ring, vm);
......
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