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Commit cecd902a authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge branch 'next-samsung-devel-spi3' of... 

Merge branch 'next-samsung-devel-spi3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into samsung/cleanup
parents 7a09266c a153e31a
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Showing with 215 additions and 191 deletions
arch/arm/mach-s3c64xx/clock.c
View file @ cecd902a
...@@ -183,18 +183,6 @@ static struct clk init_clocks_off[] = { ...@@ -183,18 +183,6 @@ static struct clk init_clocks_off[] = {
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_SPI1, .ctrlbit = S3C_CLKCON_PCLK_SPI1,
}, {
.name = "spi_48m",
.devname = "s3c64xx-spi.0",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
}, {
.name = "spi_48m",
.devname = "s3c64xx-spi.1",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
}, { }, {
.name = "48m", .name = "48m",
.devname = "s3c-sdhci.0", .devname = "s3c-sdhci.0",
...@@ -226,6 +214,22 @@ static struct clk init_clocks_off[] = { ...@@ -226,6 +214,22 @@ static struct clk init_clocks_off[] = {
}, },
}; };
static struct clk clk_48m_spi0 = {
.name = "spi_48m",
.devname = "s3c64xx-spi.0",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
};
static struct clk clk_48m_spi1 = {
.name = "spi_48m",
.devname = "s3c64xx-spi.1",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
};
static struct clk init_clocks[] = { static struct clk init_clocks[] = {
{ {
.name = "lcd", .name = "lcd",
...@@ -590,25 +594,6 @@ static struct clksrc_clk clksrcs[] = { ...@@ -590,25 +594,6 @@ static struct clksrc_clk clksrcs[] = {
.reg_src = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2 }, .reg_src = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2 },
.reg_div = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4 }, .reg_div = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4 },
.sources = &clkset_uhost, .sources = &clkset_uhost,
}, {
.clk = {
.name = "spi-bus",
.devname = "s3c64xx-spi.0",
.ctrlbit = S3C_CLKCON_SCLK_SPI0,
.enable = s3c64xx_sclk_ctrl,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
.sources = &clkset_spi_mmc,
}, {
.clk = {
.name = "spi-bus",
.devname = "s3c64xx-spi.1",
.enable = s3c64xx_sclk_ctrl,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
.sources = &clkset_spi_mmc,
}, { }, {
.clk = { .clk = {
.name = "audio-bus", .name = "audio-bus",
...@@ -708,6 +693,30 @@ static struct clksrc_clk clk_sclk_mmc2 = { ...@@ -708,6 +693,30 @@ static struct clksrc_clk clk_sclk_mmc2 = {
.sources = &clkset_spi_mmc, .sources = &clkset_spi_mmc,
}; };
static struct clksrc_clk clk_sclk_spi0 = {
.clk = {
.name = "spi-bus",
.devname = "s3c64xx-spi.0",
.ctrlbit = S3C_CLKCON_SCLK_SPI0,
.enable = s3c64xx_sclk_ctrl,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
.sources = &clkset_spi_mmc,
};
static struct clksrc_clk clk_sclk_spi1 = {
.clk = {
.name = "spi-bus",
.devname = "s3c64xx-spi.1",
.ctrlbit = S3C_CLKCON_SCLK_SPI1,
.enable = s3c64xx_sclk_ctrl,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
.sources = &clkset_spi_mmc,
};
/* Clock initialisation code */ /* Clock initialisation code */
static struct clksrc_clk *init_parents[] = { static struct clksrc_clk *init_parents[] = {
...@@ -721,12 +730,16 @@ static struct clksrc_clk *clksrc_cdev[] = { ...@@ -721,12 +730,16 @@ static struct clksrc_clk *clksrc_cdev[] = {
&clk_sclk_mmc0, &clk_sclk_mmc0,
&clk_sclk_mmc1, &clk_sclk_mmc1,
&clk_sclk_mmc2, &clk_sclk_mmc2,
&clk_sclk_spi0,
&clk_sclk_spi1,
}; };
static struct clk *clk_cdev[] = { static struct clk *clk_cdev[] = {
&clk_hsmmc0, &clk_hsmmc0,
&clk_hsmmc1, &clk_hsmmc1,
&clk_hsmmc2, &clk_hsmmc2,
&clk_48m_spi0,
&clk_48m_spi1,
}; };
static struct clk_lookup s3c64xx_clk_lookup[] = { static struct clk_lookup s3c64xx_clk_lookup[] = {
...@@ -738,6 +751,11 @@ static struct clk_lookup s3c64xx_clk_lookup[] = { ...@@ -738,6 +751,11 @@ static struct clk_lookup s3c64xx_clk_lookup[] = {
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0),
CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1),
}; };
#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
......
arch/arm/mach-s3c64xx/dev-spi.c
View file @ cecd902a
...@@ -24,12 +24,6 @@ ...@@ -24,12 +24,6 @@
#include <plat/gpio-cfg.h> #include <plat/gpio-cfg.h>
#include <plat/devs.h> #include <plat/devs.h>
static char *spi_src_clks[] = {
[S3C64XX_SPI_SRCCLK_PCLK] = "pclk",
[S3C64XX_SPI_SRCCLK_SPIBUS] = "spi-bus",
[S3C64XX_SPI_SRCCLK_48M] = "spi_48m",
};
/* SPI Controller platform_devices */ /* SPI Controller platform_devices */
/* Since we emulate multi-cs capability, we do not touch the GPC-3,7. /* Since we emulate multi-cs capability, we do not touch the GPC-3,7.
...@@ -176,5 +170,4 @@ void __init s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) ...@@ -176,5 +170,4 @@ void __init s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
pd->num_cs = num_cs; pd->num_cs = num_cs;
pd->src_clk_nr = src_clk_nr; pd->src_clk_nr = src_clk_nr;
pd->src_clk_name = spi_src_clks[src_clk_nr];
} }
arch/arm/mach-s5p64x0/clock-s5p6440.c
View file @ cecd902a
...@@ -267,18 +267,6 @@ static struct clk init_clocks_off[] = { ...@@ -267,18 +267,6 @@ static struct clk init_clocks_off[] = {
.parent = &clk_pclk.clk, .parent = &clk_pclk.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 31), .ctrlbit = (1 << 31),
}, {
.name = "sclk_spi_48",
.devname = "s3c64xx-spi.0",
.parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 22),
}, {
.name = "sclk_spi_48",
.devname = "s3c64xx-spi.1",
.parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 23),
}, { }, {
.name = "mmc_48m", .name = "mmc_48m",
.devname = "s3c-sdhci.0", .devname = "s3c-sdhci.0",
...@@ -419,26 +407,6 @@ static struct clksrc_clk clksrcs[] = { ...@@ -419,26 +407,6 @@ static struct clksrc_clk clksrcs[] = {
.sources = &clkset_group1, .sources = &clkset_group1,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 }, .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
}, {
.clk = {
.name = "sclk_spi",
.devname = "s3c64xx-spi.0",
.ctrlbit = (1 << 20),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_spi",
.devname = "s3c64xx-spi.1",
.ctrlbit = (1 << 21),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
}, { }, {
.clk = { .clk = {
.name = "sclk_post", .name = "sclk_post",
...@@ -489,6 +457,30 @@ static struct clksrc_clk clk_sclk_uclk = { ...@@ -489,6 +457,30 @@ static struct clksrc_clk clk_sclk_uclk = {
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 }, .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
}; };
static struct clksrc_clk clk_sclk_spi0 = {
.clk = {
.name = "sclk_spi",
.devname = "s3c64xx-spi.0",
.ctrlbit = (1 << 20),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
};
static struct clksrc_clk clk_sclk_spi1 = {
.clk = {
.name = "sclk_spi",
.devname = "s3c64xx-spi.1",
.ctrlbit = (1 << 21),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
};
/* Clock initialization code */ /* Clock initialization code */
static struct clksrc_clk *sysclks[] = { static struct clksrc_clk *sysclks[] = {
&clk_mout_apll, &clk_mout_apll,
...@@ -509,11 +501,16 @@ static struct clk dummy_apb_pclk = { ...@@ -509,11 +501,16 @@ static struct clk dummy_apb_pclk = {
static struct clksrc_clk *clksrc_cdev[] = { static struct clksrc_clk *clksrc_cdev[] = {
&clk_sclk_uclk, &clk_sclk_uclk,
&clk_sclk_spi0,
&clk_sclk_spi1,
}; };
static struct clk_lookup s5p6440_clk_lookup[] = { static struct clk_lookup s5p6440_clk_lookup[] = {
CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
}; };
void __init_or_cpufreq s5p6440_setup_clocks(void) void __init_or_cpufreq s5p6440_setup_clocks(void)
......
arch/arm/mach-s5p64x0/clock-s5p6450.c
View file @ cecd902a
...@@ -441,26 +441,6 @@ static struct clksrc_clk clksrcs[] = { ...@@ -441,26 +441,6 @@ static struct clksrc_clk clksrcs[] = {
.sources = &clkset_group2, .sources = &clkset_group2,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 }, .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
}, {
.clk = {
.name = "sclk_spi",
.devname = "s3c64xx-spi.0",
.ctrlbit = (1 << 20),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_spi",
.devname = "s3c64xx-spi.1",
.ctrlbit = (1 << 21),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
}, { }, {
.clk = { .clk = {
.name = "sclk_fimc", .name = "sclk_fimc",
...@@ -538,13 +518,42 @@ static struct clksrc_clk clk_sclk_uclk = { ...@@ -538,13 +518,42 @@ static struct clksrc_clk clk_sclk_uclk = {
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 }, .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
}; };
static struct clksrc_clk clk_sclk_spi0 = {
.clk = {
.name = "sclk_spi",
.devname = "s3c64xx-spi.0",
.ctrlbit = (1 << 20),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
};
static struct clksrc_clk clk_sclk_spi1 = {
.clk = {
.name = "sclk_spi",
.devname = "s3c64xx-spi.1",
.ctrlbit = (1 << 21),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
};
static struct clksrc_clk *clksrc_cdev[] = { static struct clksrc_clk *clksrc_cdev[] = {
&clk_sclk_uclk, &clk_sclk_uclk,
&clk_sclk_spi0,
&clk_sclk_spi1,
}; };
static struct clk_lookup s5p6450_clk_lookup[] = { static struct clk_lookup s5p6450_clk_lookup[] = {
CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
}; };
/* Clock initialization code */ /* Clock initialization code */
......
arch/arm/mach-s5p64x0/dev-spi.c
View file @ cecd902a
...@@ -25,11 +25,6 @@ ...@@ -25,11 +25,6 @@
#include <plat/s3c64xx-spi.h> #include <plat/s3c64xx-spi.h>
#include <plat/gpio-cfg.h> #include <plat/gpio-cfg.h>
static char *s5p64x0_spi_src_clks[] = {
[S5P64X0_SPI_SRCCLK_PCLK] = "pclk",
[S5P64X0_SPI_SRCCLK_SCLK] = "sclk_spi",
};
/* SPI Controller platform_devices */ /* SPI Controller platform_devices */
/* Since we emulate multi-cs capability, we do not touch the CS. /* Since we emulate multi-cs capability, we do not touch the CS.
...@@ -220,5 +215,4 @@ void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) ...@@ -220,5 +215,4 @@ void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
pd->num_cs = num_cs; pd->num_cs = num_cs;
pd->src_clk_nr = src_clk_nr; pd->src_clk_nr = src_clk_nr;
pd->src_clk_name = s5p64x0_spi_src_clks[src_clk_nr];
} }
arch/arm/mach-s5pc100/clock.c
View file @ cecd902a
...@@ -654,24 +654,6 @@ static struct clk init_clocks_off[] = { ...@@ -654,24 +654,6 @@ static struct clk init_clocks_off[] = {
.parent = &clk_div_pclkd1.clk, .parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl, .enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
}, {
.name = "spi_48m",
.devname = "s3c64xx-spi.0",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "spi_48m",
.devname = "s3c64xx-spi.1",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "spi_48m",
.devname = "s3c64xx-spi.2",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 9),
}, { }, {
.name = "mmc_48m", .name = "mmc_48m",
.devname = "s3c-sdhci.0", .devname = "s3c-sdhci.0",
...@@ -717,6 +699,30 @@ static struct clk clk_hsmmc0 = { ...@@ -717,6 +699,30 @@ static struct clk clk_hsmmc0 = {
.ctrlbit = (1 << 5), .ctrlbit = (1 << 5),
}; };
static struct clk clk_48m_spi0 = {
.name = "spi_48m",
.devname = "s3c64xx-spi.0",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 7),
};
static struct clk clk_48m_spi1 = {
.name = "spi_48m",
.devname = "s3c64xx-spi.1",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 8),
};
static struct clk clk_48m_spi2 = {
.name = "spi_48m",
.devname = "s3c64xx-spi.2",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 9),
};
static struct clk clk_vclk54m = { static struct clk clk_vclk54m = {
.name = "vclk_54m", .name = "vclk_54m",
.rate = 54000000, .rate = 54000000,
...@@ -934,39 +940,6 @@ static struct clksrc_clk clk_sclk_spdif = { ...@@ -934,39 +940,6 @@ static struct clksrc_clk clk_sclk_spdif = {
static struct clksrc_clk clksrcs[] = { static struct clksrc_clk clksrcs[] = {
{ {
.clk = {
.name = "sclk_spi",
.devname = "s3c64xx-spi.0",
.ctrlbit = (1 << 4),
.enable = s5pc100_sclk0_ctrl,
},
.sources = &clk_src_group1,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
}, {
.clk = {
.name = "sclk_spi",
.devname = "s3c64xx-spi.1",
.ctrlbit = (1 << 5),
.enable = s5pc100_sclk0_ctrl,
},
.sources = &clk_src_group1,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
}, {
.clk = {
.name = "sclk_spi",
.devname = "s3c64xx-spi.2",
.ctrlbit = (1 << 6),
.enable = s5pc100_sclk0_ctrl,
},
.sources = &clk_src_group1,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
}, {
.clk = { .clk = {
.name = "sclk_mixer", .name = "sclk_mixer",
.ctrlbit = (1 << 6), .ctrlbit = (1 << 6),
...@@ -1108,6 +1081,42 @@ static struct clksrc_clk clk_sclk_mmc2 = { ...@@ -1108,6 +1081,42 @@ static struct clksrc_clk clk_sclk_mmc2 = {
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 }, .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
}; };
static struct clksrc_clk clk_sclk_spi0 = {
.clk = {
.name = "sclk_spi",
.devname = "s3c64xx-spi.0",
.ctrlbit = (1 << 4),
.enable = s5pc100_sclk0_ctrl,
},
.sources = &clk_src_group1,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
};
static struct clksrc_clk clk_sclk_spi1 = {
.clk = {
.name = "sclk_spi",
.devname = "s3c64xx-spi.1",
.ctrlbit = (1 << 5),
.enable = s5pc100_sclk0_ctrl,
},
.sources = &clk_src_group1,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
};
static struct clksrc_clk clk_sclk_spi2 = {
.clk = {
.name = "sclk_spi",
.devname = "s3c64xx-spi.2",
.ctrlbit = (1 << 6),
.enable = s5pc100_sclk0_ctrl,
},
.sources = &clk_src_group1,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
};
/* Clock initialisation code */ /* Clock initialisation code */
static struct clksrc_clk *sysclks[] = { static struct clksrc_clk *sysclks[] = {
&clk_mout_apll, &clk_mout_apll,
...@@ -1141,6 +1150,9 @@ static struct clk *clk_cdev[] = { ...@@ -1141,6 +1150,9 @@ static struct clk *clk_cdev[] = {
&clk_hsmmc0, &clk_hsmmc0,
&clk_hsmmc1, &clk_hsmmc1,
&clk_hsmmc2, &clk_hsmmc2,
&clk_48m_spi0,
&clk_48m_spi1,
&clk_48m_spi2,
}; };
static struct clksrc_clk *clksrc_cdev[] = { static struct clksrc_clk *clksrc_cdev[] = {
...@@ -1148,6 +1160,9 @@ static struct clksrc_clk *clksrc_cdev[] = { ...@@ -1148,6 +1160,9 @@ static struct clksrc_clk *clksrc_cdev[] = {
&clk_sclk_mmc0, &clk_sclk_mmc0,
&clk_sclk_mmc1, &clk_sclk_mmc1,
&clk_sclk_mmc2, &clk_sclk_mmc2,
&clk_sclk_spi0,
&clk_sclk_spi1,
&clk_sclk_spi2,
}; };
void __init_or_cpufreq s5pc100_setup_clocks(void) void __init_or_cpufreq s5pc100_setup_clocks(void)
...@@ -1298,6 +1313,13 @@ static struct clk_lookup s5pc100_clk_lookup[] = { ...@@ -1298,6 +1313,13 @@ static struct clk_lookup s5pc100_clk_lookup[] = {
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_48m_spi0),
CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_48m_spi1),
CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk1", &clk_48m_spi2),
CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
}; };
void __init s5pc100_register_clocks(void) void __init s5pc100_register_clocks(void)
......
arch/arm/mach-s5pc100/dev-spi.c
View file @ cecd902a
...@@ -21,12 +21,6 @@ ...@@ -21,12 +21,6 @@
#include <plat/gpio-cfg.h> #include <plat/gpio-cfg.h>
#include <plat/irqs.h> #include <plat/irqs.h>
static char *spi_src_clks[] = {
[S5PC100_SPI_SRCCLK_PCLK] = "pclk",
[S5PC100_SPI_SRCCLK_48M] = "spi_48m",
[S5PC100_SPI_SRCCLK_SPIBUS] = "spi_bus",
};
/* SPI Controller platform_devices */ /* SPI Controller platform_devices */
/* Since we emulate multi-cs capability, we do not touch the CS. /* Since we emulate multi-cs capability, we do not touch the CS.
...@@ -223,5 +217,4 @@ void __init s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) ...@@ -223,5 +217,4 @@ void __init s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
pd->num_cs = num_cs; pd->num_cs = num_cs;
pd->src_clk_nr = src_clk_nr; pd->src_clk_nr = src_clk_nr;
pd->src_clk_name = spi_src_clks[src_clk_nr];
} }
arch/arm/mach-s5pv210/clock.c
View file @ cecd902a
...@@ -909,26 +909,6 @@ static struct clksrc_clk clksrcs[] = { ...@@ -909,26 +909,6 @@ static struct clksrc_clk clksrcs[] = {
.sources = &clkset_group2, .sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 }, .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 }, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
}, {
.clk = {
.name = "sclk_spi",
.devname = "s3c64xx-spi.0",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 16),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_spi",
.devname = "s3c64xx-spi.1",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 17),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
}, { }, {
.clk = { .clk = {
.name = "sclk_pwi", .name = "sclk_pwi",
...@@ -1046,6 +1026,31 @@ static struct clksrc_clk clk_sclk_mmc3 = { ...@@ -1046,6 +1026,31 @@ static struct clksrc_clk clk_sclk_mmc3 = {
.reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 }, .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
}; };
static struct clksrc_clk clk_sclk_spi0 = {
.clk = {
.name = "sclk_spi",
.devname = "s3c64xx-spi.0",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 16),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
};
static struct clksrc_clk clk_sclk_spi1 = {
.clk = {
.name = "sclk_spi",
.devname = "s3c64xx-spi.1",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 17),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
};
static struct clksrc_clk *clksrc_cdev[] = { static struct clksrc_clk *clksrc_cdev[] = {
&clk_sclk_uart0, &clk_sclk_uart0,
&clk_sclk_uart1, &clk_sclk_uart1,
...@@ -1055,6 +1060,8 @@ static struct clksrc_clk *clksrc_cdev[] = { ...@@ -1055,6 +1060,8 @@ static struct clksrc_clk *clksrc_cdev[] = {
&clk_sclk_mmc1, &clk_sclk_mmc1,
&clk_sclk_mmc2, &clk_sclk_mmc2,
&clk_sclk_mmc3, &clk_sclk_mmc3,
&clk_sclk_spi0,
&clk_sclk_spi1,
}; };
static struct clk *clk_cdev[] = { static struct clk *clk_cdev[] = {
...@@ -1317,6 +1324,9 @@ static struct clk_lookup s5pv210_clk_lookup[] = { ...@@ -1317,6 +1324,9 @@ static struct clk_lookup s5pv210_clk_lookup[] = {
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
}; };
void __init s5pv210_register_clocks(void) void __init s5pv210_register_clocks(void)
......
arch/arm/mach-s5pv210/dev-spi.c
View file @ cecd902a
...@@ -20,11 +20,6 @@ ...@@ -20,11 +20,6 @@
#include <plat/s3c64xx-spi.h> #include <plat/s3c64xx-spi.h>
#include <plat/gpio-cfg.h> #include <plat/gpio-cfg.h>
static char *spi_src_clks[] = {
[S5PV210_SPI_SRCCLK_PCLK] = "pclk",
[S5PV210_SPI_SRCCLK_SCLK] = "sclk_spi",
};
/* SPI Controller platform_devices */ /* SPI Controller platform_devices */
/* Since we emulate multi-cs capability, we do not touch the CS. /* Since we emulate multi-cs capability, we do not touch the CS.
...@@ -171,5 +166,4 @@ void __init s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) ...@@ -171,5 +166,4 @@ void __init s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
pd->num_cs = num_cs; pd->num_cs = num_cs;
pd->src_clk_nr = src_clk_nr; pd->src_clk_nr = src_clk_nr;
pd->src_clk_name = spi_src_clks[src_clk_nr];
} }
arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
View file @ cecd902a
...@@ -31,7 +31,6 @@ struct s3c64xx_spi_csinfo { ...@@ -31,7 +31,6 @@ struct s3c64xx_spi_csinfo {
/** /**
* struct s3c64xx_spi_info - SPI Controller defining structure * struct s3c64xx_spi_info - SPI Controller defining structure
* @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field. * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
* @src_clk_name: Platform name of the corresponding clock.
* @clk_from_cmu: If the SPI clock/prescalar control block is present * @clk_from_cmu: If the SPI clock/prescalar control block is present
* by the platform's clock-management-unit and not in SPI controller. * by the platform's clock-management-unit and not in SPI controller.
* @num_cs: Number of CS this controller emulates. * @num_cs: Number of CS this controller emulates.
...@@ -43,7 +42,6 @@ struct s3c64xx_spi_csinfo { ...@@ -43,7 +42,6 @@ struct s3c64xx_spi_csinfo {
*/ */
struct s3c64xx_spi_info { struct s3c64xx_spi_info {
int src_clk_nr; int src_clk_nr;
char *src_clk_name;
bool clk_from_cmu; bool clk_from_cmu;
int num_cs; int num_cs;
......
drivers/spi/spi-s3c64xx.c
View file @ cecd902a
...@@ -971,6 +971,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev) ...@@ -971,6 +971,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
struct s3c64xx_spi_info *sci; struct s3c64xx_spi_info *sci;
struct spi_master *master; struct spi_master *master;
int ret; int ret;
char clk_name[16];
if (pdev->id < 0) { if (pdev->id < 0) {
dev_err(&pdev->dev, dev_err(&pdev->dev,
...@@ -984,11 +985,6 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev) ...@@ -984,11 +985,6 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
} }
sci = pdev->dev.platform_data; sci = pdev->dev.platform_data;
if (!sci->src_clk_name) {
dev_err(&pdev->dev,
"Board init must call s3c64xx_spi_set_info()\n");
return -EINVAL;
}
/* Check for availability of necessary resource */ /* Check for availability of necessary resource */
...@@ -1073,17 +1069,17 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev) ...@@ -1073,17 +1069,17 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
goto err4; goto err4;
} }
sdd->src_clk = clk_get(&pdev->dev, sci->src_clk_name); sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
sdd->src_clk = clk_get(&pdev->dev, clk_name);
if (IS_ERR(sdd->src_clk)) { if (IS_ERR(sdd->src_clk)) {
dev_err(&pdev->dev, dev_err(&pdev->dev,
"Unable to acquire clock '%s'\n", sci->src_clk_name); "Unable to acquire clock '%s'\n", clk_name);
ret = PTR_ERR(sdd->src_clk); ret = PTR_ERR(sdd->src_clk);
goto err5; goto err5;
} }
if (clk_enable(sdd->src_clk)) { if (clk_enable(sdd->src_clk)) {
dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
sci->src_clk_name);
ret = -EBUSY; ret = -EBUSY;
goto err6; goto err6;
} }
......
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