Commit d0233204 authored by Rosen Penev's avatar Rosen Penev Committed by Greg Kroah-Hartman

staging: mt7621-dts: Fix remaining pcie warnings

This currently fixes the remaining dtb warnings:

Node /pcie@1e140000/pcie0 has a reg or ranges property, but no unit name
Node /pcie@1e140000/pcie1 has a reg or ranges property, but no unit name
Node /pcie@1e140000/pcie2 has a reg or ranges property, but no unit name
Node /pcie@1e140000/pcie0 node name is not "pci" or "pcie"
Node /pcie@1e140000/pcie0 missing ranges for PCI bridge (or not a bridge)
Node /pcie@1e140000/pcie0 missing bus-range for PCI bridge
Node /pcie@1e140000/pcie1 node name is not "pci" or "pcie"
Node /pcie@1e140000/pcie1 missing ranges for PCI bridge (or not a bridge)
Node /pcie@1e140000/pcie1 missing bus-range for PCI bridge
Node /pcie@1e140000/pcie2 node name is not "pci" or "pcie"
Node /pcie@1e140000/pcie2 missing ranges for PCI bridge (or not a bridge)
Node /pcie@1e140000/pcie2 missing bus-range for PCI bridge
Warning (unit_address_format): Failed prerequisite 'pci_bridge'
Warning (pci_device_reg): Failed prerequisite 'pci_bridge'
Warning (pci_device_bus_num): Failed prerequisite 'pci_bridge'

device_type was removed since according to documentation, it's deprecated
for pci(e) devices.
Signed-off-by: default avatarRosen Penev <rosenp@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 37071327
...@@ -111,6 +111,8 @@ &cpuclock { ...@@ -111,6 +111,8 @@ &cpuclock {
}; };
&pcie { &pcie {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
status = "okay"; status = "okay";
}; };
......
...@@ -447,31 +447,28 @@ pcie: pcie@1e140000 { ...@@ -447,31 +447,28 @@ pcie: pcie@1e140000 {
clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>; clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
clock-names = "pcie0", "pcie1", "pcie2"; clock-names = "pcie0", "pcie1", "pcie2";
pcie0 { pcie@0,0 {
reg = <0x0000 0 0 0 0>; reg = <0x0000 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
ranges;
device_type = "pci"; bus-range = <0x00 0xff>;
}; };
pcie1 { pcie@1,0 {
reg = <0x0800 0 0 0 0>; reg = <0x0800 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
ranges;
device_type = "pci"; bus-range = <0x00 0xff>;
}; };
pcie2 { pcie@2,0 {
reg = <0x1000 0 0 0 0>; reg = <0x1000 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
ranges;
device_type = "pci"; bus-range = <0x00 0xff>;
}; };
}; };
}; };
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