Commit d0ba51b1 authored by Felix Kuehling's avatar Felix Kuehling Committed by Alex Deucher

drm/amdgpu: Determing PTE flags separately for each mapping (v3)

The same BO can be mapped with different PTE flags by different GPUs.
Therefore determine the PTE flags separately for each mapping instead
of storing them in the KFD buffer object.

Add a helper function to determine the PTE flags to be extended with
ASIC and memory-type-specific logic in subsequent commits.

v2: Split Arcturus-specific MTYPE changes into separate commit
v3: Fix return type of get_pte_flags to uint64_t
Signed-off-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarShaoyun Liu <Shaoyun.Liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 093e48c0
...@@ -57,7 +57,7 @@ struct kgd_mem { ...@@ -57,7 +57,7 @@ struct kgd_mem {
unsigned int mapped_to_gpu_memory; unsigned int mapped_to_gpu_memory;
uint64_t va; uint64_t va;
uint32_t mapping_flags; uint32_t alloc_flags;
atomic_t invalid; atomic_t invalid;
struct amdkfd_process_info *process_info; struct amdkfd_process_info *process_info;
......
...@@ -356,6 +356,23 @@ static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync) ...@@ -356,6 +356,23 @@ static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
return amdgpu_sync_fence(NULL, sync, vm->last_update, false); return amdgpu_sync_fence(NULL, sync, vm->last_update, false);
} }
static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
{
bool coherent = mem->alloc_flags & ALLOC_MEM_FLAGS_COHERENT;
uint32_t mapping_flags;
mapping_flags = AMDGPU_VM_PAGE_READABLE;
if (mem->alloc_flags & ALLOC_MEM_FLAGS_WRITABLE)
mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
if (mem->alloc_flags & ALLOC_MEM_FLAGS_EXECUTABLE)
mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
mapping_flags |= coherent ?
AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
return amdgpu_gmc_get_pte_flags(adev, mapping_flags);
}
/* add_bo_to_vm - Add a BO to a VM /* add_bo_to_vm - Add a BO to a VM
* *
* Everything that needs to bo done only once when a BO is first added * Everything that needs to bo done only once when a BO is first added
...@@ -404,8 +421,7 @@ static int add_bo_to_vm(struct amdgpu_device *adev, struct kgd_mem *mem, ...@@ -404,8 +421,7 @@ static int add_bo_to_vm(struct amdgpu_device *adev, struct kgd_mem *mem,
} }
bo_va_entry->va = va; bo_va_entry->va = va;
bo_va_entry->pte_flags = amdgpu_gmc_get_pte_flags(adev, bo_va_entry->pte_flags = get_pte_flags(adev, mem);
mem->mapping_flags);
bo_va_entry->kgd_dev = (void *)adev; bo_va_entry->kgd_dev = (void *)adev;
list_add(&bo_va_entry->bo_list, list_bo_va); list_add(&bo_va_entry->bo_list, list_bo_va);
...@@ -1082,7 +1098,6 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( ...@@ -1082,7 +1098,6 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
int byte_align; int byte_align;
u32 domain, alloc_domain; u32 domain, alloc_domain;
u64 alloc_flags; u64 alloc_flags;
uint32_t mapping_flags;
int ret; int ret;
/* /*
...@@ -1144,16 +1159,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( ...@@ -1144,16 +1159,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
adev->asic_type != CHIP_VEGAM) ? adev->asic_type != CHIP_VEGAM) ?
VI_BO_SIZE_ALIGN : 1; VI_BO_SIZE_ALIGN : 1;
mapping_flags = AMDGPU_VM_PAGE_READABLE; (*mem)->alloc_flags = flags;
if (flags & ALLOC_MEM_FLAGS_WRITABLE)
mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
if (flags & ALLOC_MEM_FLAGS_EXECUTABLE)
mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
if (flags & ALLOC_MEM_FLAGS_COHERENT)
mapping_flags |= AMDGPU_VM_MTYPE_UC;
else
mapping_flags |= AMDGPU_VM_MTYPE_NC;
(*mem)->mapping_flags = mapping_flags;
amdgpu_sync_create(&(*mem)->sync); amdgpu_sync_create(&(*mem)->sync);
...@@ -1626,9 +1632,10 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd, ...@@ -1626,9 +1632,10 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd,
INIT_LIST_HEAD(&(*mem)->bo_va_list); INIT_LIST_HEAD(&(*mem)->bo_va_list);
mutex_init(&(*mem)->lock); mutex_init(&(*mem)->lock);
(*mem)->mapping_flags = (*mem)->alloc_flags =
AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_NC; ALLOC_MEM_FLAGS_VRAM : ALLOC_MEM_FLAGS_GTT) |
ALLOC_MEM_FLAGS_WRITABLE | ALLOC_MEM_FLAGS_EXECUTABLE;
(*mem)->bo = amdgpu_bo_ref(bo); (*mem)->bo = amdgpu_bo_ref(bo);
(*mem)->va = va; (*mem)->va = va;
......
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