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Commit d15be546 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'media/v5.8-3' of... 

Merge tag 'media/v5.8-3' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media into master

Pull media fixes from Mauro Carvalho Chehab:
 "A series of fixes for the upcoming atomisp driver. They solve issues
  when probing atomisp on devices with multiple cameras and get rid of
  warnings when built with W=1.

  The diffstat is a bit long, as this driver has several abstractions.
  The patches that solved the issues with W=1 had to get rid of some
  duplicated code (there used to have 2 versions of the same code, one
  for ISP2401 and another one for ISP2400).

  As this driver is not in 5.7, such changes won't cause regressions"

* tag 'media/v5.8-3' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (38 commits)
  Revert "media: atomisp: keep the ISP powered on when setting it"
  media: atomisp: fix mask and shift operation on ISPSSPM0
  media: atomisp: move system_local consts into a C file
  media: atomisp: get rid of version-specific system_local.h
  media: atomisp: move global stuff into a common header
  media: atomisp: remove non-used 32-bits consts at system_local
  media: atomisp: get rid of some unused static vars
  media: atomisp: Fix error code in ov5693_probe()
  media: atomisp: Replace trace_printk by pr_info
  media: atomisp: Fix __func__ style warnings
  media: atomisp: fix help message for ISP2401 selection
  media: atomisp: i2c: atomisp-ov2680.c: fixed a brace coding style issue.
  media: atomisp: make const arrays static, makes object smaller
  media: atomisp: Clean up non-existing folders from Makefile
  media: atomisp: Get rid of ACPI specifics in gmin_subdev_add()
  media: atomisp: Provide Gmin subdev as parameter to gmin_subdev_add()
  media: atomisp: Use temporary variable for device in gmin_subdev_add()
  media: atomisp: Refactor PMIC detection to a separate function
  media: atomisp: Deduplicate return ret in gmin_i2c_write()
  media: atomisp: Make pointer to PMIC client global
  ...
parents 071fb1bc 0d6db851
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Showing with 1280 additions and 1527 deletions
arch/x86/include/asm/iosf_mbi.h
View file @ d15be546
...@@ -39,6 +39,7 @@ ...@@ -39,6 +39,7 @@
#define BT_MBI_UNIT_PMC 0x04 #define BT_MBI_UNIT_PMC 0x04
#define BT_MBI_UNIT_GFX 0x06 #define BT_MBI_UNIT_GFX 0x06
#define BT_MBI_UNIT_SMI 0x0C #define BT_MBI_UNIT_SMI 0x0C
#define BT_MBI_UNIT_CCK 0x14
#define BT_MBI_UNIT_USB 0x43 #define BT_MBI_UNIT_USB 0x43
#define BT_MBI_UNIT_SATA 0xA3 #define BT_MBI_UNIT_SATA 0xA3
#define BT_MBI_UNIT_PCIE 0xA6 #define BT_MBI_UNIT_PCIE 0xA6
......
drivers/staging/media/atomisp/Kconfig
View file @ d15be546
...@@ -22,7 +22,7 @@ config VIDEO_ATOMISP ...@@ -22,7 +22,7 @@ config VIDEO_ATOMISP
module will be called atomisp module will be called atomisp
config VIDEO_ATOMISP_ISP2401 config VIDEO_ATOMISP_ISP2401
bool "VIDEO_ATOMISP_ISP2401" bool "Use Intel Atom ISP on Cherrytail/Anniedale (ISP2401)"
depends on VIDEO_ATOMISP depends on VIDEO_ATOMISP
help help
Enable support for Atom ISP2401-based boards. Enable support for Atom ISP2401-based boards.
......
drivers/staging/media/atomisp/Makefile
View file @ d15be546
...@@ -156,6 +156,7 @@ atomisp-objs += \ ...@@ -156,6 +156,7 @@ atomisp-objs += \
pci/hive_isp_css_common/host/timed_ctrl.o \ pci/hive_isp_css_common/host/timed_ctrl.o \
pci/hive_isp_css_common/host/vmem.o \ pci/hive_isp_css_common/host/vmem.o \
pci/hive_isp_css_shared/host/tag.o \ pci/hive_isp_css_shared/host/tag.o \
pci/system_local.o \
obj-byt = \ obj-byt = \
pci/css_2400_system/hive/ia_css_isp_configs.o \ pci/css_2400_system/hive/ia_css_isp_configs.o \
...@@ -182,7 +183,6 @@ INCLUDES += \ ...@@ -182,7 +183,6 @@ INCLUDES += \
-I$(atomisp)/include/hmm/ \ -I$(atomisp)/include/hmm/ \
-I$(atomisp)/include/mmu/ \ -I$(atomisp)/include/mmu/ \
-I$(atomisp)/pci/ \ -I$(atomisp)/pci/ \
-I$(atomisp)/pci/hrt/ \
-I$(atomisp)/pci/base/circbuf/interface/ \ -I$(atomisp)/pci/base/circbuf/interface/ \
-I$(atomisp)/pci/base/refcount/interface/ \ -I$(atomisp)/pci/base/refcount/interface/ \
-I$(atomisp)/pci/camera/pipe/interface/ \ -I$(atomisp)/pci/camera/pipe/interface/ \
...@@ -192,7 +192,6 @@ INCLUDES += \ ...@@ -192,7 +192,6 @@ INCLUDES += \
-I$(atomisp)/pci/hive_isp_css_include/ \ -I$(atomisp)/pci/hive_isp_css_include/ \
-I$(atomisp)/pci/hive_isp_css_include/device_access/ \ -I$(atomisp)/pci/hive_isp_css_include/device_access/ \
-I$(atomisp)/pci/hive_isp_css_include/host/ \ -I$(atomisp)/pci/hive_isp_css_include/host/ \
-I$(atomisp)/pci/hive_isp_css_include/memory_access/ \
-I$(atomisp)/pci/hive_isp_css_shared/ \ -I$(atomisp)/pci/hive_isp_css_shared/ \
-I$(atomisp)/pci/hive_isp_css_shared/host/ \ -I$(atomisp)/pci/hive_isp_css_shared/host/ \
-I$(atomisp)/pci/isp/kernels/ \ -I$(atomisp)/pci/isp/kernels/ \
...@@ -311,9 +310,7 @@ INCLUDES += \ ...@@ -311,9 +310,7 @@ INCLUDES += \
-I$(atomisp)/pci/runtime/tagger/interface/ -I$(atomisp)/pci/runtime/tagger/interface/
INCLUDES_byt += \ INCLUDES_byt += \
-I$(atomisp)/pci/css_2400_system/ \
-I$(atomisp)/pci/css_2400_system/hive/ \ -I$(atomisp)/pci/css_2400_system/hive/ \
-I$(atomisp)/pci/css_2400_system/hrt/ \
INCLUDES_cht += \ INCLUDES_cht += \
-I$(atomisp)/pci/css_2401_system/ \ -I$(atomisp)/pci/css_2401_system/ \
...@@ -321,7 +318,6 @@ INCLUDES_cht += \ ...@@ -321,7 +318,6 @@ INCLUDES_cht += \
-I$(atomisp)/pci/css_2401_system/hive/ \ -I$(atomisp)/pci/css_2401_system/hive/ \
-I$(atomisp)/pci/css_2401_system/hrt/ \ -I$(atomisp)/pci/css_2401_system/hrt/ \
# -I$(atomisp)/pci/css_2401_system/hrt/ \
# -I$(atomisp)/pci/css_2401_system/hive_isp_css_2401_system_generated/ \ # -I$(atomisp)/pci/css_2401_system/hive_isp_css_2401_system_generated/ \
DEFINES := -DHRT_HW -DHRT_ISP_CSS_CUSTOM_HOST -DHRT_USE_VIR_ADDRS -D__HOST__ DEFINES := -DHRT_HW -DHRT_ISP_CSS_CUSTOM_HOST -DHRT_USE_VIR_ADDRS -D__HOST__
......
drivers/staging/media/atomisp/i2c/atomisp-ov2680.c
View file @ d15be546
...@@ -495,11 +495,11 @@ static int ov2680_h_flip(struct v4l2_subdev *sd, s32 value) ...@@ -495,11 +495,11 @@ static int ov2680_h_flip(struct v4l2_subdev *sd, s32 value)
ret = ov2680_read_reg(client, 1, OV2680_MIRROR_REG, &val); ret = ov2680_read_reg(client, 1, OV2680_MIRROR_REG, &val);
if (ret) if (ret)
return ret; return ret;
if (value) { if (value)
val |= OV2680_FLIP_MIRROR_BIT_ENABLE; val |= OV2680_FLIP_MIRROR_BIT_ENABLE;
} else { else
val &= ~OV2680_FLIP_MIRROR_BIT_ENABLE; val &= ~OV2680_FLIP_MIRROR_BIT_ENABLE;
}
ret = ov2680_write_reg(client, 1, ret = ov2680_write_reg(client, 1,
OV2680_MIRROR_REG, val); OV2680_MIRROR_REG, val);
if (ret) if (ret)
......
drivers/staging/media/atomisp/i2c/ov5693/atomisp-ov5693.c
View file @ d15be546
...@@ -1899,7 +1899,7 @@ static int ov5693_probe(struct i2c_client *client) ...@@ -1899,7 +1899,7 @@ static int ov5693_probe(struct i2c_client *client)
{ {
struct ov5693_device *dev; struct ov5693_device *dev;
int i2c; int i2c;
int ret = 0; int ret;
void *pdata; void *pdata;
unsigned int i; unsigned int i;
...@@ -1929,8 +1929,10 @@ static int ov5693_probe(struct i2c_client *client) ...@@ -1929,8 +1929,10 @@ static int ov5693_probe(struct i2c_client *client)
pdata = gmin_camera_platform_data(&dev->sd, pdata = gmin_camera_platform_data(&dev->sd,
ATOMISP_INPUT_FORMAT_RAW_10, ATOMISP_INPUT_FORMAT_RAW_10,
atomisp_bayer_order_bggr); atomisp_bayer_order_bggr);
if (!pdata) if (!pdata) {
ret = -EINVAL;
goto out_free; goto out_free;
}
ret = ov5693_s_config(&dev->sd, client->irq, pdata); ret = ov5693_s_config(&dev->sd, client->irq, pdata);
if (ret) if (ret)
......
drivers/staging/media/atomisp/include/linux/atomisp_platform.h
View file @ d15be546
...@@ -250,6 +250,7 @@ const struct atomisp_camera_caps *atomisp_get_default_camera_caps(void); ...@@ -250,6 +250,7 @@ const struct atomisp_camera_caps *atomisp_get_default_camera_caps(void);
#define IS_MFLD __IS_SOC(INTEL_FAM6_ATOM_SALTWELL_MID) #define IS_MFLD __IS_SOC(INTEL_FAM6_ATOM_SALTWELL_MID)
#define IS_BYT __IS_SOC(INTEL_FAM6_ATOM_SILVERMONT) #define IS_BYT __IS_SOC(INTEL_FAM6_ATOM_SILVERMONT)
#define IS_CHT __IS_SOC(INTEL_FAM6_ATOM_AIRMONT) #define IS_CHT __IS_SOC(INTEL_FAM6_ATOM_AIRMONT)
#define IS_MRFD __IS_SOC(INTEL_FAM6_ATOM_SILVERMONT_MID)
#define IS_MOFD __IS_SOC(INTEL_FAM6_ATOM_AIRMONT_MID) #define IS_MOFD __IS_SOC(INTEL_FAM6_ATOM_AIRMONT_MID)
/* Both CHT and MOFD come with ISP2401 */ /* Both CHT and MOFD come with ISP2401 */
......
drivers/staging/media/atomisp/pci/atomisp-regs.h
View file @ d15be546
...@@ -20,9 +20,6 @@ ...@@ -20,9 +20,6 @@
#define ATOMISP_REGS_H #define ATOMISP_REGS_H
/* common register definitions */ /* common register definitions */
#define PUNIT_PORT 0x04
#define CCK_PORT 0x14
#define PCICMDSTS 0x01 #define PCICMDSTS 0x01
#define INTR 0x0f #define INTR 0x0f
#define MSI_CAPID 0x24 #define MSI_CAPID 0x24
......
drivers/staging/media/atomisp/pci/atomisp_acc.c
View file @ d15be546
...@@ -355,11 +355,11 @@ int atomisp_acc_map(struct atomisp_sub_device *asd, struct atomisp_acc_map *map) ...@@ -355,11 +355,11 @@ int atomisp_acc_map(struct atomisp_sub_device *asd, struct atomisp_acc_map *map)
pgnr = DIV_ROUND_UP(map->length, PAGE_SIZE); pgnr = DIV_ROUND_UP(map->length, PAGE_SIZE);
if (pgnr < ((PAGE_ALIGN(map->length)) >> PAGE_SHIFT)) { if (pgnr < ((PAGE_ALIGN(map->length)) >> PAGE_SHIFT)) {
dev_err(atomisp_dev, dev_err(asd->isp->dev,
"user space memory size is less than the expected size..\n"); "user space memory size is less than the expected size..\n");
return -ENOMEM; return -ENOMEM;
} else if (pgnr > ((PAGE_ALIGN(map->length)) >> PAGE_SHIFT)) { } else if (pgnr > ((PAGE_ALIGN(map->length)) >> PAGE_SHIFT)) {
dev_err(atomisp_dev, dev_err(asd->isp->dev,
"user space memory size is large than the expected size..\n"); "user space memory size is large than the expected size..\n");
return -ENOMEM; return -ENOMEM;
} }
......
drivers/staging/media/atomisp/pci/atomisp_cmd.c
View file @ d15be546
...@@ -21,6 +21,7 @@ ...@@ -21,6 +21,7 @@
#include <linux/firmware.h> #include <linux/firmware.h>
#include <linux/pci.h> #include <linux/pci.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/kfifo.h> #include <linux/kfifo.h>
#include <linux/pm_runtime.h> #include <linux/pm_runtime.h>
...@@ -109,7 +110,7 @@ struct atomisp_acc_pipe *atomisp_to_acc_pipe(struct video_device *dev) ...@@ -109,7 +110,7 @@ struct atomisp_acc_pipe *atomisp_to_acc_pipe(struct video_device *dev)
static unsigned short atomisp_get_sensor_fps(struct atomisp_sub_device *asd) static unsigned short atomisp_get_sensor_fps(struct atomisp_sub_device *asd)
{ {
struct v4l2_subdev_frame_interval fi; struct v4l2_subdev_frame_interval fi = { 0 };
struct atomisp_device *isp = asd->isp; struct atomisp_device *isp = asd->isp;
unsigned short fps = 0; unsigned short fps = 0;
...@@ -206,6 +207,7 @@ int atomisp_freq_scaling(struct atomisp_device *isp, ...@@ -206,6 +207,7 @@ int atomisp_freq_scaling(struct atomisp_device *isp,
enum atomisp_dfs_mode mode, enum atomisp_dfs_mode mode,
bool force) bool force)
{ {
struct pci_dev *pdev = to_pci_dev(isp->dev);
/* FIXME! Only use subdev[0] status yet */ /* FIXME! Only use subdev[0] status yet */
struct atomisp_sub_device *asd = &isp->asd[0]; struct atomisp_sub_device *asd = &isp->asd[0];
const struct atomisp_dfs_config *dfs; const struct atomisp_dfs_config *dfs;
...@@ -219,7 +221,7 @@ int atomisp_freq_scaling(struct atomisp_device *isp, ...@@ -219,7 +221,7 @@ int atomisp_freq_scaling(struct atomisp_device *isp,
return -EINVAL; return -EINVAL;
} }
if ((isp->pdev->device & ATOMISP_PCI_DEVICE_SOC_MASK) == if ((pdev->device & ATOMISP_PCI_DEVICE_SOC_MASK) ==
ATOMISP_PCI_DEVICE_SOC_CHT && ATOMISP_USE_YUVPP(asd)) ATOMISP_PCI_DEVICE_SOC_CHT && ATOMISP_USE_YUVPP(asd))
isp->dfs = &dfs_config_cht_soc; isp->dfs = &dfs_config_cht_soc;
...@@ -357,39 +359,41 @@ static void clear_isp_irq(enum hrt_isp_css_irq irq) ...@@ -357,39 +359,41 @@ static void clear_isp_irq(enum hrt_isp_css_irq irq)
irq_clear_all(IRQ0_ID); irq_clear_all(IRQ0_ID);
} }
void atomisp_msi_irq_init(struct atomisp_device *isp, struct pci_dev *dev) void atomisp_msi_irq_init(struct atomisp_device *isp)
{ {
struct pci_dev *pdev = to_pci_dev(isp->dev);
u32 msg32; u32 msg32;
u16 msg16; u16 msg16;
pci_read_config_dword(dev, PCI_MSI_CAPID, &msg32); pci_read_config_dword(pdev, PCI_MSI_CAPID, &msg32);
msg32 |= 1 << MSI_ENABLE_BIT; msg32 |= 1 << MSI_ENABLE_BIT;
pci_write_config_dword(dev, PCI_MSI_CAPID, msg32); pci_write_config_dword(pdev, PCI_MSI_CAPID, msg32);
msg32 = (1 << INTR_IER) | (1 << INTR_IIR); msg32 = (1 << INTR_IER) | (1 << INTR_IIR);
pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, msg32); pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, msg32);
pci_read_config_word(dev, PCI_COMMAND, &msg16); pci_read_config_word(pdev, PCI_COMMAND, &msg16);
msg16 |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | msg16 |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
PCI_COMMAND_INTX_DISABLE); PCI_COMMAND_INTX_DISABLE);
pci_write_config_word(dev, PCI_COMMAND, msg16); pci_write_config_word(pdev, PCI_COMMAND, msg16);
} }
void atomisp_msi_irq_uninit(struct atomisp_device *isp, struct pci_dev *dev) void atomisp_msi_irq_uninit(struct atomisp_device *isp)
{ {
struct pci_dev *pdev = to_pci_dev(isp->dev);
u32 msg32; u32 msg32;
u16 msg16; u16 msg16;
pci_read_config_dword(dev, PCI_MSI_CAPID, &msg32); pci_read_config_dword(pdev, PCI_MSI_CAPID, &msg32);
msg32 &= ~(1 << MSI_ENABLE_BIT); msg32 &= ~(1 << MSI_ENABLE_BIT);
pci_write_config_dword(dev, PCI_MSI_CAPID, msg32); pci_write_config_dword(pdev, PCI_MSI_CAPID, msg32);
msg32 = 0x0; msg32 = 0x0;
pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, msg32); pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, msg32);
pci_read_config_word(dev, PCI_COMMAND, &msg16); pci_read_config_word(pdev, PCI_COMMAND, &msg16);
msg16 &= ~(PCI_COMMAND_MASTER); msg16 &= ~(PCI_COMMAND_MASTER);
pci_write_config_word(dev, PCI_COMMAND, msg16); pci_write_config_word(pdev, PCI_COMMAND, msg16);
} }
static void atomisp_sof_event(struct atomisp_sub_device *asd) static void atomisp_sof_event(struct atomisp_sub_device *asd)
...@@ -480,11 +484,12 @@ static void print_csi_rx_errors(enum mipi_port_id port, ...@@ -480,11 +484,12 @@ static void print_csi_rx_errors(enum mipi_port_id port,
/* Clear irq reg */ /* Clear irq reg */
static void clear_irq_reg(struct atomisp_device *isp) static void clear_irq_reg(struct atomisp_device *isp)
{ {
struct pci_dev *pdev = to_pci_dev(isp->dev);
u32 msg_ret; u32 msg_ret;
pci_read_config_dword(isp->pdev, PCI_INTERRUPT_CTRL, &msg_ret); pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &msg_ret);
msg_ret |= 1 << INTR_IIR; msg_ret |= 1 << INTR_IIR;
pci_write_config_dword(isp->pdev, PCI_INTERRUPT_CTRL, msg_ret); pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, msg_ret);
} }
static struct atomisp_sub_device * static struct atomisp_sub_device *
...@@ -665,11 +670,10 @@ bool atomisp_buffers_queued_pipe(struct atomisp_video_pipe *pipe) ...@@ -665,11 +670,10 @@ bool atomisp_buffers_queued_pipe(struct atomisp_video_pipe *pipe)
void dump_sp_dmem(struct atomisp_device *isp, unsigned int addr, void dump_sp_dmem(struct atomisp_device *isp, unsigned int addr,
unsigned int size) unsigned int size)
{ {
u32 __iomem *io_virt_addr;
unsigned int data = 0; unsigned int data = 0;
unsigned int size32 = DIV_ROUND_UP(size, sizeof(u32)); unsigned int size32 = DIV_ROUND_UP(size, sizeof(u32));
dev_dbg(isp->dev, "atomisp_io_base:%p\n", atomisp_io_base); dev_dbg(isp->dev, "atomisp mmio base: %p\n", isp->base);
dev_dbg(isp->dev, "%s, addr:0x%x, size: %d, size32: %d\n", __func__, dev_dbg(isp->dev, "%s, addr:0x%x, size: %d, size32: %d\n", __func__,
addr, size, size32); addr, size, size32);
if (size32 * 4 + addr > 0x4000) { if (size32 * 4 + addr > 0x4000) {
...@@ -678,13 +682,12 @@ void dump_sp_dmem(struct atomisp_device *isp, unsigned int addr, ...@@ -678,13 +682,12 @@ void dump_sp_dmem(struct atomisp_device *isp, unsigned int addr,
return; return;
} }
addr += SP_DMEM_BASE; addr += SP_DMEM_BASE;
io_virt_addr = atomisp_io_base + (addr & 0x003FFFFF); addr &= 0x003FFFFF;
do { do {
data = *io_virt_addr; data = readl(isp->base + addr);
dev_dbg(isp->dev, "%s, \t [0x%x]:0x%x\n", __func__, addr, data); dev_dbg(isp->dev, "%s, \t [0x%x]:0x%x\n", __func__, addr, data);
io_virt_addr += sizeof(u32); addr += sizeof(u32);
size32 -= 1; } while (--size32);
} while (size32 > 0);
} }
static struct videobuf_buffer *atomisp_css_frame_to_vbuf( static struct videobuf_buffer *atomisp_css_frame_to_vbuf(
...@@ -1289,6 +1292,7 @@ void atomisp_delayed_init_work(struct work_struct *work) ...@@ -1289,6 +1292,7 @@ void atomisp_delayed_init_work(struct work_struct *work)
static void __atomisp_css_recover(struct atomisp_device *isp, bool isp_timeout) static void __atomisp_css_recover(struct atomisp_device *isp, bool isp_timeout)
{ {
struct pci_dev *pdev = to_pci_dev(isp->dev);
enum ia_css_pipe_id css_pipe_id; enum ia_css_pipe_id css_pipe_id;
bool stream_restart[MAX_STREAM_NUM] = {0}; bool stream_restart[MAX_STREAM_NUM] = {0};
bool depth_mode = false; bool depth_mode = false;
...@@ -1372,8 +1376,8 @@ static void __atomisp_css_recover(struct atomisp_device *isp, bool isp_timeout) ...@@ -1372,8 +1376,8 @@ static void __atomisp_css_recover(struct atomisp_device *isp, bool isp_timeout)
clear_isp_irq(hrt_isp_css_irq_sp); clear_isp_irq(hrt_isp_css_irq_sp);
/* Set the SRSE to 3 before resetting */ /* Set the SRSE to 3 before resetting */
pci_write_config_dword(isp->pdev, PCI_I_CONTROL, isp->saved_regs.i_control | pci_write_config_dword(pdev, PCI_I_CONTROL,
MRFLD_PCI_I_CONTROL_SRSE_RESET_MASK); isp->saved_regs.i_control | MRFLD_PCI_I_CONTROL_SRSE_RESET_MASK);
/* reset ISP and restore its state */ /* reset ISP and restore its state */
isp->isp_timeout = true; isp->isp_timeout = true;
...@@ -6158,6 +6162,7 @@ int atomisp_set_shading_table(struct atomisp_sub_device *asd, ...@@ -6158,6 +6162,7 @@ int atomisp_set_shading_table(struct atomisp_sub_device *asd,
/*Turn off ISP dphy */ /*Turn off ISP dphy */
int atomisp_ospm_dphy_down(struct atomisp_device *isp) int atomisp_ospm_dphy_down(struct atomisp_device *isp)
{ {
struct pci_dev *pdev = to_pci_dev(isp->dev);
unsigned long flags; unsigned long flags;
u32 reg; u32 reg;
...@@ -6179,9 +6184,9 @@ int atomisp_ospm_dphy_down(struct atomisp_device *isp) ...@@ -6179,9 +6184,9 @@ int atomisp_ospm_dphy_down(struct atomisp_device *isp)
* MRFLD HW design need all CSI ports are disabled before * MRFLD HW design need all CSI ports are disabled before
* powering down the IUNIT. * powering down the IUNIT.
*/ */
pci_read_config_dword(isp->pdev, MRFLD_PCI_CSI_CONTROL, &reg); pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, &reg);
reg |= MRFLD_ALL_CSI_PORTS_OFF_MASK; reg |= MRFLD_ALL_CSI_PORTS_OFF_MASK;
pci_write_config_dword(isp->pdev, MRFLD_PCI_CSI_CONTROL, reg); pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, reg);
return 0; return 0;
} }
......
drivers/staging/media/atomisp/pci/atomisp_cmd.h
View file @ d15be546
...@@ -68,8 +68,8 @@ bool atomisp_buffers_queued_pipe(struct atomisp_video_pipe *pipe); ...@@ -68,8 +68,8 @@ bool atomisp_buffers_queued_pipe(struct atomisp_video_pipe *pipe);
/* /*
* Interrupt functions * Interrupt functions
*/ */
void atomisp_msi_irq_init(struct atomisp_device *isp, struct pci_dev *dev); void atomisp_msi_irq_init(struct atomisp_device *isp);
void atomisp_msi_irq_uninit(struct atomisp_device *isp, struct pci_dev *dev); void atomisp_msi_irq_uninit(struct atomisp_device *isp);
void atomisp_wdt_work(struct work_struct *work); void atomisp_wdt_work(struct work_struct *work);
void atomisp_wdt(struct timer_list *t); void atomisp_wdt(struct timer_list *t);
void atomisp_setup_flash(struct atomisp_sub_device *asd); void atomisp_setup_flash(struct atomisp_sub_device *asd);
......
drivers/staging/media/atomisp/pci/atomisp_compat.h
View file @ d15be546
...@@ -29,8 +29,6 @@ struct atomisp_sub_device; ...@@ -29,8 +29,6 @@ struct atomisp_sub_device;
struct video_device; struct video_device;
enum atomisp_input_stream_id; enum atomisp_input_stream_id;
extern void __iomem *atomisp_io_base;
struct atomisp_metadata_buf { struct atomisp_metadata_buf {
struct ia_css_metadata *metadata; struct ia_css_metadata *metadata;
void *md_vptr; void *md_vptr;
......
drivers/staging/media/atomisp/pci/atomisp_compat_css20.c
View file @ d15be546
...@@ -33,13 +33,12 @@ ...@@ -33,13 +33,12 @@
#include "atomisp_ioctl.h" #include "atomisp_ioctl.h"
#include "atomisp_acc.h" #include "atomisp_acc.h"
#include <asm/intel-mid.h>
#include "ia_css_debug.h" #include "ia_css_debug.h"
#include "ia_css_isp_param.h" #include "ia_css_isp_param.h"
#include "sh_css_hrt.h" #include "sh_css_hrt.h"
#include "ia_css_isys.h" #include "ia_css_isys.h"
#include <linux/io.h>
#include <linux/pm_runtime.h> #include <linux/pm_runtime.h>
/* Assume max number of ACC stages */ /* Assume max number of ACC stages */
...@@ -69,92 +68,94 @@ struct bayer_ds_factor { ...@@ -69,92 +68,94 @@ struct bayer_ds_factor {
static void atomisp_css2_hw_store_8(hrt_address addr, uint8_t data) static void atomisp_css2_hw_store_8(hrt_address addr, uint8_t data)
{ {
s8 __iomem *io_virt_addr = atomisp_io_base + (addr & 0x003FFFFF); struct atomisp_device *isp = dev_get_drvdata(atomisp_dev);
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&mmio_lock, flags); spin_lock_irqsave(&mmio_lock, flags);
*io_virt_addr = data; writeb(data, isp->base + (addr & 0x003FFFFF));
spin_unlock_irqrestore(&mmio_lock, flags); spin_unlock_irqrestore(&mmio_lock, flags);
} }
static void atomisp_css2_hw_store_16(hrt_address addr, uint16_t data) static void atomisp_css2_hw_store_16(hrt_address addr, uint16_t data)
{ {
s16 __iomem *io_virt_addr = atomisp_io_base + (addr & 0x003FFFFF); struct atomisp_device *isp = dev_get_drvdata(atomisp_dev);
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&mmio_lock, flags); spin_lock_irqsave(&mmio_lock, flags);
*io_virt_addr = data; writew(data, isp->base + (addr & 0x003FFFFF));
spin_unlock_irqrestore(&mmio_lock, flags); spin_unlock_irqrestore(&mmio_lock, flags);
} }
void atomisp_css2_hw_store_32(hrt_address addr, uint32_t data) void atomisp_css2_hw_store_32(hrt_address addr, uint32_t data)
{ {
s32 __iomem *io_virt_addr = atomisp_io_base + (addr & 0x003FFFFF); struct atomisp_device *isp = dev_get_drvdata(atomisp_dev);
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&mmio_lock, flags); spin_lock_irqsave(&mmio_lock, flags);
*io_virt_addr = data; writel(data, isp->base + (addr & 0x003FFFFF));
spin_unlock_irqrestore(&mmio_lock, flags); spin_unlock_irqrestore(&mmio_lock, flags);
} }
static uint8_t atomisp_css2_hw_load_8(hrt_address addr) static uint8_t atomisp_css2_hw_load_8(hrt_address addr)
{ {
s8 __iomem *io_virt_addr = atomisp_io_base + (addr & 0x003FFFFF); struct atomisp_device *isp = dev_get_drvdata(atomisp_dev);
unsigned long flags; unsigned long flags;
u8 ret; u8 ret;
spin_lock_irqsave(&mmio_lock, flags); spin_lock_irqsave(&mmio_lock, flags);
ret = *io_virt_addr; ret = readb(isp->base + (addr & 0x003FFFFF));
spin_unlock_irqrestore(&mmio_lock, flags); spin_unlock_irqrestore(&mmio_lock, flags);
return ret; return ret;
} }
static uint16_t atomisp_css2_hw_load_16(hrt_address addr) static uint16_t atomisp_css2_hw_load_16(hrt_address addr)
{ {
s16 __iomem *io_virt_addr = atomisp_io_base + (addr & 0x003FFFFF); struct atomisp_device *isp = dev_get_drvdata(atomisp_dev);
unsigned long flags; unsigned long flags;
u16 ret; u16 ret;
spin_lock_irqsave(&mmio_lock, flags); spin_lock_irqsave(&mmio_lock, flags);
ret = *io_virt_addr; ret = readw(isp->base + (addr & 0x003FFFFF));
spin_unlock_irqrestore(&mmio_lock, flags); spin_unlock_irqrestore(&mmio_lock, flags);
return ret; return ret;
} }
static uint32_t atomisp_css2_hw_load_32(hrt_address addr) static uint32_t atomisp_css2_hw_load_32(hrt_address addr)
{ {
s32 __iomem *io_virt_addr = atomisp_io_base + (addr & 0x003FFFFF); struct atomisp_device *isp = dev_get_drvdata(atomisp_dev);
unsigned long flags; unsigned long flags;
u32 ret; u32 ret;
spin_lock_irqsave(&mmio_lock, flags); spin_lock_irqsave(&mmio_lock, flags);
ret = *io_virt_addr; ret = readl(isp->base + (addr & 0x003FFFFF));
spin_unlock_irqrestore(&mmio_lock, flags); spin_unlock_irqrestore(&mmio_lock, flags);
return ret; return ret;
} }
static void atomisp_css2_hw_store(hrt_address addr, static void atomisp_css2_hw_store(hrt_address addr, const void *from, uint32_t n)
const void *from, uint32_t n)
{ {
s8 __iomem *io_virt_addr = atomisp_io_base + (addr & 0x003FFFFF); struct atomisp_device *isp = dev_get_drvdata(atomisp_dev);
unsigned long flags; unsigned long flags;
unsigned int i; unsigned int i;
addr &= 0x003FFFFF;
spin_lock_irqsave(&mmio_lock, flags); spin_lock_irqsave(&mmio_lock, flags);
for (i = 0; i < n; i++, io_virt_addr++, from++) for (i = 0; i < n; i++, from++)
*io_virt_addr = *(s8 *)from; writeb(*(s8 *)from, isp->base + addr + i);
spin_unlock_irqrestore(&mmio_lock, flags); spin_unlock_irqrestore(&mmio_lock, flags);
} }
static void atomisp_css2_hw_load(hrt_address addr, void *to, uint32_t n) static void atomisp_css2_hw_load(hrt_address addr, void *to, uint32_t n)
{ {
s8 __iomem *io_virt_addr = atomisp_io_base + (addr & 0x003FFFFF); struct atomisp_device *isp = dev_get_drvdata(atomisp_dev);
unsigned long flags; unsigned long flags;
unsigned int i; unsigned int i;
addr &= 0x003FFFFF;
spin_lock_irqsave(&mmio_lock, flags); spin_lock_irqsave(&mmio_lock, flags);
for (i = 0; i < n; i++, to++, io_virt_addr++) for (i = 0; i < n; i++, to++)
*(s8 *)to = *io_virt_addr; *(s8 *)to = readb(isp->base + addr + i);
spin_unlock_irqrestore(&mmio_lock, flags); spin_unlock_irqrestore(&mmio_lock, flags);
} }
...@@ -181,10 +182,10 @@ void atomisp_load_uint32(hrt_address addr, uint32_t *data) ...@@ -181,10 +182,10 @@ void atomisp_load_uint32(hrt_address addr, uint32_t *data)
*data = atomisp_css2_hw_load_32(addr); *data = atomisp_css2_hw_load_32(addr);
} }
static int hmm_get_mmu_base_addr(unsigned int *mmu_base_addr) static int hmm_get_mmu_base_addr(struct device *dev, unsigned int *mmu_base_addr)
{ {
if (!sh_mmu_mrfld.get_pd_base) { if (!sh_mmu_mrfld.get_pd_base) {
dev_err(atomisp_dev, "get mmu base address failed.\n"); dev_err(dev, "get mmu base address failed.\n");
return -EINVAL; return -EINVAL;
} }
...@@ -839,7 +840,7 @@ int atomisp_css_init(struct atomisp_device *isp) ...@@ -839,7 +840,7 @@ int atomisp_css_init(struct atomisp_device *isp)
int ret; int ret;
int err; int err;
ret = hmm_get_mmu_base_addr(&mmu_base_addr); ret = hmm_get_mmu_base_addr(isp->dev, &mmu_base_addr);
if (ret) if (ret)
return ret; return ret;
...@@ -941,7 +942,7 @@ int atomisp_css_resume(struct atomisp_device *isp) ...@@ -941,7 +942,7 @@ int atomisp_css_resume(struct atomisp_device *isp)
unsigned int mmu_base_addr; unsigned int mmu_base_addr;
int ret; int ret;
ret = hmm_get_mmu_base_addr(&mmu_base_addr); ret = hmm_get_mmu_base_addr(isp->dev, &mmu_base_addr);
if (ret) { if (ret) {
dev_err(isp->dev, "get base address error.\n"); dev_err(isp->dev, "get base address error.\n");
return -EINVAL; return -EINVAL;
...@@ -1966,8 +1967,7 @@ void atomisp_css_input_set_mode(struct atomisp_sub_device *asd, ...@@ -1966,8 +1967,7 @@ void atomisp_css_input_set_mode(struct atomisp_sub_device *asd,
true, true,
0x13000, 0x13000,
&size_mem_words) != 0) { &size_mem_words) != 0) {
if (intel_mid_identify_cpu() == if (IS_MRFD)
INTEL_MID_CPU_CHIP_TANGIER)
size_mem_words = CSS_MIPI_FRAME_BUFFER_SIZE_2; size_mem_words = CSS_MIPI_FRAME_BUFFER_SIZE_2;
else else
size_mem_words = CSS_MIPI_FRAME_BUFFER_SIZE_1; size_mem_words = CSS_MIPI_FRAME_BUFFER_SIZE_1;
...@@ -2414,13 +2414,13 @@ static void __configure_preview_pp_input(struct atomisp_sub_device *asd, ...@@ -2414,13 +2414,13 @@ static void __configure_preview_pp_input(struct atomisp_sub_device *asd,
struct ia_css_resolution *effective_res = struct ia_css_resolution *effective_res =
&stream_config->input_config.effective_res; &stream_config->input_config.effective_res;
const struct bayer_ds_factor bds_fct[] = {{2, 1}, {3, 2}, {5, 4} }; static const struct bayer_ds_factor bds_fct[] = {{2, 1}, {3, 2}, {5, 4} };
/* /*
* BZ201033: YUV decimation factor of 4 causes couple of rightmost * BZ201033: YUV decimation factor of 4 causes couple of rightmost
* columns to be shaded. Remove this factor to work around the CSS bug. * columns to be shaded. Remove this factor to work around the CSS bug.
* const unsigned int yuv_dec_fct[] = {4, 2}; * const unsigned int yuv_dec_fct[] = {4, 2};
*/ */
const unsigned int yuv_dec_fct[] = { 2 }; static const unsigned int yuv_dec_fct[] = { 2 };
unsigned int i; unsigned int i;
if (width == 0 && height == 0) if (width == 0 && height == 0)
...@@ -2540,7 +2540,7 @@ static void __configure_video_pp_input(struct atomisp_sub_device *asd, ...@@ -2540,7 +2540,7 @@ static void __configure_video_pp_input(struct atomisp_sub_device *asd,
struct ia_css_resolution *effective_res = struct ia_css_resolution *effective_res =
&stream_config->input_config.effective_res; &stream_config->input_config.effective_res;
const struct bayer_ds_factor bds_factors[] = { static const struct bayer_ds_factor bds_factors[] = {
{8, 1}, {6, 1}, {4, 1}, {3, 1}, {2, 1}, {3, 2} {8, 1}, {6, 1}, {4, 1}, {3, 1}, {2, 1}, {3, 2}
}; };
unsigned int i; unsigned int i;
...@@ -4337,7 +4337,7 @@ static const char * const fw_acc_type_name[] = { ...@@ -4337,7 +4337,7 @@ static const char * const fw_acc_type_name[] = {
[IA_CSS_ACC_STANDALONE] = "Stand-alone acceleration", [IA_CSS_ACC_STANDALONE] = "Stand-alone acceleration",
}; };
int atomisp_css_dump_blob_infor(void) int atomisp_css_dump_blob_infor(struct atomisp_device *isp)
{ {
struct ia_css_blob_descr *bd = sh_css_blob_info; struct ia_css_blob_descr *bd = sh_css_blob_info;
unsigned int i, nm = sh_css_num_binaries; unsigned int i, nm = sh_css_num_binaries;
...@@ -4354,8 +4354,7 @@ int atomisp_css_dump_blob_infor(void) ...@@ -4354,8 +4354,7 @@ int atomisp_css_dump_blob_infor(void)
for (i = 0; i < sh_css_num_binaries - NUM_OF_SPS; i++) { for (i = 0; i < sh_css_num_binaries - NUM_OF_SPS; i++) {
switch (bd[i].header.type) { switch (bd[i].header.type) {
case ia_css_isp_firmware: case ia_css_isp_firmware:
dev_dbg(atomisp_dev, dev_dbg(isp->dev, "Num%2d type %s (%s), binary id is %2d, name is %s\n",
"Num%2d type %s (%s), binary id is %2d, name is %s\n",
i + NUM_OF_SPS, i + NUM_OF_SPS,
fw_type_name[bd[i].header.type], fw_type_name[bd[i].header.type],
fw_acc_type_name[bd[i].header.info.isp.type], fw_acc_type_name[bd[i].header.info.isp.type],
...@@ -4363,8 +4362,7 @@ int atomisp_css_dump_blob_infor(void) ...@@ -4363,8 +4362,7 @@ int atomisp_css_dump_blob_infor(void)
bd[i].name); bd[i].name);
break; break;
default: default:
dev_dbg(atomisp_dev, dev_dbg(isp->dev, "Num%2d type %s, name is %s\n",
"Num%2d type %s, name is %s\n",
i + NUM_OF_SPS, fw_type_name[bd[i].header.type], i + NUM_OF_SPS, fw_type_name[bd[i].header.type],
bd[i].name); bd[i].name);
} }
......
drivers/staging/media/atomisp/pci/atomisp_compat_css20.h
View file @ d15be546
...@@ -153,7 +153,7 @@ int atomisp_css_debug_dump_isp_binary(void); ...@@ -153,7 +153,7 @@ int atomisp_css_debug_dump_isp_binary(void);
int atomisp_css_dump_sp_raw_copy_linecount(bool reduced); int atomisp_css_dump_sp_raw_copy_linecount(bool reduced);
int atomisp_css_dump_blob_infor(void); int atomisp_css_dump_blob_infor(struct atomisp_device *isp);
void atomisp_css_set_isp_config_id(struct atomisp_sub_device *asd, void atomisp_css_set_isp_config_id(struct atomisp_sub_device *asd,
uint32_t isp_config_id); uint32_t isp_config_id);
......
drivers/staging/media/atomisp/pci/atomisp_drvfs.c
View file @ d15be546
...@@ -62,9 +62,9 @@ static inline int iunit_dump_dbgopt(struct atomisp_device *isp, ...@@ -62,9 +62,9 @@ static inline int iunit_dump_dbgopt(struct atomisp_device *isp,
if (opt & OPTION_VALID) { if (opt & OPTION_VALID) {
if (opt & OPTION_BIN_LIST) { if (opt & OPTION_BIN_LIST) {
ret = atomisp_css_dump_blob_infor(); ret = atomisp_css_dump_blob_infor(isp);
if (ret) { if (ret) {
dev_err(atomisp_dev, "%s dump blob infor err[ret:%d]\n", dev_err(isp->dev, "%s dump blob infor err[ret:%d]\n",
__func__, ret); __func__, ret);
goto opt_err; goto opt_err;
} }
...@@ -76,7 +76,7 @@ static inline int iunit_dump_dbgopt(struct atomisp_device *isp, ...@@ -76,7 +76,7 @@ static inline int iunit_dump_dbgopt(struct atomisp_device *isp,
atomisp_css_debug_dump_isp_binary(); atomisp_css_debug_dump_isp_binary();
} else { } else {
ret = -EPERM; ret = -EPERM;
dev_err(atomisp_dev, "%s dump running bin err[ret:%d]\n", dev_err(isp->dev, "%s dump running bin err[ret:%d]\n",
__func__, ret); __func__, ret);
goto opt_err; goto opt_err;
} }
...@@ -86,8 +86,7 @@ static inline int iunit_dump_dbgopt(struct atomisp_device *isp, ...@@ -86,8 +86,7 @@ static inline int iunit_dump_dbgopt(struct atomisp_device *isp,
hmm_show_mem_stat(__func__, __LINE__); hmm_show_mem_stat(__func__, __LINE__);
} else { } else {
ret = -EINVAL; ret = -EINVAL;
dev_err(atomisp_dev, "%s dump nothing[ret=%d]\n", __func__, dev_err(isp->dev, "%s dump nothing[ret=%d]\n", __func__, ret);
ret);
} }
opt_err: opt_err:
...@@ -185,8 +184,9 @@ static void iunit_drvfs_remove_files(struct device_driver *drv) ...@@ -185,8 +184,9 @@ static void iunit_drvfs_remove_files(struct device_driver *drv)
driver_remove_file(drv, &iunit_drvfs_attrs[i]); driver_remove_file(drv, &iunit_drvfs_attrs[i]);
} }
int atomisp_drvfs_init(struct device_driver *drv, struct atomisp_device *isp) int atomisp_drvfs_init(struct atomisp_device *isp)
{ {
struct device_driver *drv = isp->dev->driver;
int ret; int ret;
iunit_debug.isp = isp; iunit_debug.isp = isp;
...@@ -194,7 +194,7 @@ int atomisp_drvfs_init(struct device_driver *drv, struct atomisp_device *isp) ...@@ -194,7 +194,7 @@ int atomisp_drvfs_init(struct device_driver *drv, struct atomisp_device *isp)
ret = iunit_drvfs_create_files(iunit_debug.drv); ret = iunit_drvfs_create_files(iunit_debug.drv);
if (ret) { if (ret) {
dev_err(atomisp_dev, "drvfs_create_files error: %d\n", ret); dev_err(isp->dev, "drvfs_create_files error: %d\n", ret);
iunit_drvfs_remove_files(iunit_debug.drv); iunit_drvfs_remove_files(iunit_debug.drv);
} }
......
drivers/staging/media/atomisp/pci/atomisp_drvfs.h
View file @ d15be546
...@@ -19,7 +19,7 @@ ...@@ -19,7 +19,7 @@
#ifndef __ATOMISP_DRVFS_H__ #ifndef __ATOMISP_DRVFS_H__
#define __ATOMISP_DRVFS_H__ #define __ATOMISP_DRVFS_H__
int atomisp_drvfs_init(struct device_driver *drv, struct atomisp_device *isp); int atomisp_drvfs_init(struct atomisp_device *isp);
void atomisp_drvfs_exit(void); void atomisp_drvfs_exit(void);
#endif /* __ATOMISP_DRVFS_H__ */ #endif /* __ATOMISP_DRVFS_H__ */
drivers/staging/media/atomisp/pci/atomisp_internal.h
View file @ d15be546
...@@ -216,12 +216,12 @@ struct atomisp_sw_contex { ...@@ -216,12 +216,12 @@ struct atomisp_sw_contex {
* ci device struct * ci device struct
*/ */
struct atomisp_device { struct atomisp_device {
struct pci_dev *pdev;
struct device *dev; struct device *dev;
struct v4l2_device v4l2_dev; struct v4l2_device v4l2_dev;
struct media_device media_dev; struct media_device media_dev;
struct atomisp_platform_data *pdata; struct atomisp_platform_data *pdata;
void *mmu_l1_base; void *mmu_l1_base;
void __iomem *base;
const struct firmware *firmware; const struct firmware *firmware;
struct pm_qos_request pm_qos; struct pm_qos_request pm_qos;
......
drivers/staging/media/atomisp/pci/atomisp_ioctl.c
View file @ d15be546
...@@ -549,8 +549,7 @@ static int atomisp_querycap(struct file *file, void *fh, ...@@ -549,8 +549,7 @@ static int atomisp_querycap(struct file *file, void *fh,
strscpy(cap->driver, DRIVER, sizeof(cap->driver)); strscpy(cap->driver, DRIVER, sizeof(cap->driver));
strscpy(cap->card, CARD, sizeof(cap->card)); strscpy(cap->card, CARD, sizeof(cap->card));
snprintf(cap->bus_info, sizeof(cap->bus_info), "PCI:%s", snprintf(cap->bus_info, sizeof(cap->bus_info), "PCI:%s", dev_name(isp->dev));
pci_name(isp->pdev));
return 0; return 0;
} }
...@@ -1635,6 +1634,7 @@ static int atomisp_streamon(struct file *file, void *fh, ...@@ -1635,6 +1634,7 @@ static int atomisp_streamon(struct file *file, void *fh,
struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev);
struct atomisp_sub_device *asd = pipe->asd; struct atomisp_sub_device *asd = pipe->asd;
struct atomisp_device *isp = video_get_drvdata(vdev); struct atomisp_device *isp = video_get_drvdata(vdev);
struct pci_dev *pdev = to_pci_dev(isp->dev);
enum ia_css_pipe_id css_pipe_id; enum ia_css_pipe_id css_pipe_id;
unsigned int sensor_start_stream; unsigned int sensor_start_stream;
unsigned int wdt_duration = ATOMISP_ISP_TIMEOUT_DURATION; unsigned int wdt_duration = ATOMISP_ISP_TIMEOUT_DURATION;
...@@ -1844,9 +1844,8 @@ static int atomisp_streamon(struct file *file, void *fh, ...@@ -1844,9 +1844,8 @@ static int atomisp_streamon(struct file *file, void *fh,
/* Enable the CSI interface on ANN B0/K0 */ /* Enable the CSI interface on ANN B0/K0 */
if (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 << if (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 <<
ATOMISP_HW_REVISION_SHIFT) | ATOMISP_HW_STEPPING_B0)) { ATOMISP_HW_REVISION_SHIFT) | ATOMISP_HW_STEPPING_B0)) {
pci_write_config_word(isp->pdev, MRFLD_PCI_CSI_CONTROL, pci_write_config_word(pdev, MRFLD_PCI_CSI_CONTROL,
isp->saved_regs.csi_control | isp->saved_regs.csi_control | MRFLD_PCI_CSI_CONTROL_CSI_READY);
MRFLD_PCI_CSI_CONTROL_CSI_READY);
} }
/* stream on the sensor */ /* stream on the sensor */
...@@ -1891,6 +1890,7 @@ int __atomisp_streamoff(struct file *file, void *fh, enum v4l2_buf_type type) ...@@ -1891,6 +1890,7 @@ int __atomisp_streamoff(struct file *file, void *fh, enum v4l2_buf_type type)
{ {
struct video_device *vdev = video_devdata(file); struct video_device *vdev = video_devdata(file);
struct atomisp_device *isp = video_get_drvdata(vdev); struct atomisp_device *isp = video_get_drvdata(vdev);
struct pci_dev *pdev = to_pci_dev(isp->dev);
struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev);
struct atomisp_sub_device *asd = pipe->asd; struct atomisp_sub_device *asd = pipe->asd;
struct atomisp_video_pipe *capture_pipe = NULL; struct atomisp_video_pipe *capture_pipe = NULL;
...@@ -2076,9 +2076,8 @@ int __atomisp_streamoff(struct file *file, void *fh, enum v4l2_buf_type type) ...@@ -2076,9 +2076,8 @@ int __atomisp_streamoff(struct file *file, void *fh, enum v4l2_buf_type type)
/* Disable the CSI interface on ANN B0/K0 */ /* Disable the CSI interface on ANN B0/K0 */
if (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 << if (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 <<
ATOMISP_HW_REVISION_SHIFT) | ATOMISP_HW_STEPPING_B0)) { ATOMISP_HW_REVISION_SHIFT) | ATOMISP_HW_STEPPING_B0)) {
pci_write_config_word(isp->pdev, MRFLD_PCI_CSI_CONTROL, pci_write_config_word(pdev, MRFLD_PCI_CSI_CONTROL,
isp->saved_regs.csi_control & isp->saved_regs.csi_control & ~MRFLD_PCI_CSI_CONTROL_CSI_READY);
~MRFLD_PCI_CSI_CONTROL_CSI_READY);
} }
if (atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, false)) if (atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, false))
...@@ -2111,8 +2110,8 @@ int __atomisp_streamoff(struct file *file, void *fh, enum v4l2_buf_type type) ...@@ -2111,8 +2110,8 @@ int __atomisp_streamoff(struct file *file, void *fh, enum v4l2_buf_type type)
} }
/* disable PUNIT/ISP acknowlede/handshake - SRSE=3 */ /* disable PUNIT/ISP acknowlede/handshake - SRSE=3 */
pci_write_config_dword(isp->pdev, PCI_I_CONTROL, isp->saved_regs.i_control | pci_write_config_dword(pdev, PCI_I_CONTROL,
MRFLD_PCI_I_CONTROL_SRSE_RESET_MASK); isp->saved_regs.i_control | MRFLD_PCI_I_CONTROL_SRSE_RESET_MASK);
dev_err(isp->dev, "atomisp_reset"); dev_err(isp->dev, "atomisp_reset");
atomisp_reset(isp); atomisp_reset(isp);
for (i = 0; i < isp->num_of_streams; i++) { for (i = 0; i < isp->num_of_streams; i++) {
......
drivers/staging/media/atomisp/pci/base/refcount/src/refcount.c
View file @ d15be546
...@@ -48,7 +48,7 @@ static struct ia_css_refcount_entry *refcount_find_entry(ia_css_ptr ptr, ...@@ -48,7 +48,7 @@ static struct ia_css_refcount_entry *refcount_find_entry(ia_css_ptr ptr,
return NULL; return NULL;
if (!myrefcount.items) { if (!myrefcount.items) {
ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR,
"refcount_find_entry(): Ref count not initialized!\n"); "%s(): Ref count not initialized!\n", __func__);
return NULL; return NULL;
} }
...@@ -73,12 +73,12 @@ int ia_css_refcount_init(uint32_t size) ...@@ -73,12 +73,12 @@ int ia_css_refcount_init(uint32_t size)
if (size == 0) { if (size == 0) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_refcount_init(): Size of 0 for Ref count init!\n"); "%s(): Size of 0 for Ref count init!\n", __func__);
return -EINVAL; return -EINVAL;
} }
if (myrefcount.items) { if (myrefcount.items) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_refcount_init(): Ref count is already initialized\n"); "%s(): Ref count is already initialized\n", __func__);
return -EINVAL; return -EINVAL;
} }
myrefcount.items = myrefcount.items =
...@@ -99,7 +99,7 @@ void ia_css_refcount_uninit(void) ...@@ -99,7 +99,7 @@ void ia_css_refcount_uninit(void)
u32 i; u32 i;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_refcount_uninit() entry\n"); "%s() entry\n", __func__);
for (i = 0; i < myrefcount.size; i++) { for (i = 0; i < myrefcount.size; i++) {
/* driver verifier tool has issues with &arr[i] /* driver verifier tool has issues with &arr[i]
and prefers arr + i; as these are actually equivalent and prefers arr + i; as these are actually equivalent
...@@ -120,7 +120,7 @@ void ia_css_refcount_uninit(void) ...@@ -120,7 +120,7 @@ void ia_css_refcount_uninit(void)
myrefcount.items = NULL; myrefcount.items = NULL;
myrefcount.size = 0; myrefcount.size = 0;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_refcount_uninit() leave\n"); "%s() leave\n", __func__);
} }
ia_css_ptr ia_css_refcount_increment(s32 id, ia_css_ptr ptr) ia_css_ptr ia_css_refcount_increment(s32 id, ia_css_ptr ptr)
...@@ -133,7 +133,7 @@ ia_css_ptr ia_css_refcount_increment(s32 id, ia_css_ptr ptr) ...@@ -133,7 +133,7 @@ ia_css_ptr ia_css_refcount_increment(s32 id, ia_css_ptr ptr)
entry = refcount_find_entry(ptr, false); entry = refcount_find_entry(ptr, false);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_refcount_increment(%x) 0x%x\n", id, ptr); "%s(%x) 0x%x\n", __func__, id, ptr);
if (!entry) { if (!entry) {
entry = refcount_find_entry(ptr, true); entry = refcount_find_entry(ptr, true);
...@@ -145,7 +145,7 @@ ia_css_ptr ia_css_refcount_increment(s32 id, ia_css_ptr ptr) ...@@ -145,7 +145,7 @@ ia_css_ptr ia_css_refcount_increment(s32 id, ia_css_ptr ptr)
if (entry->id != id) { if (entry->id != id) {
ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR,
"ia_css_refcount_increment(): Ref count IDS do not match!\n"); "%s(): Ref count IDS do not match!\n", __func__);
return mmgr_NULL; return mmgr_NULL;
} }
...@@ -165,7 +165,7 @@ bool ia_css_refcount_decrement(s32 id, ia_css_ptr ptr) ...@@ -165,7 +165,7 @@ bool ia_css_refcount_decrement(s32 id, ia_css_ptr ptr)
struct ia_css_refcount_entry *entry; struct ia_css_refcount_entry *entry;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_refcount_decrement(%x) 0x%x\n", id, ptr); "%s(%x) 0x%x\n", __func__, id, ptr);
if (ptr == mmgr_NULL) if (ptr == mmgr_NULL)
return false; return false;
...@@ -175,7 +175,7 @@ bool ia_css_refcount_decrement(s32 id, ia_css_ptr ptr) ...@@ -175,7 +175,7 @@ bool ia_css_refcount_decrement(s32 id, ia_css_ptr ptr)
if (entry) { if (entry) {
if (entry->id != id) { if (entry->id != id) {
ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR,
"ia_css_refcount_decrement(): Ref count IDS do not match!\n"); "%s(): Ref count IDS do not match!\n", __func__);
return false; return false;
} }
if (entry->count > 0) { if (entry->count > 0) {
...@@ -225,8 +225,8 @@ void ia_css_refcount_clear(s32 id, clear_func clear_func_ptr) ...@@ -225,8 +225,8 @@ void ia_css_refcount_clear(s32 id, clear_func clear_func_ptr)
u32 count = 0; u32 count = 0;
assert(clear_func_ptr); assert(clear_func_ptr);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_refcount_clear(%x)\n", ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s(%x)\n",
id); __func__, id);
for (i = 0; i < myrefcount.size; i++) { for (i = 0; i < myrefcount.size; i++) {
/* driver verifier tool has issues with &arr[i] /* driver verifier tool has issues with &arr[i]
...@@ -236,14 +236,14 @@ void ia_css_refcount_clear(s32 id, clear_func clear_func_ptr) ...@@ -236,14 +236,14 @@ void ia_css_refcount_clear(s32 id, clear_func clear_func_ptr)
entry = myrefcount.items + i; entry = myrefcount.items + i;
if ((entry->data != mmgr_NULL) && (entry->id == id)) { if ((entry->data != mmgr_NULL) && (entry->id == id)) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_refcount_clear: %x: 0x%x\n", "%s: %x: 0x%x\n", __func__,
id, entry->data); id, entry->data);
if (clear_func_ptr) { if (clear_func_ptr) {
/* clear using provided function */ /* clear using provided function */
clear_func_ptr(entry->data); clear_func_ptr(entry->data);
} else { } else {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_refcount_clear: using hmm_free: no clear_func\n"); "%s: using hmm_free: no clear_func\n", __func__);
hmm_free(entry->data); hmm_free(entry->data);
} }
...@@ -260,7 +260,7 @@ void ia_css_refcount_clear(s32 id, clear_func clear_func_ptr) ...@@ -260,7 +260,7 @@ void ia_css_refcount_clear(s32 id, clear_func clear_func_ptr)
} }
} }
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_refcount_clear(%x): cleared %d\n", id, "%s(%x): cleared %d\n", __func__, id,
count); count);
} }
......
drivers/staging/media/atomisp/pci/hive_types.h
View file @ d15be546
...@@ -52,32 +52,14 @@ typedef unsigned short hive_uint16; ...@@ -52,32 +52,14 @@ typedef unsigned short hive_uint16;
typedef unsigned int hive_uint32; typedef unsigned int hive_uint32;
typedef unsigned long long hive_uint64; typedef unsigned long long hive_uint64;
/* by default assume 32 bit master port (both data and address) */ #define HRT_DATA_WIDTH 32
#ifndef HRT_DATA_WIDTH #define HRT_ADDRESS_WIDTH 64
#define HRT_DATA_WIDTH 32
#endif
#ifndef HRT_ADDRESS_WIDTH
#define HRT_ADDRESS_WIDTH 32
#endif
#define HRT_DATA_BYTES (HRT_DATA_WIDTH / 8) #define HRT_DATA_BYTES (HRT_DATA_WIDTH / 8)
#define HRT_ADDRESS_BYTES (HRT_ADDRESS_WIDTH / 8) #define HRT_ADDRESS_BYTES (HRT_ADDRESS_WIDTH / 8)
#define SIZEOF_HRT_REG (HRT_DATA_WIDTH >> 3)
#if HRT_DATA_WIDTH == 64
typedef hive_uint64 hrt_data;
#elif HRT_DATA_WIDTH == 32
typedef hive_uint32 hrt_data; typedef hive_uint32 hrt_data;
#else
#error data width not supported
#endif
#if HRT_ADDRESS_WIDTH == 64
typedef hive_uint64 hrt_address; typedef hive_uint64 hrt_address;
#elif HRT_ADDRESS_WIDTH == 32
typedef hive_uint32 hrt_address;
#else
#error adddres width not supported
#endif
/* use 64 bit addresses in simulation, where possible */ /* use 64 bit addresses in simulation, where possible */
typedef hive_uint64 hive_sim_address; typedef hive_uint64 hive_sim_address;
......
drivers/staging/media/atomisp/pci/hmm/hmm.c
View file @ d15be546
...@@ -735,11 +735,11 @@ ia_css_ptr hmm_host_vaddr_to_hrt_vaddr(const void *ptr) ...@@ -735,11 +735,11 @@ ia_css_ptr hmm_host_vaddr_to_hrt_vaddr(const void *ptr)
void hmm_show_mem_stat(const char *func, const int line) void hmm_show_mem_stat(const char *func, const int line)
{ {
trace_printk("tol_cnt=%d usr_size=%d res_size=%d res_cnt=%d sys_size=%d dyc_thr=%d dyc_size=%d.\n", pr_info("tol_cnt=%d usr_size=%d res_size=%d res_cnt=%d sys_size=%d dyc_thr=%d dyc_size=%d.\n",
hmm_mem_stat.tol_cnt, hmm_mem_stat.tol_cnt,
hmm_mem_stat.usr_size, hmm_mem_stat.res_size, hmm_mem_stat.usr_size, hmm_mem_stat.res_size,
hmm_mem_stat.res_cnt, hmm_mem_stat.sys_size, hmm_mem_stat.res_cnt, hmm_mem_stat.sys_size,
hmm_mem_stat.dyc_thr, hmm_mem_stat.dyc_size); hmm_mem_stat.dyc_thr, hmm_mem_stat.dyc_size);
} }
void hmm_init_mem_stat(int res_pgnr, int dyc_en, int dyc_pgnr) void hmm_init_mem_stat(int res_pgnr, int dyc_en, int dyc_pgnr)
......
drivers/staging/media/atomisp/pci/isp2400_system_global.h
View file @ d15be546
...@@ -13,306 +13,4 @@ ...@@ -13,306 +13,4 @@
* more details. * more details.
*/ */
#ifndef __SYSTEM_GLOBAL_H_INCLUDED__
#define __SYSTEM_GLOBAL_H_INCLUDED__
#include <hive_isp_css_defs.h>
#include <type_support.h>
/*
* The longest allowed (uninteruptible) bus transfer, does not
* take stalling into account
*/
#define HIVE_ISP_MAX_BURST_LENGTH 1024
/*
* Maximum allowed burst length in words for the ISP DMA
*/
#define ISP_DMA_MAX_BURST_LENGTH 128
/*
* Create a list of HAS and IS properties that defines the system
*
* The configuration assumes the following
* - The system is hetereogeneous; Multiple cells and devices classes
* - The cell and device instances are homogeneous, each device type
* belongs to the same class
* - Device instances supporting a subset of the class capabilities are
* allowed
*
* We could manage different device classes through the enumerated
* lists (C) or the use of classes (C++), but that is presently not
* fully supported
*
* N.B. the 3 input formatters are of 2 different classess
*/
#define USE_INPUT_SYSTEM_VERSION_2 #define USE_INPUT_SYSTEM_VERSION_2
#define HAS_MMU_VERSION_2
#define HAS_DMA_VERSION_2
#define HAS_GDC_VERSION_2
#define HAS_VAMEM_VERSION_2
#define HAS_HMEM_VERSION_1
#define HAS_BAMEM_VERSION_2
#define HAS_IRQ_VERSION_2
#define HAS_IRQ_MAP_VERSION_2
#define HAS_INPUT_FORMATTER_VERSION_2
/* 2401: HAS_INPUT_SYSTEM_VERSION_2401 */
#define HAS_INPUT_SYSTEM_VERSION_2
#define HAS_BUFFERED_SENSOR
#define HAS_FIFO_MONITORS_VERSION_2
/* #define HAS_GP_REGS_VERSION_2 */
#define HAS_GP_DEVICE_VERSION_2
#define HAS_GPIO_VERSION_1
#define HAS_TIMED_CTRL_VERSION_1
#define HAS_RX_VERSION_2
#define DMA_DDR_TO_VAMEM_WORKAROUND
#define DMA_DDR_TO_HMEM_WORKAROUND
/*
* Semi global. "HRT" is accessible from SP, but the HRT types do not fully apply
*/
#define HRT_VADDRESS_WIDTH 32
//#define HRT_ADDRESS_WIDTH 64 /* Surprise, this is a local property*/
#define HRT_DATA_WIDTH 32
#define SIZEOF_HRT_REG (HRT_DATA_WIDTH >> 3)
#define HIVE_ISP_CTRL_DATA_BYTES (HIVE_ISP_CTRL_DATA_WIDTH / 8)
/* The main bus connecting all devices */
#define HRT_BUS_WIDTH HIVE_ISP_CTRL_DATA_WIDTH
#define HRT_BUS_BYTES HIVE_ISP_CTRL_DATA_BYTES
/* per-frame parameter handling support */
#define SH_CSS_ENABLE_PER_FRAME_PARAMS
typedef u32 hrt_bus_align_t;
/*
* Enumerate the devices, device access through the API is by ID, through the DLI by address
* The enumerator terminators are used to size the wiring arrays and as an exception value.
*/
typedef enum {
DDR0_ID = 0,
N_DDR_ID
} ddr_ID_t;
typedef enum {
ISP0_ID = 0,
N_ISP_ID
} isp_ID_t;
typedef enum {
SP0_ID = 0,
N_SP_ID
} sp_ID_t;
typedef enum {
MMU0_ID = 0,
MMU1_ID,
N_MMU_ID
} mmu_ID_t;
typedef enum {
DMA0_ID = 0,
N_DMA_ID
} dma_ID_t;
typedef enum {
GDC0_ID = 0,
GDC1_ID,
N_GDC_ID
} gdc_ID_t;
#define N_GDC_ID_CPP 2 // this extra define is needed because we want to use it also in the preprocessor, and that doesn't work with enums.
typedef enum {
VAMEM0_ID = 0,
VAMEM1_ID,
VAMEM2_ID,
N_VAMEM_ID
} vamem_ID_t;
typedef enum {
BAMEM0_ID = 0,
N_BAMEM_ID
} bamem_ID_t;
typedef enum {
HMEM0_ID = 0,
N_HMEM_ID
} hmem_ID_t;
/*
typedef enum {
IRQ0_ID = 0,
N_IRQ_ID
} irq_ID_t;
*/
typedef enum {
IRQ0_ID = 0, // GP IRQ block
IRQ1_ID, // Input formatter
IRQ2_ID, // input system
IRQ3_ID, // input selector
N_IRQ_ID
} irq_ID_t;
typedef enum {
FIFO_MONITOR0_ID = 0,
N_FIFO_MONITOR_ID
} fifo_monitor_ID_t;
/*
* Deprecated: Since all gp_reg instances are different
* and put in the address maps of other devices we cannot
* enumerate them as that assumes the instrances are the
* same.
*
* We define a single GP_DEVICE containing all gp_regs
* w.r.t. a single base address
*
typedef enum {
GP_REGS0_ID = 0,
N_GP_REGS_ID
} gp_regs_ID_t;
*/
typedef enum {
GP_DEVICE0_ID = 0,
N_GP_DEVICE_ID
} gp_device_ID_t;
typedef enum {
GP_TIMER0_ID = 0,
GP_TIMER1_ID,
GP_TIMER2_ID,
GP_TIMER3_ID,
GP_TIMER4_ID,
GP_TIMER5_ID,
GP_TIMER6_ID,
GP_TIMER7_ID,
N_GP_TIMER_ID
} gp_timer_ID_t;
typedef enum {
GPIO0_ID = 0,
N_GPIO_ID
} gpio_ID_t;
typedef enum {
TIMED_CTRL0_ID = 0,
N_TIMED_CTRL_ID
} timed_ctrl_ID_t;
typedef enum {
INPUT_FORMATTER0_ID = 0,
INPUT_FORMATTER1_ID,
INPUT_FORMATTER2_ID,
INPUT_FORMATTER3_ID,
N_INPUT_FORMATTER_ID
} input_formatter_ID_t;
/* The IF RST is outside the IF */
#define INPUT_FORMATTER0_SRST_OFFSET 0x0824
#define INPUT_FORMATTER1_SRST_OFFSET 0x0624
#define INPUT_FORMATTER2_SRST_OFFSET 0x0424
#define INPUT_FORMATTER3_SRST_OFFSET 0x0224
#define INPUT_FORMATTER0_SRST_MASK 0x0001
#define INPUT_FORMATTER1_SRST_MASK 0x0002
#define INPUT_FORMATTER2_SRST_MASK 0x0004
#define INPUT_FORMATTER3_SRST_MASK 0x0008
typedef enum {
INPUT_SYSTEM0_ID = 0,
N_INPUT_SYSTEM_ID
} input_system_ID_t;
typedef enum {
RX0_ID = 0,
N_RX_ID
} rx_ID_t;
enum mipi_port_id {
MIPI_PORT0_ID = 0,
MIPI_PORT1_ID,
MIPI_PORT2_ID,
N_MIPI_PORT_ID
};
#define N_RX_CHANNEL_ID 4
/* Generic port enumeration with an internal port type ID */
typedef enum {
CSI_PORT0_ID = 0,
CSI_PORT1_ID,
CSI_PORT2_ID,
TPG_PORT0_ID,
PRBS_PORT0_ID,
FIFO_PORT0_ID,
MEMORY_PORT0_ID,
N_INPUT_PORT_ID
} input_port_ID_t;
typedef enum {
CAPTURE_UNIT0_ID = 0,
CAPTURE_UNIT1_ID,
CAPTURE_UNIT2_ID,
ACQUISITION_UNIT0_ID,
DMA_UNIT0_ID,
CTRL_UNIT0_ID,
GPREGS_UNIT0_ID,
FIFO_UNIT0_ID,
IRQ_UNIT0_ID,
N_SUB_SYSTEM_ID
} sub_system_ID_t;
#define N_CAPTURE_UNIT_ID 3
#define N_ACQUISITION_UNIT_ID 1
#define N_CTRL_UNIT_ID 1
enum ia_css_isp_memories {
IA_CSS_ISP_PMEM0 = 0,
IA_CSS_ISP_DMEM0,
IA_CSS_ISP_VMEM0,
IA_CSS_ISP_VAMEM0,
IA_CSS_ISP_VAMEM1,
IA_CSS_ISP_VAMEM2,
IA_CSS_ISP_HMEM0,
IA_CSS_SP_DMEM0,
IA_CSS_DDR,
N_IA_CSS_MEMORIES
};
#define IA_CSS_NUM_MEMORIES 9
/* For driver compatibility */
#define N_IA_CSS_ISP_MEMORIES IA_CSS_NUM_MEMORIES
#define IA_CSS_NUM_ISP_MEMORIES IA_CSS_NUM_MEMORIES
#if 0
typedef enum {
dev_chn, /* device channels, external resource */
ext_mem, /* external memories */
int_mem, /* internal memories */
int_chn /* internal channels, user defined */
} resource_type_t;
/* if this enum is extended with other memory resources, pls also extend the function resource_to_memptr() */
typedef enum {
vied_nci_dev_chn_dma_ext0,
int_mem_vmem0,
int_mem_dmem0
} resource_id_t;
/* enum listing the different memories within a program group.
This enum is used in the mem_ptr_t type */
typedef enum {
buf_mem_invalid = 0,
buf_mem_vmem_prog0,
buf_mem_dmem_prog0
} buf_mem_t;
#endif
#endif /* __SYSTEM_GLOBAL_H_INCLUDED__ */
drivers/staging/media/atomisp/pci/isp2400_system_local.h deleted 100644 → 0
View file @ 071fb1bc
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2010-2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef __SYSTEM_LOCAL_H_INCLUDED__
#define __SYSTEM_LOCAL_H_INCLUDED__
#ifdef HRT_ISP_CSS_CUSTOM_HOST
#ifndef HRT_USE_VIR_ADDRS
#define HRT_USE_VIR_ADDRS
#endif
#endif
#include "system_global.h"
/* HRT assumes 32 by default (see Linux/include/hive_types.h), overrule it in case it is different */
#undef HRT_ADDRESS_WIDTH
#define HRT_ADDRESS_WIDTH 64 /* Surprise, this is a local property */
/* This interface is deprecated */
#include "hive_types.h"
/*
* Cell specific address maps
*/
#if HRT_ADDRESS_WIDTH == 64
#define GP_FIFO_BASE ((hrt_address)0x0000000000090104) /* This is NOT a base address */
/* DDR */
static const hrt_address DDR_BASE[N_DDR_ID] = {
(hrt_address)0x0000000120000000ULL
};
/* ISP */
static const hrt_address ISP_CTRL_BASE[N_ISP_ID] = {
(hrt_address)0x0000000000020000ULL
};
static const hrt_address ISP_DMEM_BASE[N_ISP_ID] = {
(hrt_address)0x0000000000200000ULL
};
static const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = {
(hrt_address)0x0000000000100000ULL
};
static const hrt_address ISP_VAMEM_BASE[N_VAMEM_ID] = {
(hrt_address)0x00000000001C0000ULL,
(hrt_address)0x00000000001D0000ULL,
(hrt_address)0x00000000001E0000ULL
};
static const hrt_address ISP_HMEM_BASE[N_HMEM_ID] = {
(hrt_address)0x00000000001F0000ULL
};
/* SP */
static const hrt_address SP_CTRL_BASE[N_SP_ID] = {
(hrt_address)0x0000000000010000ULL
};
static const hrt_address SP_DMEM_BASE[N_SP_ID] = {
(hrt_address)0x0000000000300000ULL
};
static const hrt_address SP_PMEM_BASE[N_SP_ID] = {
(hrt_address)0x00000000000B0000ULL
};
/* MMU */
/*
* MMU0_ID: The data MMU
* MMU1_ID: The icache MMU
*/
static const hrt_address MMU_BASE[N_MMU_ID] = {
(hrt_address)0x0000000000070000ULL,
(hrt_address)0x00000000000A0000ULL
};
/* DMA */
static const hrt_address DMA_BASE[N_DMA_ID] = {
(hrt_address)0x0000000000040000ULL
};
/* IRQ */
static const hrt_address IRQ_BASE[N_IRQ_ID] = {
(hrt_address)0x0000000000000500ULL,
(hrt_address)0x0000000000030A00ULL,
(hrt_address)0x000000000008C000ULL,
(hrt_address)0x0000000000090200ULL
};
/*
(hrt_address)0x0000000000000500ULL};
*/
/* GDC */
static const hrt_address GDC_BASE[N_GDC_ID] = {
(hrt_address)0x0000000000050000ULL,
(hrt_address)0x0000000000060000ULL
};
/* FIFO_MONITOR (not a subset of GP_DEVICE) */
static const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = {
(hrt_address)0x0000000000000000ULL
};
/*
static const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = {
(hrt_address)0x0000000000000000ULL};
static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
(hrt_address)0x0000000000090000ULL};
*/
/* GP_DEVICE (single base for all separate GP_REG instances) */
static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
(hrt_address)0x0000000000000000ULL
};
/*GP TIMER , all timer registers are inter-twined,
* so, having multiple base addresses for
* different timers does not help*/
static const hrt_address GP_TIMER_BASE =
(hrt_address)0x0000000000000600ULL;
/* GPIO */
static const hrt_address GPIO_BASE[N_GPIO_ID] = {
(hrt_address)0x0000000000000400ULL
};
/* TIMED_CTRL */
static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = {
(hrt_address)0x0000000000000100ULL
};
/* INPUT_FORMATTER */
static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = {
(hrt_address)0x0000000000030000ULL,
(hrt_address)0x0000000000030200ULL,
(hrt_address)0x0000000000030400ULL,
(hrt_address)0x0000000000030600ULL
}; /* memcpy() */
/* INPUT_SYSTEM */
static const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = {
(hrt_address)0x0000000000080000ULL
};
/* (hrt_address)0x0000000000081000ULL, */ /* capture A */
/* (hrt_address)0x0000000000082000ULL, */ /* capture B */
/* (hrt_address)0x0000000000083000ULL, */ /* capture C */
/* (hrt_address)0x0000000000084000ULL, */ /* Acquisition */
/* (hrt_address)0x0000000000085000ULL, */ /* DMA */
/* (hrt_address)0x0000000000089000ULL, */ /* ctrl */
/* (hrt_address)0x000000000008A000ULL, */ /* GP regs */
/* (hrt_address)0x000000000008B000ULL, */ /* FIFO */
/* (hrt_address)0x000000000008C000ULL, */ /* IRQ */
/* RX, the MIPI lane control regs start at offset 0 */
static const hrt_address RX_BASE[N_RX_ID] = {
(hrt_address)0x0000000000080100ULL
};
#elif HRT_ADDRESS_WIDTH == 32
#define GP_FIFO_BASE ((hrt_address)0x00090104) /* This is NOT a base address */
/* DDR : Attention, this value not defined in 32-bit */
static const hrt_address DDR_BASE[N_DDR_ID] = {
(hrt_address)0x00000000UL
};
/* ISP */
static const hrt_address ISP_CTRL_BASE[N_ISP_ID] = {
(hrt_address)0x00020000UL
};
static const hrt_address ISP_DMEM_BASE[N_ISP_ID] = {
(hrt_address)0x00200000UL
};
static const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = {
(hrt_address)0x100000UL
};
static const hrt_address ISP_VAMEM_BASE[N_VAMEM_ID] = {
(hrt_address)0xffffffffUL,
(hrt_address)0xffffffffUL,
(hrt_address)0xffffffffUL
};
static const hrt_address ISP_HMEM_BASE[N_HMEM_ID] = {
(hrt_address)0xffffffffUL
};
/* SP */
static const hrt_address SP_CTRL_BASE[N_SP_ID] = {
(hrt_address)0x00010000UL
};
static const hrt_address SP_DMEM_BASE[N_SP_ID] = {
(hrt_address)0x00300000UL
};
static const hrt_address SP_PMEM_BASE[N_SP_ID] = {
(hrt_address)0x000B0000UL
};
/* MMU */
/*
* MMU0_ID: The data MMU
* MMU1_ID: The icache MMU
*/
static const hrt_address MMU_BASE[N_MMU_ID] = {
(hrt_address)0x00070000UL,
(hrt_address)0x000A0000UL
};
/* DMA */
static const hrt_address DMA_BASE[N_DMA_ID] = {
(hrt_address)0x00040000UL
};
/* IRQ */
static const hrt_address IRQ_BASE[N_IRQ_ID] = {
(hrt_address)0x00000500UL,
(hrt_address)0x00030A00UL,
(hrt_address)0x0008C000UL,
(hrt_address)0x00090200UL
};
/*
(hrt_address)0x00000500UL};
*/
/* GDC */
static const hrt_address GDC_BASE[N_GDC_ID] = {
(hrt_address)0x00050000UL,
(hrt_address)0x00060000UL
};
/* FIFO_MONITOR (not a subset of GP_DEVICE) */
static const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = {
(hrt_address)0x00000000UL
};
/*
static const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = {
(hrt_address)0x00000000UL};
static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
(hrt_address)0x00090000UL};
*/
/* GP_DEVICE (single base for all separate GP_REG instances) */
static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
(hrt_address)0x00000000UL
};
/*GP TIMER , all timer registers are inter-twined,
* so, having multiple base addresses for
* different timers does not help*/
static const hrt_address GP_TIMER_BASE =
(hrt_address)0x00000600UL;
/* GPIO */
static const hrt_address GPIO_BASE[N_GPIO_ID] = {
(hrt_address)0x00000400UL
};
/* TIMED_CTRL */
static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = {
(hrt_address)0x00000100UL
};
/* INPUT_FORMATTER */
static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = {
(hrt_address)0x00030000UL,
(hrt_address)0x00030200UL,
(hrt_address)0x00030400UL
};
/* (hrt_address)0x00030600UL, */ /* memcpy() */
/* INPUT_SYSTEM */
static const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = {
(hrt_address)0x00080000UL
};
/* (hrt_address)0x00081000UL, */ /* capture A */
/* (hrt_address)0x00082000UL, */ /* capture B */
/* (hrt_address)0x00083000UL, */ /* capture C */
/* (hrt_address)0x00084000UL, */ /* Acquisition */
/* (hrt_address)0x00085000UL, */ /* DMA */
/* (hrt_address)0x00089000UL, */ /* ctrl */
/* (hrt_address)0x0008A000UL, */ /* GP regs */
/* (hrt_address)0x0008B000UL, */ /* FIFO */
/* (hrt_address)0x0008C000UL, */ /* IRQ */
/* RX, the MIPI lane control regs start at offset 0 */
static const hrt_address RX_BASE[N_RX_ID] = {
(hrt_address)0x00080100UL
};
#else
#error "system_local.h: HRT_ADDRESS_WIDTH must be one of {32,64}"
#endif
#endif /* __SYSTEM_LOCAL_H_INCLUDED__ */
drivers/staging/media/atomisp/pci/isp2401_system_global.h
View file @ d15be546
...@@ -13,415 +13,7 @@ ...@@ -13,415 +13,7 @@
* more details. * more details.
*/ */
#ifndef __SYSTEM_GLOBAL_H_INCLUDED__ #define HAS_NO_INPUT_FORMATTER
#define __SYSTEM_GLOBAL_H_INCLUDED__
#include <hive_isp_css_defs.h>
#include <type_support.h>
/*
* The longest allowed (uninteruptible) bus transfer, does not
* take stalling into account
*/
#define HIVE_ISP_MAX_BURST_LENGTH 1024
/*
* Maximum allowed burst length in words for the ISP DMA
* This value is set to 2 to prevent the ISP DMA from blocking
* the bus for too long; as the input system can only buffer
* 2 lines on Moorefield and Cherrytrail, the input system buffers
* may overflow if blocked for too long (BZ 2726).
*/
#define ISP_DMA_MAX_BURST_LENGTH 2
/*
* Create a list of HAS and IS properties that defines the system
*
* The configuration assumes the following
* - The system is hetereogeneous; Multiple cells and devices classes
* - The cell and device instances are homogeneous, each device type
* belongs to the same class
* - Device instances supporting a subset of the class capabilities are
* allowed
*
* We could manage different device classes through the enumerated
* lists (C) or the use of classes (C++), but that is presently not
* fully supported
*
* N.B. the 3 input formatters are of 2 different classess
*/
#define USE_INPUT_SYSTEM_VERSION_2401 #define USE_INPUT_SYSTEM_VERSION_2401
#define HAS_MMU_VERSION_2
#define HAS_DMA_VERSION_2
#define HAS_GDC_VERSION_2
#define HAS_VAMEM_VERSION_2
#define HAS_HMEM_VERSION_1
#define HAS_BAMEM_VERSION_2
#define HAS_IRQ_VERSION_2
#define HAS_IRQ_MAP_VERSION_2
#define HAS_INPUT_FORMATTER_VERSION_2
/* 2401: HAS_INPUT_SYSTEM_VERSION_3 */
/* 2400: HAS_INPUT_SYSTEM_VERSION_2 */
#define HAS_INPUT_SYSTEM_VERSION_2
#define HAS_INPUT_SYSTEM_VERSION_2401 #define HAS_INPUT_SYSTEM_VERSION_2401
#define HAS_BUFFERED_SENSOR
#define HAS_FIFO_MONITORS_VERSION_2
/* #define HAS_GP_REGS_VERSION_2 */
#define HAS_GP_DEVICE_VERSION_2
#define HAS_GPIO_VERSION_1
#define HAS_TIMED_CTRL_VERSION_1
#define HAS_RX_VERSION_2
#define HAS_NO_INPUT_FORMATTER
/*#define HAS_NO_PACKED_RAW_PIXELS*/
/*#define HAS_NO_DVS_6AXIS_CONFIG_UPDATE*/
#define DMA_DDR_TO_VAMEM_WORKAROUND
#define DMA_DDR_TO_HMEM_WORKAROUND
/*
* Semi global. "HRT" is accessible from SP, but
* the HRT types do not fully apply
*/
#define HRT_VADDRESS_WIDTH 32
/* Surprise, this is a local property*/
/*#define HRT_ADDRESS_WIDTH 64 */
#define HRT_DATA_WIDTH 32
#define SIZEOF_HRT_REG (HRT_DATA_WIDTH >> 3)
#define HIVE_ISP_CTRL_DATA_BYTES (HIVE_ISP_CTRL_DATA_WIDTH / 8)
/* The main bus connecting all devices */
#define HRT_BUS_WIDTH HIVE_ISP_CTRL_DATA_WIDTH
#define HRT_BUS_BYTES HIVE_ISP_CTRL_DATA_BYTES
#define CSI2P_DISABLE_ISYS2401_ONLINE_MODE #define CSI2P_DISABLE_ISYS2401_ONLINE_MODE
/* per-frame parameter handling support */
#define SH_CSS_ENABLE_PER_FRAME_PARAMS
typedef u32 hrt_bus_align_t;
/*
* Enumerate the devices, device access through the API is by ID,
* through the DLI by address. The enumerator terminators are used
* to size the wiring arrays and as an exception value.
*/
typedef enum {
DDR0_ID = 0,
N_DDR_ID
} ddr_ID_t;
typedef enum {
ISP0_ID = 0,
N_ISP_ID
} isp_ID_t;
typedef enum {
SP0_ID = 0,
N_SP_ID
} sp_ID_t;
typedef enum {
MMU0_ID = 0,
MMU1_ID,
N_MMU_ID
} mmu_ID_t;
typedef enum {
DMA0_ID = 0,
N_DMA_ID
} dma_ID_t;
typedef enum {
GDC0_ID = 0,
GDC1_ID,
N_GDC_ID
} gdc_ID_t;
/* this extra define is needed because we want to use it also
in the preprocessor, and that doesn't work with enums.
*/
#define N_GDC_ID_CPP 2
typedef enum {
VAMEM0_ID = 0,
VAMEM1_ID,
VAMEM2_ID,
N_VAMEM_ID
} vamem_ID_t;
typedef enum {
BAMEM0_ID = 0,
N_BAMEM_ID
} bamem_ID_t;
typedef enum {
HMEM0_ID = 0,
N_HMEM_ID
} hmem_ID_t;
typedef enum {
ISYS_IRQ0_ID = 0, /* port a */
ISYS_IRQ1_ID, /* port b */
ISYS_IRQ2_ID, /* port c */
N_ISYS_IRQ_ID
} isys_irq_ID_t;
typedef enum {
IRQ0_ID = 0, /* GP IRQ block */
IRQ1_ID, /* Input formatter */
IRQ2_ID, /* input system */
IRQ3_ID, /* input selector */
N_IRQ_ID
} irq_ID_t;
typedef enum {
FIFO_MONITOR0_ID = 0,
N_FIFO_MONITOR_ID
} fifo_monitor_ID_t;
/*
* Deprecated: Since all gp_reg instances are different
* and put in the address maps of other devices we cannot
* enumerate them as that assumes the instrances are the
* same.
*
* We define a single GP_DEVICE containing all gp_regs
* w.r.t. a single base address
*
typedef enum {
GP_REGS0_ID = 0,
N_GP_REGS_ID
} gp_regs_ID_t;
*/
typedef enum {
GP_DEVICE0_ID = 0,
N_GP_DEVICE_ID
} gp_device_ID_t;
typedef enum {
GP_TIMER0_ID = 0,
GP_TIMER1_ID,
GP_TIMER2_ID,
GP_TIMER3_ID,
GP_TIMER4_ID,
GP_TIMER5_ID,
GP_TIMER6_ID,
GP_TIMER7_ID,
N_GP_TIMER_ID
} gp_timer_ID_t;
typedef enum {
GPIO0_ID = 0,
N_GPIO_ID
} gpio_ID_t;
typedef enum {
TIMED_CTRL0_ID = 0,
N_TIMED_CTRL_ID
} timed_ctrl_ID_t;
typedef enum {
INPUT_FORMATTER0_ID = 0,
INPUT_FORMATTER1_ID,
INPUT_FORMATTER2_ID,
INPUT_FORMATTER3_ID,
N_INPUT_FORMATTER_ID
} input_formatter_ID_t;
/* The IF RST is outside the IF */
#define INPUT_FORMATTER0_SRST_OFFSET 0x0824
#define INPUT_FORMATTER1_SRST_OFFSET 0x0624
#define INPUT_FORMATTER2_SRST_OFFSET 0x0424
#define INPUT_FORMATTER3_SRST_OFFSET 0x0224
#define INPUT_FORMATTER0_SRST_MASK 0x0001
#define INPUT_FORMATTER1_SRST_MASK 0x0002
#define INPUT_FORMATTER2_SRST_MASK 0x0004
#define INPUT_FORMATTER3_SRST_MASK 0x0008
typedef enum {
INPUT_SYSTEM0_ID = 0,
N_INPUT_SYSTEM_ID
} input_system_ID_t;
typedef enum {
RX0_ID = 0,
N_RX_ID
} rx_ID_t;
enum mipi_port_id {
MIPI_PORT0_ID = 0,
MIPI_PORT1_ID,
MIPI_PORT2_ID,
N_MIPI_PORT_ID
};
#define N_RX_CHANNEL_ID 4
/* Generic port enumeration with an internal port type ID */
typedef enum {
CSI_PORT0_ID = 0,
CSI_PORT1_ID,
CSI_PORT2_ID,
TPG_PORT0_ID,
PRBS_PORT0_ID,
FIFO_PORT0_ID,
MEMORY_PORT0_ID,
N_INPUT_PORT_ID
} input_port_ID_t;
typedef enum {
CAPTURE_UNIT0_ID = 0,
CAPTURE_UNIT1_ID,
CAPTURE_UNIT2_ID,
ACQUISITION_UNIT0_ID,
DMA_UNIT0_ID,
CTRL_UNIT0_ID,
GPREGS_UNIT0_ID,
FIFO_UNIT0_ID,
IRQ_UNIT0_ID,
N_SUB_SYSTEM_ID
} sub_system_ID_t;
#define N_CAPTURE_UNIT_ID 3
#define N_ACQUISITION_UNIT_ID 1
#define N_CTRL_UNIT_ID 1
/*
* Input-buffer Controller.
*/
typedef enum {
IBUF_CTRL0_ID = 0, /* map to ISYS2401_IBUF_CNTRL_A */
IBUF_CTRL1_ID, /* map to ISYS2401_IBUF_CNTRL_B */
IBUF_CTRL2_ID, /* map ISYS2401_IBUF_CNTRL_C */
N_IBUF_CTRL_ID
} ibuf_ctrl_ID_t;
/* end of Input-buffer Controller */
/*
* Stream2MMIO.
*/
typedef enum {
STREAM2MMIO0_ID = 0, /* map to ISYS2401_S2M_A */
STREAM2MMIO1_ID, /* map to ISYS2401_S2M_B */
STREAM2MMIO2_ID, /* map to ISYS2401_S2M_C */
N_STREAM2MMIO_ID
} stream2mmio_ID_t;
typedef enum {
/*
* Stream2MMIO 0 has 8 SIDs that are indexed by
* [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID7_ID].
*
* Stream2MMIO 1 has 4 SIDs that are indexed by
* [STREAM2MMIO_SID0_ID...TREAM2MMIO_SID3_ID].
*
* Stream2MMIO 2 has 4 SIDs that are indexed by
* [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID3_ID].
*/
STREAM2MMIO_SID0_ID = 0,
STREAM2MMIO_SID1_ID,
STREAM2MMIO_SID2_ID,
STREAM2MMIO_SID3_ID,
STREAM2MMIO_SID4_ID,
STREAM2MMIO_SID5_ID,
STREAM2MMIO_SID6_ID,
STREAM2MMIO_SID7_ID,
N_STREAM2MMIO_SID_ID
} stream2mmio_sid_ID_t;
/* end of Stream2MMIO */
/**
* Input System 2401: CSI-MIPI recevier.
*/
typedef enum {
CSI_RX_BACKEND0_ID = 0, /* map to ISYS2401_MIPI_BE_A */
CSI_RX_BACKEND1_ID, /* map to ISYS2401_MIPI_BE_B */
CSI_RX_BACKEND2_ID, /* map to ISYS2401_MIPI_BE_C */
N_CSI_RX_BACKEND_ID
} csi_rx_backend_ID_t;
typedef enum {
CSI_RX_FRONTEND0_ID = 0, /* map to ISYS2401_CSI_RX_A */
CSI_RX_FRONTEND1_ID, /* map to ISYS2401_CSI_RX_B */
CSI_RX_FRONTEND2_ID, /* map to ISYS2401_CSI_RX_C */
#define N_CSI_RX_FRONTEND_ID (CSI_RX_FRONTEND2_ID + 1)
} csi_rx_frontend_ID_t;
typedef enum {
CSI_RX_DLANE0_ID = 0, /* map to DLANE0 in CSI RX */
CSI_RX_DLANE1_ID, /* map to DLANE1 in CSI RX */
CSI_RX_DLANE2_ID, /* map to DLANE2 in CSI RX */
CSI_RX_DLANE3_ID, /* map to DLANE3 in CSI RX */
N_CSI_RX_DLANE_ID
} csi_rx_fe_dlane_ID_t;
/* end of CSI-MIPI receiver */
typedef enum {
ISYS2401_DMA0_ID = 0,
N_ISYS2401_DMA_ID
} isys2401_dma_ID_t;
/**
* Pixel-generator. ("system_global.h")
*/
typedef enum {
PIXELGEN0_ID = 0,
PIXELGEN1_ID,
PIXELGEN2_ID,
N_PIXELGEN_ID
} pixelgen_ID_t;
/* end of pixel-generator. ("system_global.h") */
typedef enum {
INPUT_SYSTEM_CSI_PORT0_ID = 0,
INPUT_SYSTEM_CSI_PORT1_ID,
INPUT_SYSTEM_CSI_PORT2_ID,
INPUT_SYSTEM_PIXELGEN_PORT0_ID,
INPUT_SYSTEM_PIXELGEN_PORT1_ID,
INPUT_SYSTEM_PIXELGEN_PORT2_ID,
N_INPUT_SYSTEM_INPUT_PORT_ID
} input_system_input_port_ID_t;
#define N_INPUT_SYSTEM_CSI_PORT 3
typedef enum {
ISYS2401_DMA_CHANNEL_0 = 0,
ISYS2401_DMA_CHANNEL_1,
ISYS2401_DMA_CHANNEL_2,
ISYS2401_DMA_CHANNEL_3,
ISYS2401_DMA_CHANNEL_4,
ISYS2401_DMA_CHANNEL_5,
ISYS2401_DMA_CHANNEL_6,
ISYS2401_DMA_CHANNEL_7,
ISYS2401_DMA_CHANNEL_8,
ISYS2401_DMA_CHANNEL_9,
ISYS2401_DMA_CHANNEL_10,
ISYS2401_DMA_CHANNEL_11,
N_ISYS2401_DMA_CHANNEL
} isys2401_dma_channel;
enum ia_css_isp_memories {
IA_CSS_ISP_PMEM0 = 0,
IA_CSS_ISP_DMEM0,
IA_CSS_ISP_VMEM0,
IA_CSS_ISP_VAMEM0,
IA_CSS_ISP_VAMEM1,
IA_CSS_ISP_VAMEM2,
IA_CSS_ISP_HMEM0,
IA_CSS_SP_DMEM0,
IA_CSS_DDR,
N_IA_CSS_MEMORIES
};
#define IA_CSS_NUM_MEMORIES 9
/* For driver compatibility */
#define N_IA_CSS_ISP_MEMORIES IA_CSS_NUM_MEMORIES
#define IA_CSS_NUM_ISP_MEMORIES IA_CSS_NUM_MEMORIES
#endif /* __SYSTEM_GLOBAL_H_INCLUDED__ */
drivers/staging/media/atomisp/pci/sh_css.c
View file @ d15be546
...@@ -1841,8 +1841,13 @@ ia_css_init(struct device *dev, const struct ia_css_env *env, ...@@ -1841,8 +1841,13 @@ ia_css_init(struct device *dev, const struct ia_css_env *env,
#endif #endif
#if !defined(HAS_NO_INPUT_SYSTEM) #if !defined(HAS_NO_INPUT_SYSTEM)
dma_set_max_burst_size(DMA0_ID, HIVE_DMA_BUS_DDR_CONN,
ISP_DMA_MAX_BURST_LENGTH); if (!IS_ISP2401)
dma_set_max_burst_size(DMA0_ID, HIVE_DMA_BUS_DDR_CONN,
ISP2400_DMA_MAX_BURST_LENGTH);
else
dma_set_max_burst_size(DMA0_ID, HIVE_DMA_BUS_DDR_CONN,
ISP2401_DMA_MAX_BURST_LENGTH);
if (ia_css_isys_init() != INPUT_SYSTEM_ERR_NO_ERROR) if (ia_css_isys_init() != INPUT_SYSTEM_ERR_NO_ERROR)
err = -EINVAL; err = -EINVAL;
......
drivers/staging/media/atomisp/pci/system_global.h
View file @ d15be546
...@@ -4,8 +4,403 @@ ...@@ -4,8 +4,403 @@
* (c) 2020 Mauro Carvalho Chehab <mchehab+huawei@kernel.org> * (c) 2020 Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
*/ */
#ifndef __SYSTEM_GLOBAL_H_INCLUDED__
#define __SYSTEM_GLOBAL_H_INCLUDED__
/*
* Create a list of HAS and IS properties that defines the system
* Those are common for both ISP2400 and ISP2401
*
* The configuration assumes the following
* - The system is hetereogeneous; Multiple cells and devices classes
* - The cell and device instances are homogeneous, each device type
* belongs to the same class
* - Device instances supporting a subset of the class capabilities are
* allowed
*
* We could manage different device classes through the enumerated
* lists (C) or the use of classes (C++), but that is presently not
* fully supported
*
* N.B. the 3 input formatters are of 2 different classess
*/
#define HAS_MMU_VERSION_2
#define HAS_DMA_VERSION_2
#define HAS_GDC_VERSION_2
#define HAS_VAMEM_VERSION_2
#define HAS_HMEM_VERSION_1
#define HAS_BAMEM_VERSION_2
#define HAS_IRQ_VERSION_2
#define HAS_IRQ_MAP_VERSION_2
#define HAS_INPUT_FORMATTER_VERSION_2
#define HAS_INPUT_SYSTEM_VERSION_2
#define HAS_BUFFERED_SENSOR
#define HAS_FIFO_MONITORS_VERSION_2
#define HAS_GP_DEVICE_VERSION_2
#define HAS_GPIO_VERSION_1
#define HAS_TIMED_CTRL_VERSION_1
#define HAS_RX_VERSION_2
/* per-frame parameter handling support */
#define SH_CSS_ENABLE_PER_FRAME_PARAMS
#define DMA_DDR_TO_VAMEM_WORKAROUND
#define DMA_DDR_TO_HMEM_WORKAROUND
/*
* The longest allowed (uninteruptible) bus transfer, does not
* take stalling into account
*/
#define HIVE_ISP_MAX_BURST_LENGTH 1024
/*
* Maximum allowed burst length in words for the ISP DMA
* This value is set to 2 to prevent the ISP DMA from blocking
* the bus for too long; as the input system can only buffer
* 2 lines on Moorefield and Cherrytrail, the input system buffers
* may overflow if blocked for too long (BZ 2726).
*/
#define ISP2400_DMA_MAX_BURST_LENGTH 128
#define ISP2401_DMA_MAX_BURST_LENGTH 2
#ifdef ISP2401 #ifdef ISP2401
# include "isp2401_system_global.h" # include "isp2401_system_global.h"
#else #else
# include "isp2400_system_global.h" # include "isp2400_system_global.h"
#endif #endif
#include <hive_isp_css_defs.h>
#include <type_support.h>
/* This interface is deprecated */
#include "hive_types.h"
/*
* Semi global. "HRT" is accessible from SP, but the HRT types do not fully apply
*/
#define HRT_VADDRESS_WIDTH 32
#define SIZEOF_HRT_REG (HRT_DATA_WIDTH >> 3)
#define HIVE_ISP_CTRL_DATA_BYTES (HIVE_ISP_CTRL_DATA_WIDTH / 8)
/* The main bus connecting all devices */
#define HRT_BUS_WIDTH HIVE_ISP_CTRL_DATA_WIDTH
#define HRT_BUS_BYTES HIVE_ISP_CTRL_DATA_BYTES
typedef u32 hrt_bus_align_t;
/*
* Enumerate the devices, device access through the API is by ID,
* through the DLI by address. The enumerator terminators are used
* to size the wiring arrays and as an exception value.
*/
typedef enum {
DDR0_ID = 0,
N_DDR_ID
} ddr_ID_t;
typedef enum {
ISP0_ID = 0,
N_ISP_ID
} isp_ID_t;
typedef enum {
SP0_ID = 0,
N_SP_ID
} sp_ID_t;
typedef enum {
MMU0_ID = 0,
MMU1_ID,
N_MMU_ID
} mmu_ID_t;
typedef enum {
DMA0_ID = 0,
N_DMA_ID
} dma_ID_t;
typedef enum {
GDC0_ID = 0,
GDC1_ID,
N_GDC_ID
} gdc_ID_t;
/* this extra define is needed because we want to use it also
in the preprocessor, and that doesn't work with enums.
*/
#define N_GDC_ID_CPP 2
typedef enum {
VAMEM0_ID = 0,
VAMEM1_ID,
VAMEM2_ID,
N_VAMEM_ID
} vamem_ID_t;
typedef enum {
BAMEM0_ID = 0,
N_BAMEM_ID
} bamem_ID_t;
typedef enum {
HMEM0_ID = 0,
N_HMEM_ID
} hmem_ID_t;
typedef enum {
IRQ0_ID = 0, /* GP IRQ block */
IRQ1_ID, /* Input formatter */
IRQ2_ID, /* input system */
IRQ3_ID, /* input selector */
N_IRQ_ID
} irq_ID_t;
typedef enum {
FIFO_MONITOR0_ID = 0,
N_FIFO_MONITOR_ID
} fifo_monitor_ID_t;
typedef enum {
GP_DEVICE0_ID = 0,
N_GP_DEVICE_ID
} gp_device_ID_t;
typedef enum {
GP_TIMER0_ID = 0,
GP_TIMER1_ID,
GP_TIMER2_ID,
GP_TIMER3_ID,
GP_TIMER4_ID,
GP_TIMER5_ID,
GP_TIMER6_ID,
GP_TIMER7_ID,
N_GP_TIMER_ID
} gp_timer_ID_t;
typedef enum {
GPIO0_ID = 0,
N_GPIO_ID
} gpio_ID_t;
typedef enum {
TIMED_CTRL0_ID = 0,
N_TIMED_CTRL_ID
} timed_ctrl_ID_t;
typedef enum {
INPUT_FORMATTER0_ID = 0,
INPUT_FORMATTER1_ID,
INPUT_FORMATTER2_ID,
INPUT_FORMATTER3_ID,
N_INPUT_FORMATTER_ID
} input_formatter_ID_t;
/* The IF RST is outside the IF */
#define INPUT_FORMATTER0_SRST_OFFSET 0x0824
#define INPUT_FORMATTER1_SRST_OFFSET 0x0624
#define INPUT_FORMATTER2_SRST_OFFSET 0x0424
#define INPUT_FORMATTER3_SRST_OFFSET 0x0224
#define INPUT_FORMATTER0_SRST_MASK 0x0001
#define INPUT_FORMATTER1_SRST_MASK 0x0002
#define INPUT_FORMATTER2_SRST_MASK 0x0004
#define INPUT_FORMATTER3_SRST_MASK 0x0008
typedef enum {
INPUT_SYSTEM0_ID = 0,
N_INPUT_SYSTEM_ID
} input_system_ID_t;
typedef enum {
RX0_ID = 0,
N_RX_ID
} rx_ID_t;
enum mipi_port_id {
MIPI_PORT0_ID = 0,
MIPI_PORT1_ID,
MIPI_PORT2_ID,
N_MIPI_PORT_ID
};
#define N_RX_CHANNEL_ID 4
/* Generic port enumeration with an internal port type ID */
typedef enum {
CSI_PORT0_ID = 0,
CSI_PORT1_ID,
CSI_PORT2_ID,
TPG_PORT0_ID,
PRBS_PORT0_ID,
FIFO_PORT0_ID,
MEMORY_PORT0_ID,
N_INPUT_PORT_ID
} input_port_ID_t;
typedef enum {
CAPTURE_UNIT0_ID = 0,
CAPTURE_UNIT1_ID,
CAPTURE_UNIT2_ID,
ACQUISITION_UNIT0_ID,
DMA_UNIT0_ID,
CTRL_UNIT0_ID,
GPREGS_UNIT0_ID,
FIFO_UNIT0_ID,
IRQ_UNIT0_ID,
N_SUB_SYSTEM_ID
} sub_system_ID_t;
#define N_CAPTURE_UNIT_ID 3
#define N_ACQUISITION_UNIT_ID 1
#define N_CTRL_UNIT_ID 1
enum ia_css_isp_memories {
IA_CSS_ISP_PMEM0 = 0,
IA_CSS_ISP_DMEM0,
IA_CSS_ISP_VMEM0,
IA_CSS_ISP_VAMEM0,
IA_CSS_ISP_VAMEM1,
IA_CSS_ISP_VAMEM2,
IA_CSS_ISP_HMEM0,
IA_CSS_SP_DMEM0,
IA_CSS_DDR,
N_IA_CSS_MEMORIES
};
#define IA_CSS_NUM_MEMORIES 9
/* For driver compatibility */
#define N_IA_CSS_ISP_MEMORIES IA_CSS_NUM_MEMORIES
#define IA_CSS_NUM_ISP_MEMORIES IA_CSS_NUM_MEMORIES
/*
* ISP2401 specific enums
*/
typedef enum {
ISYS_IRQ0_ID = 0, /* port a */
ISYS_IRQ1_ID, /* port b */
ISYS_IRQ2_ID, /* port c */
N_ISYS_IRQ_ID
} isys_irq_ID_t;
/*
* Input-buffer Controller.
*/
typedef enum {
IBUF_CTRL0_ID = 0, /* map to ISYS2401_IBUF_CNTRL_A */
IBUF_CTRL1_ID, /* map to ISYS2401_IBUF_CNTRL_B */
IBUF_CTRL2_ID, /* map ISYS2401_IBUF_CNTRL_C */
N_IBUF_CTRL_ID
} ibuf_ctrl_ID_t;
/* end of Input-buffer Controller */
/*
* Stream2MMIO.
*/
typedef enum {
STREAM2MMIO0_ID = 0, /* map to ISYS2401_S2M_A */
STREAM2MMIO1_ID, /* map to ISYS2401_S2M_B */
STREAM2MMIO2_ID, /* map to ISYS2401_S2M_C */
N_STREAM2MMIO_ID
} stream2mmio_ID_t;
typedef enum {
/*
* Stream2MMIO 0 has 8 SIDs that are indexed by
* [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID7_ID].
*
* Stream2MMIO 1 has 4 SIDs that are indexed by
* [STREAM2MMIO_SID0_ID...TREAM2MMIO_SID3_ID].
*
* Stream2MMIO 2 has 4 SIDs that are indexed by
* [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID3_ID].
*/
STREAM2MMIO_SID0_ID = 0,
STREAM2MMIO_SID1_ID,
STREAM2MMIO_SID2_ID,
STREAM2MMIO_SID3_ID,
STREAM2MMIO_SID4_ID,
STREAM2MMIO_SID5_ID,
STREAM2MMIO_SID6_ID,
STREAM2MMIO_SID7_ID,
N_STREAM2MMIO_SID_ID
} stream2mmio_sid_ID_t;
/* end of Stream2MMIO */
/**
* Input System 2401: CSI-MIPI recevier.
*/
typedef enum {
CSI_RX_BACKEND0_ID = 0, /* map to ISYS2401_MIPI_BE_A */
CSI_RX_BACKEND1_ID, /* map to ISYS2401_MIPI_BE_B */
CSI_RX_BACKEND2_ID, /* map to ISYS2401_MIPI_BE_C */
N_CSI_RX_BACKEND_ID
} csi_rx_backend_ID_t;
typedef enum {
CSI_RX_FRONTEND0_ID = 0, /* map to ISYS2401_CSI_RX_A */
CSI_RX_FRONTEND1_ID, /* map to ISYS2401_CSI_RX_B */
CSI_RX_FRONTEND2_ID, /* map to ISYS2401_CSI_RX_C */
#define N_CSI_RX_FRONTEND_ID (CSI_RX_FRONTEND2_ID + 1)
} csi_rx_frontend_ID_t;
typedef enum {
CSI_RX_DLANE0_ID = 0, /* map to DLANE0 in CSI RX */
CSI_RX_DLANE1_ID, /* map to DLANE1 in CSI RX */
CSI_RX_DLANE2_ID, /* map to DLANE2 in CSI RX */
CSI_RX_DLANE3_ID, /* map to DLANE3 in CSI RX */
N_CSI_RX_DLANE_ID
} csi_rx_fe_dlane_ID_t;
/* end of CSI-MIPI receiver */
typedef enum {
ISYS2401_DMA0_ID = 0,
N_ISYS2401_DMA_ID
} isys2401_dma_ID_t;
/**
* Pixel-generator. ("system_global.h")
*/
typedef enum {
PIXELGEN0_ID = 0,
PIXELGEN1_ID,
PIXELGEN2_ID,
N_PIXELGEN_ID
} pixelgen_ID_t;
/* end of pixel-generator. ("system_global.h") */
typedef enum {
INPUT_SYSTEM_CSI_PORT0_ID = 0,
INPUT_SYSTEM_CSI_PORT1_ID,
INPUT_SYSTEM_CSI_PORT2_ID,
INPUT_SYSTEM_PIXELGEN_PORT0_ID,
INPUT_SYSTEM_PIXELGEN_PORT1_ID,
INPUT_SYSTEM_PIXELGEN_PORT2_ID,
N_INPUT_SYSTEM_INPUT_PORT_ID
} input_system_input_port_ID_t;
#define N_INPUT_SYSTEM_CSI_PORT 3
typedef enum {
ISYS2401_DMA_CHANNEL_0 = 0,
ISYS2401_DMA_CHANNEL_1,
ISYS2401_DMA_CHANNEL_2,
ISYS2401_DMA_CHANNEL_3,
ISYS2401_DMA_CHANNEL_4,
ISYS2401_DMA_CHANNEL_5,
ISYS2401_DMA_CHANNEL_6,
ISYS2401_DMA_CHANNEL_7,
ISYS2401_DMA_CHANNEL_8,
ISYS2401_DMA_CHANNEL_9,
ISYS2401_DMA_CHANNEL_10,
ISYS2401_DMA_CHANNEL_11,
N_ISYS2401_DMA_CHANNEL
} isys2401_dma_channel;
#endif /* __SYSTEM_GLOBAL_H_INCLUDED__ */
drivers/staging/media/atomisp/pci/system_local.h
View file @ d15be546
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: GPL-2.0 */
// SPDX-License-Identifier: GPL-2.0-or-later
/* /*
* (c) 2020 Mauro Carvalho Chehab <mchehab+huawei@kernel.org> * Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/ */
#ifdef ISP2401 #ifndef __SYSTEM_LOCAL_H_INCLUDED__
# include "isp2401_system_local.h" #define __SYSTEM_LOCAL_H_INCLUDED__
#else
# include "isp2400_system_local.h" #ifdef HRT_ISP_CSS_CUSTOM_HOST
#ifndef HRT_USE_VIR_ADDRS
#define HRT_USE_VIR_ADDRS
#endif
#endif #endif
#include "system_global.h"
/* This interface is deprecated */
#include "hive_types.h"
/*
* Cell specific address maps
*/
#define GP_FIFO_BASE ((hrt_address)0x0000000000090104) /* This is NOT a base address */
/* ISP */
extern const hrt_address ISP_CTRL_BASE[N_ISP_ID];
extern const hrt_address ISP_DMEM_BASE[N_ISP_ID];
extern const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID];
/* SP */
extern const hrt_address SP_CTRL_BASE[N_SP_ID];
extern const hrt_address SP_DMEM_BASE[N_SP_ID];
/* MMU */
extern const hrt_address MMU_BASE[N_MMU_ID];
/* DMA */
extern const hrt_address DMA_BASE[N_DMA_ID];
extern const hrt_address ISYS2401_DMA_BASE[N_ISYS2401_DMA_ID];
/* IRQ */
extern const hrt_address IRQ_BASE[N_IRQ_ID];
/* GDC */
extern const hrt_address GDC_BASE[N_GDC_ID];
/* FIFO_MONITOR (not a subset of GP_DEVICE) */
extern const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID];
/* GP_DEVICE (single base for all separate GP_REG instances) */
extern const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID];
/*GP TIMER , all timer registers are inter-twined,
* so, having multiple base addresses for
* different timers does not help*/
extern const hrt_address GP_TIMER_BASE;
/* GPIO */
extern const hrt_address GPIO_BASE[N_GPIO_ID];
/* TIMED_CTRL */
extern const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID];
/* INPUT_FORMATTER */
extern const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID];
/* INPUT_SYSTEM */
extern const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID];
/* RX, the MIPI lane control regs start at offset 0 */
extern const hrt_address RX_BASE[N_RX_ID];
/* IBUF_CTRL, part of the Input System 2401 */
extern const hrt_address IBUF_CTRL_BASE[N_IBUF_CTRL_ID];
/* ISYS IRQ Controllers, part of the Input System 2401 */
extern const hrt_address ISYS_IRQ_BASE[N_ISYS_IRQ_ID];
/* CSI FE, part of the Input System 2401 */
extern const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID];
/* CSI BE, part of the Input System 2401 */
extern const hrt_address CSI_RX_BE_CTRL_BASE[N_CSI_RX_BACKEND_ID];
/* PIXEL Generator, part of the Input System 2401 */
extern const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID];
/* Stream2MMIO, part of the Input System 2401 */
extern const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID];
#endif /* __SYSTEM_LOCAL_H_INCLUDED__ */
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