Commit d4e83843 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher

drm/amdgpu: added support 2nd UVD instance

Added psp fw loading support for vega20 2nd UVD instance.
Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Acked-by: default avatarHuang Rui <ray.huang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarFeifei Xu <Feifei.Xu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 851c2509
...@@ -193,6 +193,7 @@ enum AMDGPU_UCODE_ID { ...@@ -193,6 +193,7 @@ enum AMDGPU_UCODE_ID {
AMDGPU_UCODE_ID_STORAGE, AMDGPU_UCODE_ID_STORAGE,
AMDGPU_UCODE_ID_SMC, AMDGPU_UCODE_ID_SMC,
AMDGPU_UCODE_ID_UVD, AMDGPU_UCODE_ID_UVD,
AMDGPU_UCODE_ID_UVD1,
AMDGPU_UCODE_ID_VCE, AMDGPU_UCODE_ID_VCE,
AMDGPU_UCODE_ID_VCN, AMDGPU_UCODE_ID_VCN,
AMDGPU_UCODE_ID_MAXIMUM, AMDGPU_UCODE_ID_MAXIMUM,
......
...@@ -189,7 +189,8 @@ enum psp_gfx_fw_type ...@@ -189,7 +189,8 @@ enum psp_gfx_fw_type
GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM = 20, GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM = 20,
GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM = 21, GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM = 21,
GFX_FW_TYPE_RLC_RESTORE_LIST_CNTL = 22, GFX_FW_TYPE_RLC_RESTORE_LIST_CNTL = 22,
GFX_FW_TYPE_MAX = 23 GFX_FW_TYPE_UVD1 = 23,
GFX_FW_TYPE_MAX = 24
}; };
/* Command to load HW IP FW. */ /* Command to load HW IP FW. */
......
...@@ -81,6 +81,9 @@ psp_v11_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type * ...@@ -81,6 +81,9 @@ psp_v11_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *
case AMDGPU_UCODE_ID_VCE: case AMDGPU_UCODE_ID_VCE:
*type = GFX_FW_TYPE_VCE; *type = GFX_FW_TYPE_VCE;
break; break;
case AMDGPU_UCODE_ID_UVD1:
*type = GFX_FW_TYPE_UVD1;
break;
case AMDGPU_UCODE_ID_MAXIMUM: case AMDGPU_UCODE_ID_MAXIMUM:
default: default:
return -EINVAL; return -EINVAL;
......
...@@ -441,6 +441,13 @@ static int uvd_v7_0_sw_init(void *handle) ...@@ -441,6 +441,13 @@ static int uvd_v7_0_sw_init(void *handle)
adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw; adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw;
adev->firmware.fw_size += adev->firmware.fw_size +=
ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
if (adev->uvd.num_uvd_inst == UVD7_MAX_HW_INSTANCES_VEGA20) {
adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].ucode_id = AMDGPU_UCODE_ID_UVD1;
adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].fw = adev->uvd.fw;
adev->firmware.fw_size +=
ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
}
DRM_INFO("PSP loading UVD firmware\n"); DRM_INFO("PSP loading UVD firmware\n");
} }
......
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