[PATCH] Clean up MAX_NR_NODES/NUMNODES/etc. [5/5]

From: Matthew Dobson <colpatch@us.ibm.com>

Fix up the ia64 arch.

arch/ia64/kernel/acpi.c

@@ -41,6 +41,7 @@
 #include <linux/irq.h>
 #include <linux/acpi.h>
 #include <linux/efi.h>
+#include <linux/mmzone.h>
 #include <asm/io.h>
 #include <asm/iosapic.h>
 #include <asm/machvec.h>
@@ -341,7 +342,7 @@ static u32 __initdata pxm_flag[PXM_FLAG_LEN];
 #define pxm_bit_test(bit)	(test_bit(bit,(void *)pxm_flag))
 /* maps to convert between proximity domain and logical node ID */
 int __initdata pxm_to_nid_map[MAX_PXM_DOMAINS];
-int __initdata nid_to_pxm_map[NR_NODES];
+int __initdata nid_to_pxm_map[MAX_NUMNODES];
 static struct acpi_table_slit __initdata *slit_table;
 
 /*

arch/ia64/mm/discontig.c

@@ -14,7 +14,6 @@
 #include <linux/mm.h>
 #include <linux/swap.h>
 #include <linux/bootmem.h>
-#include <linux/mmzone.h>
 #include <linux/acpi.h>
 #include <linux/efi.h>
 #include <asm/pgalloc.h>
@@ -26,10 +25,10 @@
  */
 #define GRANULEROUNDUP(n) (((n)+IA64_GRANULE_SIZE-1) & ~(IA64_GRANULE_SIZE-1))
 
-static struct ia64_node_data	*node_data[NR_NODES];
-static long			boot_pg_data[8*NR_NODES+sizeof(pg_data_t)]  __initdata;
-static pg_data_t		*pg_data_ptr[NR_NODES] __initdata;
-static bootmem_data_t		bdata[NR_NODES][NR_BANKS_PER_NODE+1] __initdata;
+static struct ia64_node_data	*node_data[MAX_NUMNODES];
+static long			boot_pg_data[8*MAX_NUMNODES+sizeof(pg_data_t)]  __initdata;
+static pg_data_t		*pg_data_ptr[MAX_NUMNODES] __initdata;
+static bootmem_data_t		bdata[MAX_NUMNODES][NR_BANKS_PER_NODE+1] __initdata;
 /*
  * Return the compact node number of this cpu. Used prior to
  * setting up the cpu_data area.

arch/ia64/mm/numa.c

@@ -15,7 +15,6 @@
 #include <linux/mm.h>
 #include <linux/init.h>
 #include <linux/bootmem.h>
-#include <linux/mmzone.h>
 #include <asm/numa.h>
 
 /*
@@ -29,7 +28,7 @@ struct node_cpuid_s node_cpuid[NR_CPUS];
  * This is a matrix with "distances" between nodes, they should be
  * proportional to the memory access latency ratios.
  */
-u8 numa_slit[NR_NODES * NR_NODES];
+u8 numa_slit[MAX_NUMNODES * MAX_NUMNODES];
 
 /* Identify which cnode a physical address resides on */
 int

include/asm-ia64/acpi.h

@@ -99,7 +99,7 @@ int acpi_get_addr_space (void *obj, u8 type, u64 *base, u64 *length,u64 *tra);
 /* Proximity bitmap length; _PXM is at most 255 (8 bit)*/
 #define MAX_PXM_DOMAINS (256)
 extern int __initdata pxm_to_nid_map[MAX_PXM_DOMAINS];
-extern int __initdata nid_to_pxm_map[NR_NODES];
+extern int __initdata nid_to_pxm_map[MAX_NUMNODES];
 #endif
 
 #endif /*__KERNEL__*/

include/asm-ia64/mmzone.h

@@ -92,14 +92,12 @@
 extern unsigned long max_low_pfn;
 
 
-#ifdef CONFIG_IA64_DIG
+#if defined(CONFIG_IA64_DIG)
 
 /*
  * Platform definitions for DIG platform with contiguous memory.
  */
-#define MAX_PHYSNODE_ID	8	/* Maximum node number +1 */
-#define NR_NODES	8	/* Maximum number of nodes in SSI */
-
+#define MAX_PHYSNODE_ID	8		/* Maximum node number +1 */
 #define MAX_PHYS_MEMORY	(1UL << 40)	/* 1 TB */
 
 /*
@@ -119,37 +117,34 @@ extern unsigned long max_low_pfn;
 # error Unsupported bank and nodesize!
 #endif
 #define BANKSIZE		(1UL << BANKSHIFT)
-#define BANK_OFFSET(addr)	((unsigned long)(addr) & (BANKSIZE-1))
-#define NR_BANKS		(NR_BANKS_PER_NODE * NR_NODES)
-
-/*
- * VALID_MEM_KADDR returns a boolean to indicate if a kaddr is
- * potentially a valid cacheable identity mapped RAM memory address.
- * Note that the RAM may or may not actually be present!!
- */
-#define VALID_MEM_KADDR(kaddr)	1
-
-/*
- * Given a nodeid & a bank number, find the address of the mem_map
- * entry for the first page of the bank.
- */
-#define BANK_MEM_MAP_INDEX(kaddr) \
-	(((unsigned long)(kaddr) & (MAX_PHYS_MEMORY-1)) >> BANKSHIFT)
 
 #elif defined(CONFIG_IA64_SGI_SN2)
+
 /*
  * SGI SN2 discontig definitions
  */
 #define MAX_PHYSNODE_ID	2048	/* 2048 node ids (also called nasid) */
-#define NR_NODES	128	/* Maximum number of nodes in SSI */
 #define MAX_PHYS_MEMORY	(1UL << 49)
 
-#define BANKSHIFT		38
 #define NR_BANKS_PER_NODE	4
+#define BANKSHIFT		38
 #define SN2_NODE_SIZE		(64UL*1024*1024*1024)	/* 64GB per node */
 #define BANKSIZE		(SN2_NODE_SIZE/NR_BANKS_PER_NODE)
+
+#endif /* CONFIG_IA64_DIG */
+
+#if defined(CONFIG_IA64_DIG) || defined (CONFIG_IA64_SGI_SN2)
+/* Common defines for both platforms */
+#include <asm/numnodes.h>
 #define BANK_OFFSET(addr)	((unsigned long)(addr) & (BANKSIZE-1))
-#define NR_BANKS		(NR_BANKS_PER_NODE * NR_NODES)
+#define NR_BANKS		(NR_BANKS_PER_NODE * (1 << NODES_SHIFT))
+#define NR_MEMBLKS		(NR_BANKS)
+
+/*
+ * VALID_MEM_KADDR returns a boolean to indicate if a kaddr is
+ * potentially a valid cacheable identity mapped RAM memory address.
+ * Note that the RAM may or may not actually be present!!
+ */
 #define VALID_MEM_KADDR(kaddr)	1
 
 /*
@@ -159,5 +154,6 @@ extern unsigned long max_low_pfn;
 #define BANK_MEM_MAP_INDEX(kaddr) \
 	(((unsigned long)(kaddr) & (MAX_PHYS_MEMORY-1)) >> BANKSHIFT)
 
-#endif /* CONFIG_IA64_DIG */
+#endif /* CONFIG_IA64_DIG || CONFIG_IA64_SGI_SN2 */
+
 #endif /* _ASM_IA64_MMZONE_H */

include/asm-ia64/nodedata.h

@@ -14,7 +14,7 @@
 #define _ASM_IA64_NODEDATA_H
 
 
-#include <asm/mmzone.h>
+#include <linux/mmzone.h>
 
 /*
  * Node Data. One of these structures is located on each node of a NUMA system.
@@ -24,9 +24,9 @@ struct pglist_data;
 struct ia64_node_data {
 	short			active_cpu_count;
 	short			node;
-        struct pglist_data	*pg_data_ptrs[NR_NODES];
+        struct pglist_data	*pg_data_ptrs[MAX_NUMNODES];
 	struct page		*bank_mem_map_base[NR_BANKS];
-	struct ia64_node_data	*node_data_ptrs[NR_NODES];
+	struct ia64_node_data	*node_data_ptrs[MAX_NUMNODES];
 	short			node_id_map[NR_BANKS];
 };
 

include/asm-ia64/numa.h

@@ -16,17 +16,11 @@
 
 #ifdef CONFIG_NUMA
 
-#ifdef CONFIG_DISCONTIGMEM
 # include <asm/mmzone.h>
-# define NR_MEMBLKS   (NR_BANKS)
-#else
-# define NR_NODES     (8)
-# define NR_MEMBLKS   (NR_NODES * 8)
-#endif
 
 #include <linux/cache.h>
 extern volatile char cpu_to_node_map[NR_CPUS] __cacheline_aligned;
-extern volatile cpumask_t node_to_cpu_mask[NR_NODES] __cacheline_aligned;
+extern volatile cpumask_t node_to_cpu_mask[MAX_NUMNODES] __cacheline_aligned;
 
 /* Stuff below this line could be architecture independent */
 
@@ -60,7 +54,7 @@ extern struct node_cpuid_s node_cpuid[NR_CPUS];
  * proportional to the memory access latency ratios.
  */
 
-extern u8 numa_slit[NR_NODES * NR_NODES];
+extern u8 numa_slit[MAX_NUMNODES * MAX_NUMNODES];
 #define node_distance(from,to) (numa_slit[from * numnodes + to])
 
 extern int paddr_to_nid(unsigned long paddr);

include/asm-ia64/numnodes.h

 #ifndef _ASM_MAX_NUMNODES_H
 #define _ASM_MAX_NUMNODES_H
 
-#include <asm/mmzone.h>
-#define MAX_NUMNODES	NR_NODES
+#ifdef CONFIG_IA64_DIG
+/* Max 8 Nodes */
+#define NODES_SHIFT	3
+#elif defined(CONFIG_IA64_SGI_SN2)
+/* Max 128 Nodes */
+#define NODES_SHIFT	7
+#endif
 
 #endif /* _ASM_MAX_NUMNODES_H */

include/asm-ia64/sn/pda.h

@@ -10,6 +10,7 @@
 
 #include <linux/config.h>
 #include <linux/cache.h>
+#include <linux/mmzone.h>
 #include <asm/percpu.h>
 #include <asm/system.h>
 #include <asm/processor.h>
@@ -56,7 +57,7 @@ typedef struct pda_s {
 
 	unsigned long	sn_soft_irr[4];
 	unsigned long	sn_in_service_ivecs[4];
-	short		cnodeid_to_nasid_table[NR_NODES];	
+	short		cnodeid_to_nasid_table[MAX_NUMNODES];
 	int		sn_lb_int_war_ticks;
 	int		sn_last_irq;
 	int		sn_first_irq;