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Commit d610b54f authored by Jerome Brunet's avatar Jerome Brunet Committed by Neil Armstrong
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clk: meson: split divider and gate part of mpll 

The mpll clock is a kind of fractional divider which can gate.
When the RW operation have been added, enable/disable ops have been
mistakenly inserted in this driver. These ops are essentially a
poor copy/paste of the generic gate ops.

This change removes the gate ops from the mpll driver and inserts a
generic gate clock on each mpll divider, simplifying the mpll
driver and reducing code duplication.
Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
parent 722825dc
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Showing with 197 additions and 118 deletions
drivers/clk/meson/axg.c
View file @ d610b54f
...@@ -296,7 +296,7 @@ static struct clk_fixed_factor axg_fclk_div7 = { ...@@ -296,7 +296,7 @@ static struct clk_fixed_factor axg_fclk_div7 = {
}, },
}; };
static struct clk_regmap axg_mpll0 = { static struct clk_regmap axg_mpll0_div = {
.data = &(struct meson_clk_mpll_data){ .data = &(struct meson_clk_mpll_data){
.sdm = { .sdm = {
.reg_off = HHI_MPLL_CNTL7, .reg_off = HHI_MPLL_CNTL7,
...@@ -313,11 +313,6 @@ static struct clk_regmap axg_mpll0 = { ...@@ -313,11 +313,6 @@ static struct clk_regmap axg_mpll0 = {
.shift = 16, .shift = 16,
.width = 9, .width = 9,
}, },
.en = {
.reg_off = HHI_MPLL_CNTL7,
.shift = 14,
.width = 1,
},
.ssen = { .ssen = {
.reg_off = HHI_MPLL_CNTL, .reg_off = HHI_MPLL_CNTL,
.shift = 25, .shift = 25,
...@@ -331,14 +326,28 @@ static struct clk_regmap axg_mpll0 = { ...@@ -331,14 +326,28 @@ static struct clk_regmap axg_mpll0 = {
.lock = &meson_clk_lock, .lock = &meson_clk_lock,
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll0", .name = "mpll0_div",
.ops = &meson_clk_mpll_ops, .ops = &meson_clk_mpll_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1, .num_parents = 1,
}, },
}; };
static struct clk_regmap axg_mpll1 = { static struct clk_regmap axg_mpll0 = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_MPLL_CNTL7,
.bit_idx = 14,
},
.hw.init = &(struct clk_init_data){
.name = "mpll0",
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpll0_div" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap axg_mpll1_div = {
.data = &(struct meson_clk_mpll_data){ .data = &(struct meson_clk_mpll_data){
.sdm = { .sdm = {
.reg_off = HHI_MPLL_CNTL8, .reg_off = HHI_MPLL_CNTL8,
...@@ -355,11 +364,6 @@ static struct clk_regmap axg_mpll1 = { ...@@ -355,11 +364,6 @@ static struct clk_regmap axg_mpll1 = {
.shift = 16, .shift = 16,
.width = 9, .width = 9,
}, },
.en = {
.reg_off = HHI_MPLL_CNTL8,
.shift = 14,
.width = 1,
},
.misc = { .misc = {
.reg_off = HHI_PLL_TOP_MISC, .reg_off = HHI_PLL_TOP_MISC,
.shift = 1, .shift = 1,
...@@ -368,14 +372,28 @@ static struct clk_regmap axg_mpll1 = { ...@@ -368,14 +372,28 @@ static struct clk_regmap axg_mpll1 = {
.lock = &meson_clk_lock, .lock = &meson_clk_lock,
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll1", .name = "mpll1_div",
.ops = &meson_clk_mpll_ops, .ops = &meson_clk_mpll_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1, .num_parents = 1,
}, },
}; };
static struct clk_regmap axg_mpll2 = { static struct clk_regmap axg_mpll1 = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_MPLL_CNTL8,
.bit_idx = 14,
},
.hw.init = &(struct clk_init_data){
.name = "mpll1",
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpll1_div" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap axg_mpll2_div = {
.data = &(struct meson_clk_mpll_data){ .data = &(struct meson_clk_mpll_data){
.sdm = { .sdm = {
.reg_off = HHI_MPLL_CNTL9, .reg_off = HHI_MPLL_CNTL9,
...@@ -392,11 +410,6 @@ static struct clk_regmap axg_mpll2 = { ...@@ -392,11 +410,6 @@ static struct clk_regmap axg_mpll2 = {
.shift = 16, .shift = 16,
.width = 9, .width = 9,
}, },
.en = {
.reg_off = HHI_MPLL_CNTL9,
.shift = 14,
.width = 1,
},
.misc = { .misc = {
.reg_off = HHI_PLL_TOP_MISC, .reg_off = HHI_PLL_TOP_MISC,
.shift = 2, .shift = 2,
...@@ -405,14 +418,28 @@ static struct clk_regmap axg_mpll2 = { ...@@ -405,14 +418,28 @@ static struct clk_regmap axg_mpll2 = {
.lock = &meson_clk_lock, .lock = &meson_clk_lock,
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll2", .name = "mpll2_div",
.ops = &meson_clk_mpll_ops, .ops = &meson_clk_mpll_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1, .num_parents = 1,
}, },
}; };
static struct clk_regmap axg_mpll3 = { static struct clk_regmap axg_mpll2 = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_MPLL_CNTL9,
.bit_idx = 14,
},
.hw.init = &(struct clk_init_data){
.name = "mpll2",
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpll2_div" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap axg_mpll3_div = {
.data = &(struct meson_clk_mpll_data){ .data = &(struct meson_clk_mpll_data){
.sdm = { .sdm = {
.reg_off = HHI_MPLL3_CNTL0, .reg_off = HHI_MPLL3_CNTL0,
...@@ -429,11 +456,6 @@ static struct clk_regmap axg_mpll3 = { ...@@ -429,11 +456,6 @@ static struct clk_regmap axg_mpll3 = {
.shift = 2, .shift = 2,
.width = 9, .width = 9,
}, },
.en = {
.reg_off = HHI_MPLL3_CNTL0,
.shift = 0,
.width = 1,
},
.misc = { .misc = {
.reg_off = HHI_PLL_TOP_MISC, .reg_off = HHI_PLL_TOP_MISC,
.shift = 3, .shift = 3,
...@@ -442,13 +464,27 @@ static struct clk_regmap axg_mpll3 = { ...@@ -442,13 +464,27 @@ static struct clk_regmap axg_mpll3 = {
.lock = &meson_clk_lock, .lock = &meson_clk_lock,
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll3", .name = "mpll3_div",
.ops = &meson_clk_mpll_ops, .ops = &meson_clk_mpll_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1, .num_parents = 1,
}, },
}; };
static struct clk_regmap axg_mpll3 = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_MPLL3_CNTL0,
.bit_idx = 0,
},
.hw.init = &(struct clk_init_data){
.name = "mpll3",
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpll3_div" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
static const char * const clk81_parent_names[] = { static const char * const clk81_parent_names[] = {
"xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
...@@ -722,6 +758,10 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = { ...@@ -722,6 +758,10 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = {
[CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw, [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw,
[CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw, [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw,
[CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw, [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw,
[CLKID_MPLL0_DIV] = &axg_mpll0_div.hw,
[CLKID_MPLL1_DIV] = &axg_mpll1_div.hw,
[CLKID_MPLL2_DIV] = &axg_mpll2_div.hw,
[CLKID_MPLL3_DIV] = &axg_mpll3_div.hw,
[NR_CLKS] = NULL, [NR_CLKS] = NULL,
}, },
.num = NR_CLKS, .num = NR_CLKS,
...@@ -786,6 +826,10 @@ static struct clk_regmap *const axg_clk_regmaps[] = { ...@@ -786,6 +826,10 @@ static struct clk_regmap *const axg_clk_regmaps[] = {
&axg_mpll1, &axg_mpll1,
&axg_mpll2, &axg_mpll2,
&axg_mpll3, &axg_mpll3,
&axg_mpll0_div,
&axg_mpll1_div,
&axg_mpll2_div,
&axg_mpll3_div,
&axg_fixed_pll, &axg_fixed_pll,
&axg_sys_pll, &axg_sys_pll,
&axg_gp0_pll, &axg_gp0_pll,
......
drivers/clk/meson/axg.h
View file @ d610b54f
...@@ -117,8 +117,12 @@ ...@@ -117,8 +117,12 @@
#define CLKID_SD_EMMC_B_CLK0_DIV 62 #define CLKID_SD_EMMC_B_CLK0_DIV 62
#define CLKID_SD_EMMC_C_CLK0_SEL 63 #define CLKID_SD_EMMC_C_CLK0_SEL 63
#define CLKID_SD_EMMC_C_CLK0_DIV 64 #define CLKID_SD_EMMC_C_CLK0_DIV 64
#define CLKID_MPLL0_DIV 65
#define CLKID_MPLL1_DIV 66
#define CLKID_MPLL2_DIV 67
#define CLKID_MPLL3_DIV 68
#define NR_CLKS 65 #define NR_CLKS 69
/* include the CLKIDs that have been made part of the DT binding */ /* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/axg-clkc.h> #include <dt-bindings/clock/axg-clkc.h>
......
drivers/clk/meson/clk-mpll.c
View file @ d610b54f
...@@ -170,57 +170,13 @@ static int mpll_set_rate(struct clk_hw *hw, ...@@ -170,57 +170,13 @@ static int mpll_set_rate(struct clk_hw *hw,
return 0; return 0;
} }
static void mpll_enable_core(struct clk_hw *hw, int enable)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);
unsigned long flags = 0;
if (mpll->lock)
spin_lock_irqsave(mpll->lock, flags);
else
__acquire(mpll->lock);
meson_parm_write(clk->map, &mpll->en, enable ? 1 : 0);
if (mpll->lock)
spin_unlock_irqrestore(mpll->lock, flags);
else
__release(mpll->lock);
}
static int mpll_enable(struct clk_hw *hw)
{
mpll_enable_core(hw, 1);
return 0;
}
static void mpll_disable(struct clk_hw *hw)
{
mpll_enable_core(hw, 0);
}
static int mpll_is_enabled(struct clk_hw *hw)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);
return meson_parm_read(clk->map, &mpll->en);
}
const struct clk_ops meson_clk_mpll_ro_ops = { const struct clk_ops meson_clk_mpll_ro_ops = {
.recalc_rate = mpll_recalc_rate, .recalc_rate = mpll_recalc_rate,
.round_rate = mpll_round_rate, .round_rate = mpll_round_rate,
.is_enabled = mpll_is_enabled,
}; };
const struct clk_ops meson_clk_mpll_ops = { const struct clk_ops meson_clk_mpll_ops = {
.recalc_rate = mpll_recalc_rate, .recalc_rate = mpll_recalc_rate,
.round_rate = mpll_round_rate, .round_rate = mpll_round_rate,
.set_rate = mpll_set_rate, .set_rate = mpll_set_rate,
.enable = mpll_enable,
.disable = mpll_disable,
.is_enabled = mpll_is_enabled,
}; };
drivers/clk/meson/clkc.h
View file @ d610b54f
...@@ -116,7 +116,6 @@ struct meson_clk_mpll_data { ...@@ -116,7 +116,6 @@ struct meson_clk_mpll_data {
struct parm sdm; struct parm sdm;
struct parm sdm_en; struct parm sdm_en;
struct parm n2; struct parm n2;
struct parm en;
struct parm ssen; struct parm ssen;
struct parm misc; struct parm misc;
spinlock_t *lock; spinlock_t *lock;
......
drivers/clk/meson/gxbb.c
View file @ d610b54f
...@@ -540,7 +540,7 @@ static struct clk_fixed_factor gxbb_fclk_div7 = { ...@@ -540,7 +540,7 @@ static struct clk_fixed_factor gxbb_fclk_div7 = {
}, },
}; };
static struct clk_regmap gxbb_mpll0 = { static struct clk_regmap gxbb_mpll0_div = {
.data = &(struct meson_clk_mpll_data){ .data = &(struct meson_clk_mpll_data){
.sdm = { .sdm = {
.reg_off = HHI_MPLL_CNTL7, .reg_off = HHI_MPLL_CNTL7,
...@@ -557,11 +557,6 @@ static struct clk_regmap gxbb_mpll0 = { ...@@ -557,11 +557,6 @@ static struct clk_regmap gxbb_mpll0 = {
.shift = 16, .shift = 16,
.width = 9, .width = 9,
}, },
.en = {
.reg_off = HHI_MPLL_CNTL7,
.shift = 14,
.width = 1,
},
.ssen = { .ssen = {
.reg_off = HHI_MPLL_CNTL, .reg_off = HHI_MPLL_CNTL,
.shift = 25, .shift = 25,
...@@ -570,14 +565,28 @@ static struct clk_regmap gxbb_mpll0 = { ...@@ -570,14 +565,28 @@ static struct clk_regmap gxbb_mpll0 = {
.lock = &meson_clk_lock, .lock = &meson_clk_lock,
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll0", .name = "mpll0_div",
.ops = &meson_clk_mpll_ops, .ops = &meson_clk_mpll_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1, .num_parents = 1,
}, },
}; };
static struct clk_regmap gxbb_mpll1 = { static struct clk_regmap gxbb_mpll0 = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_MPLL_CNTL7,
.bit_idx = 14,
},
.hw.init = &(struct clk_init_data){
.name = "mpll0",
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpll0_div" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap gxbb_mpll1_div = {
.data = &(struct meson_clk_mpll_data){ .data = &(struct meson_clk_mpll_data){
.sdm = { .sdm = {
.reg_off = HHI_MPLL_CNTL8, .reg_off = HHI_MPLL_CNTL8,
...@@ -594,22 +603,31 @@ static struct clk_regmap gxbb_mpll1 = { ...@@ -594,22 +603,31 @@ static struct clk_regmap gxbb_mpll1 = {
.shift = 16, .shift = 16,
.width = 9, .width = 9,
}, },
.en = {
.reg_off = HHI_MPLL_CNTL8,
.shift = 14,
.width = 1,
},
.lock = &meson_clk_lock, .lock = &meson_clk_lock,
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll1", .name = "mpll1_div",
.ops = &meson_clk_mpll_ops, .ops = &meson_clk_mpll_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1, .num_parents = 1,
}, },
}; };
static struct clk_regmap gxbb_mpll2 = { static struct clk_regmap gxbb_mpll1 = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_MPLL_CNTL8,
.bit_idx = 14,
},
.hw.init = &(struct clk_init_data){
.name = "mpll1",
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpll1_div" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap gxbb_mpll2_div = {
.data = &(struct meson_clk_mpll_data){ .data = &(struct meson_clk_mpll_data){
.sdm = { .sdm = {
.reg_off = HHI_MPLL_CNTL9, .reg_off = HHI_MPLL_CNTL9,
...@@ -626,21 +644,30 @@ static struct clk_regmap gxbb_mpll2 = { ...@@ -626,21 +644,30 @@ static struct clk_regmap gxbb_mpll2 = {
.shift = 16, .shift = 16,
.width = 9, .width = 9,
}, },
.en = {
.reg_off = HHI_MPLL_CNTL9,
.shift = 14,
.width = 1,
},
.lock = &meson_clk_lock, .lock = &meson_clk_lock,
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll2", .name = "mpll2_div",
.ops = &meson_clk_mpll_ops, .ops = &meson_clk_mpll_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1, .num_parents = 1,
}, },
}; };
static struct clk_regmap gxbb_mpll2 = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_MPLL_CNTL9,
.bit_idx = 14,
},
.hw.init = &(struct clk_init_data){
.name = "mpll2",
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpll2_div" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
static const char * const clk81_parent_names[] = { static const char * const clk81_parent_names[] = {
"xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
...@@ -1668,6 +1695,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = { ...@@ -1668,6 +1695,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
[CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
[CLKID_VAPB] = &gxbb_vapb.hw, [CLKID_VAPB] = &gxbb_vapb.hw,
[CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw, [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw,
[CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
[CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
[CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
[NR_CLKS] = NULL, [NR_CLKS] = NULL,
}, },
.num = NR_CLKS, .num = NR_CLKS,
...@@ -1815,6 +1845,9 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = { ...@@ -1815,6 +1845,9 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
[CLKID_VAPB_1] = &gxbb_vapb_1.hw, [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
[CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
[CLKID_VAPB] = &gxbb_vapb.hw, [CLKID_VAPB] = &gxbb_vapb.hw,
[CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
[CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
[CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
[NR_CLKS] = NULL, [NR_CLKS] = NULL,
}, },
.num = NR_CLKS, .num = NR_CLKS,
...@@ -1961,6 +1994,9 @@ static struct clk_regmap *const gx_clk_regmaps[] = { ...@@ -1961,6 +1994,9 @@ static struct clk_regmap *const gx_clk_regmaps[] = {
&gxbb_mpll0, &gxbb_mpll0,
&gxbb_mpll1, &gxbb_mpll1,
&gxbb_mpll2, &gxbb_mpll2,
&gxbb_mpll0_div,
&gxbb_mpll1_div,
&gxbb_mpll2_div,
&gxbb_cts_amclk_div, &gxbb_cts_amclk_div,
&gxbb_fixed_pll, &gxbb_fixed_pll,
&gxbb_sys_pll, &gxbb_sys_pll,
......
drivers/clk/meson/gxbb.h
View file @ d610b54f
...@@ -195,8 +195,11 @@ ...@@ -195,8 +195,11 @@
#define CLKID_VAPB_0_DIV 134 #define CLKID_VAPB_0_DIV 134
#define CLKID_VAPB_1_DIV 137 #define CLKID_VAPB_1_DIV 137
#define CLKID_HDMI_PLL_PRE_MULT 141 #define CLKID_HDMI_PLL_PRE_MULT 141
#define CLKID_MPLL0_DIV 142
#define CLKID_MPLL1_DIV 143
#define CLKID_MPLL2_DIV 144
#define NR_CLKS 142 #define NR_CLKS 145
/* include the CLKIDs that have been made part of the DT binding */ /* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/gxbb-clkc.h> #include <dt-bindings/clock/gxbb-clkc.h>
......
drivers/clk/meson/meson8b.c
View file @ d610b54f
...@@ -289,7 +289,7 @@ static struct clk_fixed_factor meson8b_fclk_div7 = { ...@@ -289,7 +289,7 @@ static struct clk_fixed_factor meson8b_fclk_div7 = {
}, },
}; };
static struct clk_regmap meson8b_mpll0 = { static struct clk_regmap meson8b_mpll0_div = {
.data = &(struct meson_clk_mpll_data){ .data = &(struct meson_clk_mpll_data){
.sdm = { .sdm = {
.reg_off = HHI_MPLL_CNTL7, .reg_off = HHI_MPLL_CNTL7,
...@@ -306,11 +306,6 @@ static struct clk_regmap meson8b_mpll0 = { ...@@ -306,11 +306,6 @@ static struct clk_regmap meson8b_mpll0 = {
.shift = 16, .shift = 16,
.width = 9, .width = 9,
}, },
.en = {
.reg_off = HHI_MPLL_CNTL7,
.shift = 14,
.width = 1,
},
.ssen = { .ssen = {
.reg_off = HHI_MPLL_CNTL, .reg_off = HHI_MPLL_CNTL,
.shift = 25, .shift = 25,
...@@ -319,14 +314,28 @@ static struct clk_regmap meson8b_mpll0 = { ...@@ -319,14 +314,28 @@ static struct clk_regmap meson8b_mpll0 = {
.lock = &meson_clk_lock, .lock = &meson_clk_lock,
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll0", .name = "mpll0_div",
.ops = &meson_clk_mpll_ops, .ops = &meson_clk_mpll_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1, .num_parents = 1,
}, },
}; };
static struct clk_regmap meson8b_mpll1 = { static struct clk_regmap meson8b_mpll0 = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_MPLL_CNTL7,
.bit_idx = 14,
},
.hw.init = &(struct clk_init_data){
.name = "mpll0",
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpll0_div" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap meson8b_mpll1_div = {
.data = &(struct meson_clk_mpll_data){ .data = &(struct meson_clk_mpll_data){
.sdm = { .sdm = {
.reg_off = HHI_MPLL_CNTL8, .reg_off = HHI_MPLL_CNTL8,
...@@ -343,22 +352,31 @@ static struct clk_regmap meson8b_mpll1 = { ...@@ -343,22 +352,31 @@ static struct clk_regmap meson8b_mpll1 = {
.shift = 16, .shift = 16,
.width = 9, .width = 9,
}, },
.en = {
.reg_off = HHI_MPLL_CNTL8,
.shift = 14,
.width = 1,
},
.lock = &meson_clk_lock, .lock = &meson_clk_lock,
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll1", .name = "mpll1_div",
.ops = &meson_clk_mpll_ops, .ops = &meson_clk_mpll_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1, .num_parents = 1,
}, },
}; };
static struct clk_regmap meson8b_mpll2 = { static struct clk_regmap meson8b_mpll1 = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_MPLL_CNTL8,
.bit_idx = 14,
},
.hw.init = &(struct clk_init_data){
.name = "mpll1",
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpll1_div" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap meson8b_mpll2_div = {
.data = &(struct meson_clk_mpll_data){ .data = &(struct meson_clk_mpll_data){
.sdm = { .sdm = {
.reg_off = HHI_MPLL_CNTL9, .reg_off = HHI_MPLL_CNTL9,
...@@ -375,21 +393,30 @@ static struct clk_regmap meson8b_mpll2 = { ...@@ -375,21 +393,30 @@ static struct clk_regmap meson8b_mpll2 = {
.shift = 16, .shift = 16,
.width = 9, .width = 9,
}, },
.en = {
.reg_off = HHI_MPLL_CNTL9,
.shift = 14,
.width = 1,
},
.lock = &meson_clk_lock, .lock = &meson_clk_lock,
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "mpll2", .name = "mpll2_div",
.ops = &meson_clk_mpll_ops, .ops = &meson_clk_mpll_ops,
.parent_names = (const char *[]){ "fixed_pll" }, .parent_names = (const char *[]){ "fixed_pll" },
.num_parents = 1, .num_parents = 1,
}, },
}; };
static struct clk_regmap meson8b_mpll2 = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_MPLL_CNTL9,
.bit_idx = 14,
},
.hw.init = &(struct clk_init_data){
.name = "mpll2",
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpll2_div" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
/* /*
* FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL * FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL
* post-dividers and should be modeled with their respective PLLs via the * post-dividers and should be modeled with their respective PLLs via the
...@@ -640,6 +667,9 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = { ...@@ -640,6 +667,9 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
[CLKID_MPLL0] = &meson8b_mpll0.hw, [CLKID_MPLL0] = &meson8b_mpll0.hw,
[CLKID_MPLL1] = &meson8b_mpll1.hw, [CLKID_MPLL1] = &meson8b_mpll1.hw,
[CLKID_MPLL2] = &meson8b_mpll2.hw, [CLKID_MPLL2] = &meson8b_mpll2.hw,
[CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
[CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
[CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
[CLK_NR_CLKS] = NULL, [CLK_NR_CLKS] = NULL,
}, },
.num = CLK_NR_CLKS, .num = CLK_NR_CLKS,
...@@ -729,6 +759,9 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = { ...@@ -729,6 +759,9 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
&meson8b_mpll0, &meson8b_mpll0,
&meson8b_mpll1, &meson8b_mpll1,
&meson8b_mpll2, &meson8b_mpll2,
&meson8b_mpll0_div,
&meson8b_mpll1_div,
&meson8b_mpll2_div,
&meson8b_fixed_pll, &meson8b_fixed_pll,
&meson8b_vid_pll, &meson8b_vid_pll,
&meson8b_sys_pll, &meson8b_sys_pll,
......
drivers/clk/meson/meson8b.h
View file @ d610b54f
...@@ -69,7 +69,11 @@ ...@@ -69,7 +69,11 @@
* will remain defined here. * will remain defined here.
*/ */
#define CLK_NR_CLKS 96 #define CLKID_MPLL0_DIV 96
#define CLKID_MPLL1_DIV 97
#define CLKID_MPLL2_DIV 98
#define CLK_NR_CLKS 99
/* /*
* include the CLKID and RESETID that have * include the CLKID and RESETID that have
......
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