Commit d633becc authored by Shawn Lin's avatar Shawn Lin Committed by Heiko Stuebner

arm64: dts: rockchip: extent bus-ranges of PCIe for rk3399

In order to support multiple hierarchy of PCIe buses,
for instance, PCIe switch, we need to extent bus-ranges
to as max as possible. We have 32 regions and could support
up to 31 buses except bus 0 for our root bridge.
Signed-off-by: default avatarShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent b74a2e98
...@@ -220,7 +220,7 @@ pcie0: pcie@f8000000 { ...@@ -220,7 +220,7 @@ pcie0: pcie@f8000000 {
#size-cells = <2>; #size-cells = <2>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
aspm-no-l0s; aspm-no-l0s;
bus-range = <0x0 0x1>; bus-range = <0x0 0x1f>;
clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
clock-names = "aclk", "aclk-perf", clock-names = "aclk", "aclk-perf",
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment