Commit d6cae2bc authored by Sergey Ryazanov's avatar Sergey Ryazanov Committed by Kalle Valo

ath9k: fix AR9002 ADC and NF calibrations

ADC calibration is only required for a 80 MHz sampling rate (i.e. for
40 MHz channels), when the chip utilizes the pair of ADCs in interleved
mode. Calibration on a 20 MHz channel will never be completed.

Previous channel check is trying to exclude all channels where the
calibration will get stuck. It effectively blocks the calibration run
for HT20 channels, but fails to exclude 20 MHz channels without HT (e.g.
legacy mode channels).

Fix this issue by reworking the channel check to explicitly allow ADCs
gain & DC offset calibrations for HT40 channels only. Also update the
complicated comment to make it clear that these calibrations are for
multi-ADC mode only.

Stuck ADCs calibration blocks the NF calibration, what could make it
impossible to work in a noisy evironment: too big Rx attentuation,
invalid RSSI value, etc. So this change is actually more of a NF
calibration fix rather then the ADC calibration fix.

Run tested with AR9220.
Signed-off-by: default avatarSergey Ryazanov <ryazanov.s.a@gmail.com>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20200424004923.17129-2-ryazanov.s.a@gmail.com
parent 59a022cc
...@@ -37,9 +37,8 @@ static bool ar9002_hw_is_cal_supported(struct ath_hw *ah, ...@@ -37,9 +37,8 @@ static bool ar9002_hw_is_cal_supported(struct ath_hw *ah,
break; break;
case ADC_GAIN_CAL: case ADC_GAIN_CAL:
case ADC_DC_CAL: case ADC_DC_CAL:
/* Run ADC Gain Cal for non-CCK & non 2GHz-HT20 only */ /* Run even/odd ADCs calibrations for HT40 channels only */
if (!((IS_CHAN_2GHZ(chan) || IS_CHAN_A_FAST_CLOCK(ah, chan)) && if (IS_CHAN_HT40(chan))
IS_CHAN_HT20(chan)))
supported = true; supported = true;
break; break;
} }
......
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