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Commit da72a66b authored by Linus Walleij's avatar Linus Walleij
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ARM: integrator: get rid of preallocated irq descriptors 

The Integrators were using the .nr_irqs field of the machine
descriptor to pre-allocate a number of descriptors at boot. This
is not right: the irq chip implementations should allocate
their descriptors themselves, and as a result the simple
irqdomain code warns about it.

Get rid of this by just deleting the .nr_irq field from the
machine descriptors but take care: doing so makes the default
implementation hog the first 16 IRQ numbers, so these cannot
be used by the still static IRQ number assignments in the
ATAG boot case. So for these, bump the IRQ numbers to begin
at 64 and upward.

Introduce an offset to offset all IRQ numbers if need be,
though we don't expect to do that again as device tree comes
along.
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 3a6ca8c5
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Showing with 55 additions and 60 deletions
arch/arm/mach-integrator/include/mach/irqs.h
View file @ da72a66b
...@@ -19,64 +19,63 @@ ...@@ -19,64 +19,63 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/ */
/* /*
* Interrupt numbers * Interrupt numbers, all of the above are just static reservations
* used so they can be encoded into device resources. They will finally
* be done away with when switching to device tree.
*/ */
#define IRQ_PIC_START 1 #define IRQ_PIC_START 64
#define IRQ_SOFTINT 1 #define IRQ_SOFTINT (IRQ_PIC_START+0)
#define IRQ_UARTINT0 2 #define IRQ_UARTINT0 (IRQ_PIC_START+1)
#define IRQ_UARTINT1 3 #define IRQ_UARTINT1 (IRQ_PIC_START+2)
#define IRQ_KMIINT0 4 #define IRQ_KMIINT0 (IRQ_PIC_START+3)
#define IRQ_KMIINT1 5 #define IRQ_KMIINT1 (IRQ_PIC_START+4)
#define IRQ_TIMERINT0 6 #define IRQ_TIMERINT0 (IRQ_PIC_START+5)
#define IRQ_TIMERINT1 7 #define IRQ_TIMERINT1 (IRQ_PIC_START+6)
#define IRQ_TIMERINT2 8 #define IRQ_TIMERINT2 (IRQ_PIC_START+7)
#define IRQ_RTCINT 9 #define IRQ_RTCINT (IRQ_PIC_START+8)
#define IRQ_AP_EXPINT0 10 #define IRQ_AP_EXPINT0 (IRQ_PIC_START+9)
#define IRQ_AP_EXPINT1 11 #define IRQ_AP_EXPINT1 (IRQ_PIC_START+10)
#define IRQ_AP_EXPINT2 12 #define IRQ_AP_EXPINT2 (IRQ_PIC_START+11)
#define IRQ_AP_EXPINT3 13 #define IRQ_AP_EXPINT3 (IRQ_PIC_START+12)
#define IRQ_AP_PCIINT0 14 #define IRQ_AP_PCIINT0 (IRQ_PIC_START+13)
#define IRQ_AP_PCIINT1 15 #define IRQ_AP_PCIINT1 (IRQ_PIC_START+14)
#define IRQ_AP_PCIINT2 16 #define IRQ_AP_PCIINT2 (IRQ_PIC_START+15)
#define IRQ_AP_PCIINT3 17 #define IRQ_AP_PCIINT3 (IRQ_PIC_START+16)
#define IRQ_AP_V3INT 18 #define IRQ_AP_V3INT (IRQ_PIC_START+17)
#define IRQ_AP_CPINT0 19 #define IRQ_AP_CPINT0 (IRQ_PIC_START+18)
#define IRQ_AP_CPINT1 20 #define IRQ_AP_CPINT1 (IRQ_PIC_START+19)
#define IRQ_AP_LBUSTIMEOUT 21 #define IRQ_AP_LBUSTIMEOUT (IRQ_PIC_START+20)
#define IRQ_AP_APCINT 22 #define IRQ_AP_APCINT (IRQ_PIC_START+21)
#define IRQ_CP_CLCDCINT 23 #define IRQ_CP_CLCDCINT (IRQ_PIC_START+22)
#define IRQ_CP_MMCIINT0 24 #define IRQ_CP_MMCIINT0 (IRQ_PIC_START+23)
#define IRQ_CP_MMCIINT1 25 #define IRQ_CP_MMCIINT1 (IRQ_PIC_START+24)
#define IRQ_CP_AACIINT 26 #define IRQ_CP_AACIINT (IRQ_PIC_START+25)
#define IRQ_CP_CPPLDINT 27 #define IRQ_CP_CPPLDINT (IRQ_PIC_START+26)
#define IRQ_CP_ETHINT 28 #define IRQ_CP_ETHINT (IRQ_PIC_START+27)
#define IRQ_CP_TSPENINT 29 #define IRQ_CP_TSPENINT (IRQ_PIC_START+28)
#define IRQ_PIC_END 29 #define IRQ_PIC_END (IRQ_PIC_START+28)
#define IRQ_CIC_START 32 #define IRQ_CIC_START (IRQ_PIC_END+1)
#define IRQ_CM_SOFTINT 32 #define IRQ_CM_SOFTINT (IRQ_CIC_START+0)
#define IRQ_CM_COMMRX 33 #define IRQ_CM_COMMRX (IRQ_CIC_START+1)
#define IRQ_CM_COMMTX 34 #define IRQ_CM_COMMTX (IRQ_CIC_START+2)
#define IRQ_CIC_END 34 #define IRQ_CIC_END (IRQ_CIC_START+2)
/* /*
* IntegratorCP only * IntegratorCP only
*/ */
#define IRQ_SIC_START 35 #define IRQ_SIC_START (IRQ_CIC_END+1)
#define IRQ_SIC_CP_SOFTINT 35 #define IRQ_SIC_CP_SOFTINT (IRQ_SIC_START+0)
#define IRQ_SIC_CP_RI0 36 #define IRQ_SIC_CP_RI0 (IRQ_SIC_START+1)
#define IRQ_SIC_CP_RI1 37 #define IRQ_SIC_CP_RI1 (IRQ_SIC_START+2)
#define IRQ_SIC_CP_CARDIN 38 #define IRQ_SIC_CP_CARDIN (IRQ_SIC_START+3)
#define IRQ_SIC_CP_LMINT0 39 #define IRQ_SIC_CP_LMINT0 (IRQ_SIC_START+4)
#define IRQ_SIC_CP_LMINT1 40 #define IRQ_SIC_CP_LMINT1 (IRQ_SIC_START+5)
#define IRQ_SIC_CP_LMINT2 41 #define IRQ_SIC_CP_LMINT2 (IRQ_SIC_START+6)
#define IRQ_SIC_CP_LMINT3 42 #define IRQ_SIC_CP_LMINT3 (IRQ_SIC_START+7)
#define IRQ_SIC_CP_LMINT4 43 #define IRQ_SIC_CP_LMINT4 (IRQ_SIC_START+8)
#define IRQ_SIC_CP_LMINT5 44 #define IRQ_SIC_CP_LMINT5 (IRQ_SIC_START+9)
#define IRQ_SIC_CP_LMINT6 45 #define IRQ_SIC_CP_LMINT6 (IRQ_SIC_START+10)
#define IRQ_SIC_CP_LMINT7 46 #define IRQ_SIC_CP_LMINT7 (IRQ_SIC_START+11)
#define IRQ_SIC_END 46 #define IRQ_SIC_END (IRQ_SIC_START+11)
#define NR_IRQS_INTEGRATOR_AP 34
#define NR_IRQS_INTEGRATOR_CP 47
arch/arm/mach-integrator/integrator_ap.c
View file @ da72a66b
...@@ -499,7 +499,6 @@ static const char * ap_dt_board_compat[] = { ...@@ -499,7 +499,6 @@ static const char * ap_dt_board_compat[] = {
DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)") DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
.reserve = integrator_reserve, .reserve = integrator_reserve,
.map_io = ap_map_io, .map_io = ap_map_io,
.nr_irqs = NR_IRQS_INTEGRATOR_AP,
.init_early = ap_init_early, .init_early = ap_init_early,
.init_irq = ap_init_irq_of, .init_irq = ap_init_irq_of,
.handle_irq = fpga_handle_irq, .handle_irq = fpga_handle_irq,
...@@ -609,7 +608,6 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator") ...@@ -609,7 +608,6 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator")
.atag_offset = 0x100, .atag_offset = 0x100,
.reserve = integrator_reserve, .reserve = integrator_reserve,
.map_io = ap_map_io, .map_io = ap_map_io,
.nr_irqs = NR_IRQS_INTEGRATOR_AP,
.init_early = ap_init_early, .init_early = ap_init_early,
.init_irq = ap_init_irq, .init_irq = ap_init_irq,
.handle_irq = fpga_handle_irq, .handle_irq = fpga_handle_irq,
......
arch/arm/mach-integrator/integrator_cp.c
View file @ da72a66b
...@@ -350,7 +350,6 @@ static const char * intcp_dt_board_compat[] = { ...@@ -350,7 +350,6 @@ static const char * intcp_dt_board_compat[] = {
DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)") DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
.reserve = integrator_reserve, .reserve = integrator_reserve,
.map_io = intcp_map_io, .map_io = intcp_map_io,
.nr_irqs = NR_IRQS_INTEGRATOR_CP,
.init_early = intcp_init_early, .init_early = intcp_init_early,
.init_irq = intcp_init_irq_of, .init_irq = intcp_init_irq_of,
.handle_irq = fpga_handle_irq, .handle_irq = fpga_handle_irq,
...@@ -423,7 +422,7 @@ static void __init intcp_init_irq(void) ...@@ -423,7 +422,7 @@ static void __init intcp_init_irq(void)
u32 pic_mask, cic_mask, sic_mask; u32 pic_mask, cic_mask, sic_mask;
/* These masks are for the HW IRQ registers */ /* These masks are for the HW IRQ registers */
pic_mask = ~((~0u) << (11 - IRQ_PIC_START)); pic_mask = ~((~0u) << (11 - 0));
pic_mask |= (~((~0u) << (29 - 22))) << 22; pic_mask |= (~((~0u) << (29 - 22))) << 22;
cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START)); cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START)); sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
...@@ -504,7 +503,6 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP") ...@@ -504,7 +503,6 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
.atag_offset = 0x100, .atag_offset = 0x100,
.reserve = integrator_reserve, .reserve = integrator_reserve,
.map_io = intcp_map_io, .map_io = intcp_map_io,
.nr_irqs = NR_IRQS_INTEGRATOR_CP,
.init_early = intcp_init_early, .init_early = intcp_init_early,
.init_irq = intcp_init_irq, .init_irq = intcp_init_irq,
.handle_irq = fpga_handle_irq, .handle_irq = fpga_handle_irq,
......
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