Commit dad3cfbd authored by Russell King's avatar Russell King

[SERIAL] Convert TI16C750 flow control into a port capability.

Add UART_CAP_AFE, and use this to enable TI16C750 flow control,
but only if we have 32 bytes or more of FIFO.
parent ed6eb421
...@@ -210,7 +210,7 @@ static const struct serial8250_config uart_config[] = { ...@@ -210,7 +210,7 @@ static const struct serial8250_config uart_config[] = {
.tx_loadsz = 64, .tx_loadsz = 64,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
UART_FCR7_64BYTE, UART_FCR7_64BYTE,
.flags = UART_CAP_FIFO | UART_CAP_SLEEP, .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
}, },
[PORT_STARTECH] = { [PORT_STARTECH] = {
.name = "Startech", .name = "Startech",
...@@ -1584,11 +1584,14 @@ serial8250_set_termios(struct uart_port *port, struct termios *termios, ...@@ -1584,11 +1584,14 @@ serial8250_set_termios(struct uart_port *port, struct termios *termios,
} }
/* /*
* TI16C750: hardware flow control and 64 byte FIFOs. When AFE is * MCR-based auto flow control. When AFE is enabled, RTS will be
* enabled, RTS will be deasserted when the receive FIFO contains * deasserted when the receive FIFO contains more characters than
* more characters than the trigger, or the MCR RTS bit is cleared. * the trigger, or the MCR RTS bit is cleared. In the case where
* the remote UART is not using CTS auto flow control, we must
* have sufficient FIFO entries for the latency of the remote
* UART to respond. IOW, at least 32 bytes of FIFO.
*/ */
if (up->port.type == PORT_16750) { if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
up->mcr &= ~UART_MCR_AFE; up->mcr &= ~UART_MCR_AFE;
if (termios->c_cflag & CRTSCTS) if (termios->c_cflag & CRTSCTS)
up->mcr |= UART_MCR_AFE; up->mcr |= UART_MCR_AFE;
......
...@@ -47,6 +47,7 @@ struct serial8250_config { ...@@ -47,6 +47,7 @@ struct serial8250_config {
#define UART_CAP_FIFO (1 << 8) /* UART has FIFO */ #define UART_CAP_FIFO (1 << 8) /* UART has FIFO */
#define UART_CAP_EFR (1 << 9) /* UART has EFR */ #define UART_CAP_EFR (1 << 9) /* UART has EFR */
#define UART_CAP_SLEEP (1 << 10) /* UART has IER sleep */ #define UART_CAP_SLEEP (1 << 10) /* UART has IER sleep */
#define UART_CAP_AFE (1 << 11) /* MCR-based hw flow control */
#undef SERIAL_DEBUG_PCI #undef SERIAL_DEBUG_PCI
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment