Commit dbcae5ea authored by Ulrich Hecht's avatar Ulrich Hecht Committed by Simon Horman

arm64: dts: r8a7796: Enable SCIF DMA

Signed-off-by: default avatarUlrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 19d76f3e
...@@ -568,6 +568,9 @@ scif0: serial@e6e60000 { ...@@ -568,6 +568,9 @@ scif0: serial@e6e60000 {
<&cpg CPG_CORE R8A7796_CLK_S3D1>, <&cpg CPG_CORE R8A7796_CLK_S3D1>,
<&scif_clk>; <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x51>, <&dmac1 0x50>,
<&dmac2 0x51>, <&dmac2 0x50>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled"; status = "disabled";
}; };
...@@ -581,6 +584,9 @@ scif1: serial@e6e68000 { ...@@ -581,6 +584,9 @@ scif1: serial@e6e68000 {
<&cpg CPG_CORE R8A7796_CLK_S3D1>, <&cpg CPG_CORE R8A7796_CLK_S3D1>,
<&scif_clk>; <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x53>, <&dmac1 0x52>,
<&dmac2 0x53>, <&dmac2 0x52>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled"; status = "disabled";
}; };
...@@ -607,6 +613,8 @@ scif3: serial@e6c50000 { ...@@ -607,6 +613,8 @@ scif3: serial@e6c50000 {
<&cpg CPG_CORE R8A7796_CLK_S3D1>, <&cpg CPG_CORE R8A7796_CLK_S3D1>,
<&scif_clk>; <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x57>, <&dmac0 0x56>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled"; status = "disabled";
}; };
...@@ -620,6 +628,8 @@ scif4: serial@e6c40000 { ...@@ -620,6 +628,8 @@ scif4: serial@e6c40000 {
<&cpg CPG_CORE R8A7796_CLK_S3D1>, <&cpg CPG_CORE R8A7796_CLK_S3D1>,
<&scif_clk>; <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x59>, <&dmac0 0x58>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled"; status = "disabled";
}; };
...@@ -633,6 +643,9 @@ scif5: serial@e6f30000 { ...@@ -633,6 +643,9 @@ scif5: serial@e6f30000 {
<&cpg CPG_CORE R8A7796_CLK_S3D1>, <&cpg CPG_CORE R8A7796_CLK_S3D1>,
<&scif_clk>; <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
<&dmac2 0x5b>, <&dmac2 0x5a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled"; status = "disabled";
}; };
......
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