Commit dc41fb43 authored by Ralf Baechle's avatar Ralf Baechle

[MIPS] Fix 32-bit kernel by replacing 64-bit-only code.

dclz() expects its 64-bit argument being passed as a single register
but on 32-bit kernels it'll actually be in a register pair.
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 73b76c78
......@@ -469,21 +469,6 @@ void bcm1480_kgdb_interrupt(struct pt_regs *regs)
#endif /* CONFIG_KGDB */
static inline int dclz(unsigned long long x)
{
int lz;
__asm__ (
" .set push \n"
" .set mips64 \n"
" dclz %0, %1 \n"
" .set pop \n"
: "=r" (lz)
: "r" (x));
return lz;
}
extern void bcm1480_timer_interrupt(struct pt_regs *regs);
extern void bcm1480_mailbox_interrupt(struct pt_regs *regs);
extern void bcm1480_kgdb_interrupt(struct pt_regs *regs);
......@@ -536,9 +521,9 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
if (mask_h) {
if (mask_h ^ 1)
do_IRQ(63 - dclz(mask_h), regs);
do_IRQ(fls64(mask_h) - 1, regs);
else
do_IRQ(127 - dclz(mask_l), regs);
do_IRQ(63 + fls64(mask_l), regs);
}
}
}
......@@ -419,21 +419,6 @@ static void sb1250_kgdb_interrupt(struct pt_regs *regs)
#endif /* CONFIG_KGDB */
static inline int dclz(unsigned long long x)
{
int lz;
__asm__ (
" .set push \n"
" .set mips64 \n"
" dclz %0, %1 \n"
" .set pop \n"
: "=r" (lz)
: "r" (x));
return lz;
}
extern void sb1250_timer_interrupt(struct pt_regs *regs);
extern void sb1250_mailbox_interrupt(struct pt_regs *regs);
extern void sb1250_kgdb_interrupt(struct pt_regs *regs);
......@@ -490,6 +475,6 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(),
R_IMR_INTERRUPT_STATUS_BASE)));
if (mask)
do_IRQ(63 - dclz(mask), regs);
do_IRQ(fls64(mask) - 1, regs);
}
}
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