Commit dec0520a authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher

drm/amdgpu: remove inproper workaround for vega10

the workaround is not needed for soc15 ASICs except
for vega10. it is even not needed with latest vega10
vbios.
Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1744fb23
...@@ -956,8 +956,6 @@ struct amdgpu_device { ...@@ -956,8 +956,6 @@ struct amdgpu_device {
/* s3/s4 mask */ /* s3/s4 mask */
bool in_suspend; bool in_suspend;
/* record last mm index being written through WREG32*/
unsigned long last_mm_index;
bool in_gpu_reset; bool in_gpu_reset;
enum pp_mp1_state mp1_state; enum pp_mp1_state mp1_state;
struct mutex lock_reset; struct mutex lock_reset;
......
...@@ -387,10 +387,6 @@ void static inline amdgpu_mm_wreg_mmio(struct amdgpu_device *adev, uint32_t reg, ...@@ -387,10 +387,6 @@ void static inline amdgpu_mm_wreg_mmio(struct amdgpu_device *adev, uint32_t reg,
writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
} }
if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
udelay(500);
}
} }
/** /**
...@@ -406,10 +402,6 @@ void static inline amdgpu_mm_wreg_mmio(struct amdgpu_device *adev, uint32_t reg, ...@@ -406,10 +402,6 @@ void static inline amdgpu_mm_wreg_mmio(struct amdgpu_device *adev, uint32_t reg,
void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
uint32_t acc_flags) uint32_t acc_flags)
{ {
if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
adev->last_mm_index = v;
}
if ((acc_flags & AMDGPU_REGS_KIQ) || (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))) if ((acc_flags & AMDGPU_REGS_KIQ) || (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)))
return amdgpu_kiq_wreg(adev, reg, v); return amdgpu_kiq_wreg(adev, reg, v);
...@@ -464,20 +456,12 @@ u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) ...@@ -464,20 +456,12 @@ u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
*/ */
void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
{ {
if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
adev->last_mm_index = v;
}
if ((reg * 4) < adev->rio_mem_size) if ((reg * 4) < adev->rio_mem_size)
iowrite32(v, adev->rio_mem + (reg * 4)); iowrite32(v, adev->rio_mem + (reg * 4));
else { else {
iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
} }
if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
udelay(500);
}
} }
/** /**
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment