Commit e09745f2 authored by Arnaud Mouiche's avatar Arnaud Mouiche Committed by Mark Brown

ASoC: fsl_ssi: The IPG/5 limitation concerns the bitclk, not the sysclk.

im6sl reference manual 47.7.4:
"
Bit clock - Used to serially clock the data bits in and out of the SSI port.
This clock is either generated internally (from SSI's sys clock) or taken
from external clock source (through the Tx/Rx clock ports).
[...]
Care should be taken to ensure that the bit clock frequency (either
internally generated by dividing the SSI's sys clock or sourced from
external device through Tx/Rx clock ports) is never greater than 1/5
of the ipg_clk (from CCM) frequency.
"

Since, in master mode, the sysclk is a multiple of bitclk, we can
easily reach a high sysclk value, whereas keeping a reasonable bitclk.

ex: 8ch x 16bit x 48kHz = 6144000, requires a 24576000 sysclk (PM=1)
    yet ipg_clk/5 = 66Mhz/5 = 13.2
Signed-off-by: default avatarArnaud Mouiche <arnaud.mouiche@invoxia.com>
Reviewed-by: default avatarFabio Estevam <fabio.estevam@nxp.com>
Tested-by: default avatarCaleb Crome <caleb@crome.org>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 48a260ee
...@@ -670,6 +670,15 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, ...@@ -670,6 +670,15 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
if (IS_ERR(ssi_private->baudclk)) if (IS_ERR(ssi_private->baudclk))
return -EINVAL; return -EINVAL;
/*
* Hardware limitation: The bclk rate must be
* never greater than 1/5 IPG clock rate
*/
if (freq * 5 > clk_get_rate(ssi_private->clk)) {
dev_err(cpu_dai->dev, "bitclk > ipgclk/5\n");
return -EINVAL;
}
baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream)); baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream));
/* It should be already enough to divide clock by setting pm alone */ /* It should be already enough to divide clock by setting pm alone */
...@@ -686,13 +695,6 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, ...@@ -686,13 +695,6 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
else else
clkrate = clk_round_rate(ssi_private->baudclk, tmprate); clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
/*
* Hardware limitation: The bclk rate must be
* never greater than 1/5 IPG clock rate
*/
if (clkrate * 5 > clk_get_rate(ssi_private->clk))
continue;
clkrate /= factor; clkrate /= factor;
afreq = clkrate / (i + 1); afreq = clkrate / (i + 1);
......
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