Commit e1706720 authored by John Hubbard's avatar John Hubbard Committed by Linus Torvalds

phy: fix build breakage: add PHY_MODE_SATA

Commit 49e54187 ("ata: libahci_platform: comply to PHY framework") uses
the PHY_MODE_SATA, but that enum had not yet been added. This caused a
build failure for me, with today's linux.git.

Also, there is a potentially conflicting (mis-named) PHY_MODE_SATA, hiding
in the Marvell Berlin SATA PHY driver.

Fix the build by:

    1) Renaming Marvell's defined value to a more scoped name,
       in order to avoid any potential conflicts: PHY_BERLIN_MODE_SATA.

    2) Adding the missing enum, which was going to be added anyway as part
       of [1].

[1] https://lkml.kernel.org/r/20190108163124.6409-3-miquel.raynal@bootlin.com

Fixes: 49e54187 ("ata: libahci_platform: comply to PHY framework")
Signed-off-by: default avatarJohn Hubbard <jhubbard@nvidia.com>
Acked-by: default avatarJens Axboe <axboe@kernel.dk>
Acked-by: default avatarOlof Johansson <olof@lixom.net>
Cc: Grzegorz Jaszczyk <jaz@semihalf.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent b8c3b899
...@@ -32,7 +32,7 @@ ...@@ -32,7 +32,7 @@
/* register 0x01 */ /* register 0x01 */
#define REF_FREF_SEL_25 BIT(0) #define REF_FREF_SEL_25 BIT(0)
#define PHY_MODE_SATA (0x0 << 5) #define PHY_BERLIN_MODE_SATA (0x0 << 5)
/* register 0x02 */ /* register 0x02 */
#define USE_MAX_PLL_RATE BIT(12) #define USE_MAX_PLL_RATE BIT(12)
...@@ -102,7 +102,8 @@ static int phy_berlin_sata_power_on(struct phy *phy) ...@@ -102,7 +102,8 @@ static int phy_berlin_sata_power_on(struct phy *phy)
/* set PHY mode and ref freq to 25 MHz */ /* set PHY mode and ref freq to 25 MHz */
phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01, phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01,
0x00ff, REF_FREF_SEL_25 | PHY_MODE_SATA); 0x00ff,
REF_FREF_SEL_25 | PHY_BERLIN_MODE_SATA);
/* set PHY up to 6 Gbps */ /* set PHY up to 6 Gbps */
phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25, phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25,
......
...@@ -42,6 +42,7 @@ enum phy_mode { ...@@ -42,6 +42,7 @@ enum phy_mode {
PHY_MODE_PCIE, PHY_MODE_PCIE,
PHY_MODE_ETHERNET, PHY_MODE_ETHERNET,
PHY_MODE_MIPI_DPHY, PHY_MODE_MIPI_DPHY,
PHY_MODE_SATA
}; };
/** /**
......
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