Commit e4e48c47 authored by Vinod Koul's avatar Vinod Koul

Merge branch 'topic/intel' into for-linus

parents b802c841 f7c799e9
This diff is collapsed.
...@@ -15,6 +15,18 @@ ...@@ -15,6 +15,18 @@
#include "internal.h" #include "internal.h"
static struct dw_dma_platform_data mrfld_pdata = {
.nr_channels = 8,
.is_private = true,
.is_memcpy = true,
.is_idma32 = true,
.chan_allocation_order = CHAN_ALLOCATION_ASCENDING,
.chan_priority = CHAN_PRIORITY_ASCENDING,
.block_size = 131071,
.nr_masters = 1,
.data_width = {4},
};
static int dw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pid) static int dw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pid)
{ {
const struct dw_dma_platform_data *pdata = (void *)pid->driver_data; const struct dw_dma_platform_data *pdata = (void *)pid->driver_data;
...@@ -47,6 +59,7 @@ static int dw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pid) ...@@ -47,6 +59,7 @@ static int dw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pid)
return -ENOMEM; return -ENOMEM;
chip->dev = &pdev->dev; chip->dev = &pdev->dev;
chip->id = pdev->devfn;
chip->regs = pcim_iomap_table(pdev)[0]; chip->regs = pcim_iomap_table(pdev)[0];
chip->irq = pdev->irq; chip->irq = pdev->irq;
chip->pdata = pdata; chip->pdata = pdata;
...@@ -95,14 +108,16 @@ static const struct dev_pm_ops dw_pci_dev_pm_ops = { ...@@ -95,14 +108,16 @@ static const struct dev_pm_ops dw_pci_dev_pm_ops = {
}; };
static const struct pci_device_id dw_pci_id_table[] = { static const struct pci_device_id dw_pci_id_table[] = {
/* Medfield */ /* Medfield (GPDMA) */
{ PCI_VDEVICE(INTEL, 0x0827) }, { PCI_VDEVICE(INTEL, 0x0827) },
{ PCI_VDEVICE(INTEL, 0x0830) },
/* BayTrail */ /* BayTrail */
{ PCI_VDEVICE(INTEL, 0x0f06) }, { PCI_VDEVICE(INTEL, 0x0f06) },
{ PCI_VDEVICE(INTEL, 0x0f40) }, { PCI_VDEVICE(INTEL, 0x0f40) },
/* Merrifield iDMA 32-bit (GPDMA) */
{ PCI_VDEVICE(INTEL, 0x11a2), (kernel_ulong_t)&mrfld_pdata },
/* Braswell */ /* Braswell */
{ PCI_VDEVICE(INTEL, 0x2286) }, { PCI_VDEVICE(INTEL, 0x2286) },
{ PCI_VDEVICE(INTEL, 0x22c0) }, { PCI_VDEVICE(INTEL, 0x22c0) },
......
...@@ -202,6 +202,7 @@ static int dw_probe(struct platform_device *pdev) ...@@ -202,6 +202,7 @@ static int dw_probe(struct platform_device *pdev)
pdata = dw_dma_parse_dt(pdev); pdata = dw_dma_parse_dt(pdev);
chip->dev = dev; chip->dev = dev;
chip->id = pdev->id;
chip->pdata = pdata; chip->pdata = pdata;
chip->clk = devm_clk_get(chip->dev, "hclk"); chip->clk = devm_clk_get(chip->dev, "hclk");
......
...@@ -3,15 +3,19 @@ ...@@ -3,15 +3,19 @@
* *
* Copyright (C) 2005-2007 Atmel Corporation * Copyright (C) 2005-2007 Atmel Corporation
* Copyright (C) 2010-2011 ST Microelectronics * Copyright (C) 2010-2011 ST Microelectronics
* Copyright (C) 2016 Intel Corporation
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation. * published by the Free Software Foundation.
*/ */
#include <linux/bitops.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/dmaengine.h> #include <linux/dmaengine.h>
#include <linux/io-64-nonatomic-hi-lo.h>
#include "internal.h" #include "internal.h"
#define DW_DMA_MAX_NR_REQUESTS 16 #define DW_DMA_MAX_NR_REQUESTS 16
...@@ -85,9 +89,9 @@ struct dw_dma_regs { ...@@ -85,9 +89,9 @@ struct dw_dma_regs {
DW_REG(ID); DW_REG(ID);
DW_REG(TEST); DW_REG(TEST);
/* reserved */ /* iDMA 32-bit support */
DW_REG(__reserved0); DW_REG(CLASS_PRIORITY0);
DW_REG(__reserved1); DW_REG(CLASS_PRIORITY1);
/* optional encoded params, 0x3c8..0x3f7 */ /* optional encoded params, 0x3c8..0x3f7 */
u32 __reserved; u32 __reserved;
...@@ -99,6 +103,17 @@ struct dw_dma_regs { ...@@ -99,6 +103,17 @@ struct dw_dma_regs {
/* top-level parameters */ /* top-level parameters */
u32 DW_PARAMS; u32 DW_PARAMS;
/* component ID */
u32 COMP_TYPE;
u32 COMP_VERSION;
/* iDMA 32-bit support */
DW_REG(FIFO_PARTITION0);
DW_REG(FIFO_PARTITION1);
DW_REG(SAI_ERR);
DW_REG(GLOBAL_CFG);
}; };
/* /*
...@@ -170,8 +185,9 @@ enum dw_dma_msize { ...@@ -170,8 +185,9 @@ enum dw_dma_msize {
#define DWC_CTLL_LLP_S_EN (1 << 28) /* src block chain */ #define DWC_CTLL_LLP_S_EN (1 << 28) /* src block chain */
/* Bitfields in CTL_HI */ /* Bitfields in CTL_HI */
#define DWC_CTLH_DONE 0x00001000 #define DWC_CTLH_BLOCK_TS_MASK GENMASK(11, 0)
#define DWC_CTLH_BLOCK_TS_MASK 0x00000fff #define DWC_CTLH_BLOCK_TS(x) ((x) & DWC_CTLH_BLOCK_TS_MASK)
#define DWC_CTLH_DONE (1 << 12)
/* Bitfields in CFG_LO */ /* Bitfields in CFG_LO */
#define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */ #define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */
...@@ -214,6 +230,33 @@ enum dw_dma_msize { ...@@ -214,6 +230,33 @@ enum dw_dma_msize {
/* Bitfields in CFG */ /* Bitfields in CFG */
#define DW_CFG_DMA_EN (1 << 0) #define DW_CFG_DMA_EN (1 << 0)
/* iDMA 32-bit support */
/* Bitfields in CTL_HI */
#define IDMA32C_CTLH_BLOCK_TS_MASK GENMASK(16, 0)
#define IDMA32C_CTLH_BLOCK_TS(x) ((x) & IDMA32C_CTLH_BLOCK_TS_MASK)
#define IDMA32C_CTLH_DONE (1 << 17)
/* Bitfields in CFG_LO */
#define IDMA32C_CFGL_DST_BURST_ALIGN (1 << 0) /* dst burst align */
#define IDMA32C_CFGL_SRC_BURST_ALIGN (1 << 1) /* src burst align */
#define IDMA32C_CFGL_CH_DRAIN (1 << 10) /* drain FIFO */
#define IDMA32C_CFGL_DST_OPT_BL (1 << 20) /* optimize dst burst length */
#define IDMA32C_CFGL_SRC_OPT_BL (1 << 21) /* optimize src burst length */
/* Bitfields in CFG_HI */
#define IDMA32C_CFGH_SRC_PER(x) ((x) << 0)
#define IDMA32C_CFGH_DST_PER(x) ((x) << 4)
#define IDMA32C_CFGH_RD_ISSUE_THD(x) ((x) << 8)
#define IDMA32C_CFGH_RW_ISSUE_THD(x) ((x) << 18)
#define IDMA32C_CFGH_SRC_PER_EXT(x) ((x) << 28) /* src peripheral extension */
#define IDMA32C_CFGH_DST_PER_EXT(x) ((x) << 30) /* dst peripheral extension */
/* Bitfields in FIFO_PARTITION */
#define IDMA32C_FP_PSIZE_CH0(x) ((x) << 0)
#define IDMA32C_FP_PSIZE_CH1(x) ((x) << 13)
#define IDMA32C_FP_UPDATE (1 << 26)
enum dw_dmac_flags { enum dw_dmac_flags {
DW_DMA_IS_CYCLIC = 0, DW_DMA_IS_CYCLIC = 0,
DW_DMA_IS_SOFT_LLP = 1, DW_DMA_IS_SOFT_LLP = 1,
...@@ -270,6 +313,7 @@ static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan) ...@@ -270,6 +313,7 @@ static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
struct dw_dma { struct dw_dma {
struct dma_device dma; struct dma_device dma;
char name[20];
void __iomem *regs; void __iomem *regs;
struct dma_pool *desc_pool; struct dma_pool *desc_pool;
struct tasklet_struct tasklet; struct tasklet_struct tasklet;
...@@ -293,6 +337,11 @@ static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw) ...@@ -293,6 +337,11 @@ static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
#define dma_writel(dw, name, val) \ #define dma_writel(dw, name, val) \
dma_writel_native((val), &(__dw_regs(dw)->name)) dma_writel_native((val), &(__dw_regs(dw)->name))
#define idma32_readq(dw, name) \
hi_lo_readq(&(__dw_regs(dw)->name))
#define idma32_writeq(dw, name, val) \
hi_lo_writeq((val), &(__dw_regs(dw)->name))
#define channel_set_bit(dw, reg, mask) \ #define channel_set_bit(dw, reg, mask) \
dma_writel(dw, reg, ((mask) << 8) | (mask)) dma_writel(dw, reg, ((mask) << 8) | (mask))
#define channel_clear_bit(dw, reg, mask) \ #define channel_clear_bit(dw, reg, mask) \
......
...@@ -23,6 +23,7 @@ struct dw_dma; ...@@ -23,6 +23,7 @@ struct dw_dma;
/** /**
* struct dw_dma_chip - representation of DesignWare DMA controller hardware * struct dw_dma_chip - representation of DesignWare DMA controller hardware
* @dev: struct device of the DMA controller * @dev: struct device of the DMA controller
* @id: instance ID
* @irq: irq line * @irq: irq line
* @regs: memory mapped I/O space * @regs: memory mapped I/O space
* @clk: hclk clock * @clk: hclk clock
...@@ -31,6 +32,7 @@ struct dw_dma; ...@@ -31,6 +32,7 @@ struct dw_dma;
*/ */
struct dw_dma_chip { struct dw_dma_chip {
struct device *dev; struct device *dev;
int id;
int irq; int irq;
void __iomem *regs; void __iomem *regs;
struct clk *clk; struct clk *clk;
......
...@@ -41,6 +41,7 @@ struct dw_dma_slave { ...@@ -41,6 +41,7 @@ struct dw_dma_slave {
* @is_private: The device channels should be marked as private and not for * @is_private: The device channels should be marked as private and not for
* by the general purpose DMA channel allocator. * by the general purpose DMA channel allocator.
* @is_memcpy: The device channels do support memory-to-memory transfers. * @is_memcpy: The device channels do support memory-to-memory transfers.
* @is_idma32: The type of the DMA controller is iDMA32
* @chan_allocation_order: Allocate channels starting from 0 or 7 * @chan_allocation_order: Allocate channels starting from 0 or 7
* @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0. * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
* @block_size: Maximum block size supported by the controller * @block_size: Maximum block size supported by the controller
...@@ -53,6 +54,7 @@ struct dw_dma_platform_data { ...@@ -53,6 +54,7 @@ struct dw_dma_platform_data {
unsigned int nr_channels; unsigned int nr_channels;
bool is_private; bool is_private;
bool is_memcpy; bool is_memcpy;
bool is_idma32;
#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ #define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */
#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */ #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */
unsigned char chan_allocation_order; unsigned char chan_allocation_order;
......
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