Commit e537c994 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher

drm/amdgpu: acquire available gfx queues

currently, amdgpu will owns the first gfx queue of each pipe
they are:
me:0 pipe:0 queue:0
me:0 pipe:1 queue:0
Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarJack Xiao <jack.xiao@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Acked-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cf02b03f
......@@ -199,6 +199,30 @@ void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
}
void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev)
{
int i, queue, pipe, me;
for (i = 0; i < AMDGPU_MAX_GFX_QUEUES; ++i) {
queue = i % adev->gfx.me.num_queue_per_pipe;
pipe = (i / adev->gfx.me.num_queue_per_pipe)
% adev->gfx.me.num_pipe_per_me;
me = (i / adev->gfx.me.num_queue_per_pipe)
/ adev->gfx.me.num_pipe_per_me;
if (me >= adev->gfx.me.num_me)
break;
/* policy: amdgpu owns the first queue per pipe at this stage
* will extend to mulitple queues per pipe later */
if (me == 0 && queue < 1)
set_bit(i, adev->gfx.me.queue_bitmap);
}
/* update the number of active graphics rings */
adev->gfx.num_gfx_rings =
bitmap_weight(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
}
static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev,
struct amdgpu_ring *ring)
{
......
......@@ -335,6 +335,8 @@ int amdgpu_gfx_compute_mqd_sw_init(struct amdgpu_device *adev,
void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device *adev);
void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev);
int amdgpu_gfx_queue_to_bit(struct amdgpu_device *adev, int mec,
int pipe, int queue);
void amdgpu_gfx_bit_to_queue(struct amdgpu_device *adev, int bit,
......
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